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Port Handshake
Register
TM(0,1) (Transfer Mode)
Bits 2 and 3
EI (Enable Inhibit)
HT(5-7) (Handshake Type)
116 Agilent E1330B Digital I/O Module Register Information
The Port Handshake Register determines the type of handshake protocol
used for the port data transfers and how the data is transferred from the
Digital I/O module to the mainframe on the VXIbus.
Port Address (0–3) base+18
7
6
HT2
HT1
These bits control the transfer mode for the port between the Digital I/O
module and the VXIbus as shown in Table B-3.
Transfer Mode
Flag Driven
Interrupt Driven
Fast Handshake
The three transfer modes are used to transfer data between the VXIbus and
the Digital I/O module:
•
Flag Driven – the mainframe polls the Data Register Ready bit (bit 0,
Port Transfer Control Register). When this bit is set, it reads data from
the Port Data Register or writes data to the Port Data Register.
•
Interrupt Driven – the peripheral sets bit 1 of the Port Status/Control
Register and the Digital I/O module interrupts the VXIbus for data
transfer with the mainframe.
•
Fast Handshake – the peripheral talks directly with the VXIbus's Data
Acknowledge Line to transfer data between the Port Data Registers
and the VXIbus.
Are not used.
This bit, if set to "1", enables the STS line to inhibit a transfer cycle during
a transfer. If bit 4 is set, the transfer is inhibited when the peripheral puts STS
in the BUSY state and resumes when STS returns to the READY state.
These bits determine the type of handshake for port input and output
transfers as shown in Table B-4.
, base+19
16
16
5
4
3
HT0
EI
—
Table B-3. Transfer Mode
TM1 Bit 1
0
0
1
, base+1A
, base+1B
16
16
2
1
0
—
TM1
TM0
TM0 Bit 0
0
1
0
Appendix B
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