Chipset Features Setup - SOYO SY-7VCA User Manual

BIOS Setup Utility
After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.

3-4.1 CHIPSET FEATURES SETUP

CHIPSET
FEATURES
Bank 0/1, 2/3,
4/5 DRAM
Timing
SDRAM Cycle
Length
DRAM Clock
Memory Hole
P2C/C2P
Concurrency
Fast R-W
Turn Around
Setting Description
SDRAM This item allows you to select the
10ns value in this field, depending on
whether the board has paged
SDRAM
DRAMs or EDO (extended data
8ns
output) DRAMs.
Normal
Medium
Fast
Turbo
2 When synchronous DRAM is
3 installed, the number of clock cycles
of CAS latency depends on the
DRAM timing. Do not reset this
field from the default value
specified by the system designer.
HCLK-
This item allows you to control the
33M
DRAM speed.
Host Clock
Disabled
Enabled Some interface cards will map their
ROM address to this area. If this
occurs, select [Enabled] in this field.
Disabled This item allows you to
enable/disable the PCI to CPU, CPU
Enabled
to PCI concurrency
Disabled This item controls the DRAM
timing. It allows you to enable/
Enabled disable the fast read/write turn
around.
69
SY-7VCA
Note
Default
Default
Default
Default
Default
Default