Block Diagram - Fujitsu MB15C02 Datasheet

Single serial input pll frequency synthesizer
Table of Contents

Advertisement

■ BLOCK DIAGRAM

V
DD
Intermittent
mode control
circuit
Clock
Data
Control
register
LE
f
in
PS
LD
Lock detector
Do
Programmable
reference divider
Binary 14-bit
reference counter
14
14-bit latch
14
18-bit shift register
18
18-bit latch
6
Binary 6-bit
Binary 12-bit
Prescaler
swallow
programma-
counter
ble counter
Control circuit
oscillator
fr
Phase
comparator
fp
12
MB15C02
Crystal
V
SS
circuit
OSC
IN
OSC
OUT
TEST
FC
Output
φP
control
circuit
Output
φR
control
circuit
Charge
V
P
pump
5

Advertisement

Table of Contents
loading

Table of Contents