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Fujitsu MB15C02 Datasheet

Single serial input pll frequency synthesizer.
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FUJITSU MICROELECTRONICS
DATA SHEET
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C02
■ DESCRIPTION
The Fujitsu Microelectronics MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a
prescaler. A 64/65 division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C02 is suitable for mobile communications, such as paging systems.
■ FEATURES
• High frequency operation: 220 MHz max
• Single power supply : V
• Power saving function
• Pulse swallow function: 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 6-bit swallow counter: 0 to 63
- Binary 12-bit programmable counter: 5 to 4,095
• Wide operating temperature: Ta = –20 to 60°C
■ PACKAGES
16-pin, Plastic SSOP
Copyright©1999-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
1999.2
@V
330 MHz max
@V
450 MHz max
@V
= 1.0 to 1.5 V
DD
(FPT-16P-M05)
= 1.0 V to 1.5 V
DD
= 1.2 V to 1.5 V
DD
= 1.3 V to 1.5 V
DD
20-pin, Plastic SSOP
(FPT-20P-M03)
DS04–21348–3Ea
1

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   Summary of Contents for Fujitsu MB15C02

  • Page 1

    MB15C02 ■ DESCRIPTION The Fujitsu Microelectronics MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65 division is available for the prescaler that enables pulse swallow operation. This operates with a supply voltage of 1.0 V (min.).

  • Page 2: Pin Assignments

    MB15C02 ■ PIN ASSIGNMENTS SSOP-20 pin Clock Data TEST View φP φR (FPT-20P-M03) SSOP-16 pin Clock Data TEST View φP φR (FPT-16P-M05)

  • Page 3: Pin Descriptions

    MB15C02 ■ PIN DESCRIPTIONS Pin no. Descriptions SSOP SSOP name – Power supply voltage Clock input for the shift register.(Schmitt trigger input) Clock Data is shifted into the shift register on the rising edge of the clock. – – No connection Data Serial data input using binary code.(Schmitt trigger input) Load enable signal input (Schmitt trigger input)

  • Page 4

    MB15C02 (Continued) Pin no. Descriptions SSOP SSOP name Oscillator output. Connection for an external crystal. – – No connection Programmable reference divider input. Oscillator input. Clock can be input to OSC from outside. In the case, please leave OSC pin open and make connection with OSC as AC coupling.

  • Page 5: Block Diagram

    MB15C02 ■ BLOCK DIAGRAM Crystal oscillator circuit Programmable reference divider Binary 14-bit reference counter Intermittent mode control circuit 14-bit latch Clock Phase TEST comparator Output 18-bit shift register φP control Data Control circuit register Output φR control 18-bit latch circuit Binary 6-bit Binary 12-bit Charge...

  • Page 6: Absolute Maximum Ratings

    MB15C02 ■ ABSOLUTE MAXIMUM RATINGS Rating Parameter Symbol Unit Remark Min. Max. Power supply voltage GND–0.5 +2.0 Input voltage GND–0.5 +0.5 Output voltage GND–0.5 +0.5 Output current –10 °C Storage temperature –40 +125 WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings.

  • Page 7: Electrical Characteristics

    MB15C02 ■ ELECTRICAL CHARACTERISTICS (For 220 MHz :V = Vp = 1.0 to 1.5 V, Ta = –20 to +60°C) (For 330 MHz :V = Vp = 1.2 to 1.5 V, Ta = –20 to +60°C) (For 450 MHz :V = Vp = 1.3 to 1.5 V, Ta = –20 to +60°C) Value Parameter...

  • Page 8

    MB15C02 ■ FUNCTION DESCRIPTIONS 1. Pulse Swallow Function The divide ratio can be calculated using the following equation: = [(M × N) + A] × f ÷ R (A < N) : Output frequency of external voltage controlled oscillator (VCO) : Preset divide ratio of binary 12-bit programmable counter (5 to 4,095) : Preset divide ratio of binary 6-bit swallow counter (0 to 63) : Output frequency of the reference frequency oscillator...

  • Page 9

    MB15C02 Divide ratio range: Prescaler : M = 64, M+1=65 Swallow counter : A = 0 to 63 Programmable counter : N = 5 to 4095 The MB15C02 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable counters must satisfy the relationship N>A.

  • Page 10

    MB15C02 (b) Charge pump The charge pump is available in two forms: internal external. Internal charge pump output (Do) External charge pump outputs (φR, φP) (c) Phase comparator input/output waveforms The phase comparator outputs logic levels summarized in Table 1, according to the phase error between fr and fp.

  • Page 11

    MB15C02 (d) Lock detector The lock detector detects the lock and unlock states of the PLL. The lock detector outputs “H” when the PLL enters the lock state and outputs “L” when the PLL enters the unlock state as shown in Figure 2. When PS = “L”, the lock detector outputs “H”...

  • Page 12

    MB15C02 4. Setting the Divide Ratio (1) Serial data format The format of the serial data is shown is Figure 3. The serial data is composed of a control bit and divide ratio setting data. The control bit selects the programmable divider or programmable reference divider. In case of the programmable divider, serial data consists of 18 bits(6 bits for the swallow counter and 12 bits for the programmable counter) and 1 control bit as shown in Figure 3.1.

  • Page 13

    MB15C02 (2) The flow of serial data Serial data is received via data pin in synchronization with the clock input and loaded into shift register which contains the divide ratio setting data and into the control register which contains the control bit. The logical product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the latches.

  • Page 14

    MB15C02 (4) Setting the divide ratio for the programmable reference divider Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set to 1. Table.3 Divide ratio for the programmable reference divider Divide ratio ⋅...

  • Page 15

    MB15C02 Since the divide rations are unpredictable when the MB15C02 is turned on, it is necessary to initialize the divide ratio for both dividers at power-on time. As shown in Figure 6, after setting the divide ratio for one of the dividers (e.g., programmable reference divider), set LE to “H”...

  • Page 16

    MB15C02 ■ TYPICAL CHARACTERISTICS 1. fin Input Sensitivity fin input frequency vs. Input sensitivity 20.0 Ta = +25°C 10.0 −10.0 −20.0 −30.0 −40.0 = 1.0 V = 1.2 V −50.0 = 1.3 V = 1.5 V −60.0 1000 fin input frequency (MHz) 2.

  • Page 17

    MB15C02 3. fin Power Supply Voltage Power supply voltage vs. fin input frequency (MHz) 1000 Ta = +25°C Vfin = −2.0 (dBm) Power supply voltage (V) 4. OSC Power Supply Voltage Power supply voltage vs. OSC input frequency Ta = +25°C Vfin = −2.0 (dBm) Power supply voltage (V)

  • Page 18

    MB15C02 5. I Power Supply Current Input frequency vs. power supply current Ta = +25°C = 1.0 V = 1.2 V = 1.3 V = 1.5 V 1000 Input frequency (MHz)

  • Page 19

    MB15C02 6. Do (Charge Pump) Power Supply Voltage ) vs. I (at V = 0.2 V) Ta = +25°C ) vs. I (at V – 0.2 V) –5.0 Ta = +25°C –4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5...

  • Page 20

    MB15C02 7. Spectrum Wave Form ∆MKR −85.50 dB ATTEN 10 dB UAUG 16 RL 0 dBm 10dB/ 25.0 kHz • LOCK Frequency : 286.0 MHz (fr = 25 kHz) • V = 1.2 V, V = 1.2 V ∆MKR Ta = +25°C 25.0 kHz −85.50 dB CENTER 286.0000 MHz...

  • Page 21

    MB15C02 8. Lock Up Time • LOCK Frequency: 290.0 MHz to 286.0 MHz (fr = 25 kHz) • V = 1.2 V, V = 1.2 V, Ta = +25°C 290.0 MHz → 286.0 MHz, within ± 1 kHz 4.00 ms ∆MKr x : 3.99999984 ms A euts N/A...

  • Page 22: Usage Precautions

    MB15C02 (Continued) • LOCK Frequency: PS on to 286.0 MHz (fr = 25 kHz) • V = 1.2 V, V = 1.2 V, Ta = +25°C PS ON → 286.0 MHz, within ± 1 kHz 2.00 ms ∆MKr x : 1.99999978 ms A euts N/A y : −680 Hz 286.0050...

  • Page 23: Package Dimensions

    4.40±0.10 6.40±0.20 5.40(.213) (.173±.004) (.252±.008) "A" +0.10 +0.05 Details of "A" part 0.65±0.12 0.22 0.15 –0.05 –0.02 (.0256±.0047) +.004 +.002 .009 .006 –.002 –.001 0.10±0.10(.004±.004) (STAND OFF) 10° 0.50±0.20 4.55(.179)REF (.020±.008) Dimensions in mm (inches) 1994 FUJITSU LIMITED F16013S-2C-4 (Continued)

  • Page 24

    INDEX 4.40±0.10 6.40±0.20 5.40(.213) (.173±.004) (.252±.008) "A" +0.10 +0.05 Details of "A" part 0.65±0.12 0.22 0.15 –0.05 –0.02 (.0256±.0047) +.004 +.002 .009 .006 –.002 –.001 0.10±0.10(.004±.004) (STAND OFF) 10° 0.50±0.20 5.85(.230)REF (.020±.008) Dimensions in mm (inches) 1994 FUJITSU LIMITED F20012S-2C-4...

  • Page 25

    MB15C02 MEMO...

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    MB15C02 MEMO...

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    MB15C02 MEMO...

  • Page 28

    (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

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