Fujitsu MB15C02 Datasheet page 14

MB15C02
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set
to 1.
Table.3 Divide ratio for the programmable reference divider
Divide
R
ratio
0
(R)
5 1
6 0
⋅ ⋅
16383 1
(5) Setting data input timing
The MB15C02 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data
bits are effective.
To set the divide ratio for the MB15C02 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
(>1 µs): Data setup time
t
1
(>1 µs): LE setup time to the rising edge of last clock
t
4
Data
Clock
LE
14
R R R R
1 2 3 4
0 1 0 0
1 1 0 0
⋅ ⋅ ⋅ ⋅
1 1 1 1
(>1 µs): Data hold time
t
2
t2
t1
Figure 5. Serial data input timing
R R R R
5 6 7 8
0 0 0 0
0 0 0 0
⋅ ⋅ ⋅ ⋅
1 1 1 1
(> µs): Clock pulse width
t
3
(>1 µs): LE pulse width
t
5
t3
R R R R
9 10 11 12
0 0 0 0
0 0 0 0
⋅ ⋅ ⋅ ⋅
1 1 1 1
t4
t5
R
13
0
0
⋅
1