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Freescale Semiconductor MPC860T User Manual

(rev. d) fast ethernet controller
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Freescale Semiconductor, Inc.
MPC860T (Rev. D) Fast Ethernet
Controller
Supplement to the MPC860 PowerQUICC™ User's Manual
MPC860TAD/D
Rev. 0.8, 09/1999
ª
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com

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Summary of Contents for Freescale Semiconductor MPC860T

  • Page 1 Freescale Semiconductor, Inc. MPC860T (Rev. D) Fast Ethernet Controller Supplement to the MPC860 PowerQUICC™ User’s Manual MPC860TAD/D Rev. 0.8, 09/1999 ª PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.com...
  • Page 2 Freescale Semiconductor, Inc. DigitalDNA and Mfax are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. C is a registered trademark of Philips Semiconductors This document contains information on a new product under development.

  • Page 3: Table Of Contents

    Freescale Semiconductor, Inc. CONTENTS Paragraph Page Title Number Number Chapter 1 Overview Document Revision History................. 1-1 Overview......................1-1 Comparison with the MPC860................1-2 Features ........................ 1-2 1.4.1 MPC860TBlock Diagram ................1-3 1.4.2 SIU Interrupt Configuration................1-5 Glueless System Design..................1-5...
  • Page 4 Freescale Semiconductor, Inc. CONTENTS Paragraph Page Title Number Number Chapter 4 Parallel I/O Ports Port D Pin Functions.....................4-1 4.1.1 Port D Registers....................4-2 4.1.2 Enabling MII Mode ..................4-2 Chapter 5 SDMA Bus Arbitration and Transfers Overview ......................5-1 The SDMA Registers....................5-1 5.2.1 SDMA Configuration Register (SDCR)............5-2...
  • Page 5 Freescale Semiconductor, Inc. CONTENTS Paragraph Page Title Number Number 6.3.1 Hardware Initialization...................6-22 6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN]) ......6-22 6.3.2.1 Descriptor Controller Initialization ............6-23 6.3.2.2 User Initialization (after Asserting ECNTRL[ETHER_EN]) ....6-23 Buffer Descriptors (BDs) ...................6-24 6.4.1 Ethernet Receive Buffer Descriptor (RxBD) ..........6-24 6.4.2...
  • Page 6 Freescale Semiconductor, Inc. CONTENTS Paragraph Page Title Number Number MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.com...
  • Page 7 Freescale Semiconductor, Inc. ILLUSTRATIONS Figure Page Title Number Number MPC860T Block Diagram .................. 1-4 MPC860T Interrupt Structure ................1-5 MPC860T Serial Configuration................1-6 Ethernet Address Recognition Flowchart ............3-5 SDMA Bus Arbitration ..................5-1 SDMA Configuration Register (SDCR) ............. 5-2 ADDR_LOW Register..................
  • Page 8 Freescale Semiconductor, Inc. ILLUSTRATIONS Figure Page Title Number Number viii MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.com...
  • Page 9 Freescale Semiconductor, Inc. TABLES Table Page Title Number Number Document Revision History................1-1 FEC Signal Descriptions..................2-1 MII Signals......................3-1 Serial Mode Connections to the External Transceiver ........3-2 Transmission Errors .................... 3-7 Reception Errors ....................3-8 Port D Pin Assignment..................4-2 SDCR Field Descriptions..................
  • Page 10 Freescale Semiconductor, Inc. TABLES Table Page Title Number Number 6-27 Receive Buffer Descriptor (RxBD) Field Description........6-25 6-29 Transmit Buffer Descriptor (TxBD) Field Descriptions........6-26 MII Receive Signal Timing ................7-2 MII Transmit Signal Timing................7-2 MII Async Inputs Signal Timing ................ 7-3 MII Serial Management Channel Timing ............

  • Page 11: Overview

    Freescale Semiconductor, Inc. Chapter 1 Overview This chapter provides an overview of Rev. D of the MPC860T, focussing primarily on the Fast Ethernet controller (FEC). It provides a discussion of its basic features and a general look at how the MPC860T can be implemented. This document is provided as a supplement to the MPC860 PowerQUICC UserÕs Manual.

  • Page 12: Comparison With The Mpc860

    Freescale Semiconductor, Inc. The MPC860T integrates three separate processing blocks. The Þrst two, common with all MPC860 devices, are as follows: ¥ A high-performance PowerPCª core that can be used as a general purpose processor for application programming ¥ A RISC engine embedded in the communications processor module (CPM) designed to provide the communications protocol processing provided by the MPC860MH.

  • Page 13: Mpc860Tblock Diagram

    Freescale Semiconductor, Inc. management of transmit and receive buffer memory ¥ 10/100 base-T media access control (MAC) features Ñ Address recognition for broadcast, single station address, promiscuous mode, and multicast hashing Ñ Full support of media-independent interface (MII) Ñ Interrupts supported per frame or per buffer (selectable buffer interrupt functionality using the I bit is not supported however.)

  • Page 14: Mpc860T Block Diagram

    Freescale Semiconductor, Inc. 4-KByte Instruction System Interface Unit (SIU) Unified Instruction Cache Memory Controller Instruction MMU Embedded Internal External PowerPC Bus Interface Bus Interface Processor 4-KByte Unit Unit Load/Store Core Data Cache System Functions Data MMU Real-Time Clock PCMCIA-ATA Interface...

  • Page 15: Glueless System Design

    Freescale Semiconductor, Inc. in memory management of transmit and receive data frames. External memory (DRAM) is inexpensive, and because BD rings in external memory have no inherent size limitations, memory management easily can be optimized to system needs. 1.4.2 SIU Interrupt ConÞguration As shown in Figure 1-2, the SIU receives interrupts from internal sources, such as the FEC and other modules and external pins, IRQ[0Ð7].

  • Page 16: Mpc860T Serial Configuration

    Freescale Semiconductor, Inc. Figure 1-3 shows the glueless connection of the serial channels to physical layer framers and transceivers. MPC8xx 100Base-T Transceiver “7-wire” interface 10Base-T SCC1 (Ethernet) Transceiver SCC2 (QMC) T1 Framer SCC3 (QMC) RS-232 SCC4 (UART) Transceiver Figure 1-3. MPC860T Serial Configuration MPC860T (Rev.

  • Page 17: Fec External Signals

    Freescale Semiconductor, Inc. Chapter 2 FEC External Signals This chapter contains brief descriptions of the MPC860T FEC input and output signals in their functional groups. 2.1 Signal Descriptions The MPC860T system bus signals consist of all the lines that interface with the external bus.
  • Page 18 Freescale Semiconductor, Inc. Table 2-1. FEC Signal Descriptions (Continued) Name Description Number PD[12] General-purpose I/O port D bit 12ÑThis is bit 12 of the general-purpose I/O port D. L1RSYNCB L1RSYNCBÑInput receive data sync signal to the TDM channel B. MII_MDC MII management data clockÑOutput clock provides a timing reference to the PHY for data...
  • Page 19 Freescale Semiconductor, Inc. Table 2-1. FEC Signal Descriptions (Continued) Name Description Number PD[4] General-purpose I/O port D bit 4ÑThis is bit 4 of the general-purpose I/O port D. REJECT3 Reject 3ÑThis input to SCC3 allows a CAM to reject the current Ethernet frame after it MII_TXD[2] determines the frame address did not match.
  • Page 20 Freescale Semiconductor, Inc. MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.com...

  • Page 21: Fast Ethernet Controller Operation

    Freescale Semiconductor, Inc. Chapter 3 Fast Ethernet Controller Operation This chapter discusses the operation of the FEC. 3.1 Transceiver Connection The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface 10-Mbps Ethernet. interface mode selected R_CNTRL[MII_MODE], described in Section 6.2.20, ÒReceive Control Register...

  • Page 22: Fec Frame Transmission

    Freescale Semiconductor, Inc. Table 3-2. Serial Mode Connections to the External Transceiver Signal Description FEC Signal Name Transmit clock TX_CLK Transmit enable TX_EN Transmit data TXD0 Collision Receive clock RX_CLK Receive enable RX_DV Receive Data RXD0 Unused 860T inputsÑTie to ground RX_ER, CRS, RXD[3:1] Unused 860T outputsÑIgnore...

  • Page 23: Fec Frame Reception

    Freescale Semiconductor, Inc. (I_EVENT[BABT] = 1); however, the entire frame is sent (no truncation). Whether buffer or frame interrupts can be generated is determined by I_MASK settings. To pause transmission, set the graceful transmit stop bit, X_CNTRL[GTS]. When GTS is set, the FEC transmitter stops immediately if no transmission is in progress or continues transmission until the current frame either Þnishes or terminates with a collision.

  • Page 24: Cam Interface

    Freescale Semiconductor, Inc. of the frame to the associated data buffer. R_BUFF_SIZE[R_BUFF_SIZE] determines buffer length, which should be at least 128 bytes. R_BUFF_SIZE must be quad-word (16-byte) aligned. During reception, the FEC checks for a frame that is either too short or too long. When the frame ends (CRS is negated), the receive CRC Þeld is checked and written to the data...

  • Page 25: Hash Table Algorithm

    Freescale Semiconductor, Inc. broadcast address. If it is, the frame is accepted unconditionally; otherwise (multicast address) a hash table lookup is performed using the 64-entry hash table deÞned in the hash table registers. In promiscuous mode (R_CNTRL[PROM] = 1), the FEC receives all the incoming frames regardless of their address.

  • Page 26: Inter-Packet Gap Time

    Freescale Semiconductor, Inc. of the CRC-encoded result to generate a number between 0 and 63. Bit 31 of the CRC result selects HASH_TABLE_HIGH (bit 31 = 1) or HASH_TABLE_LOW (bit 31 = 0). Bits 30Ð26 of the CRC result select the bit in the selected register.

  • Page 27: Internal And External Loopback

    Freescale Semiconductor, Inc. 3.10 Internal and External Loopback The FEC supports Both internal and external loopback. In loopback mode, both FIFOs are used and the FEC operates in full-duplex fashion. Both internal and external loopback are conÞgured through R_CNTRL[LOOP, DRT].
  • Page 28 Freescale Semiconductor, Inc. Table 3-4. Reception Errors Error Description Overrun Error The FEC maintains an internal FIFO for receiving data. If a receiver FIFO overrun occurs, the FEC closes the buffer and sets RxBD[OV]. Non-Octet The FEC handles up to seven dribbling bits when the receive frame terminates nonoctet aligned and Error it checks the CRC of the frame on the last octet boundary.

  • Page 29: Parallel I/O Ports

    Freescale Semiconductor, Inc. Chapter 4 Parallel I/O Ports This chapter shows how to use port D pin multiplexing to support Fast Ethernet controller (FEC) operations. 4.1 Port D Pin Functions Each of the 13 port D pins is independently conÞgured as a general-purpose I/O pin if the corresponding port D pin assignment register (PDPAR) bit is cleared.

  • Page 30: Port D Registers

    Freescale Semiconductor, Inc. Table 4-1 shows the port D pin assignments. Table 4-1. Port D Pin Assignment Signal Function Signal PDPAR=1 Input to On-Chip PDPAR = 0 Peripherals PDDIR=0 PDDIR=1 PD15 PORT D15 L1TSYNCA MII-RXD3 (I) L1TSYNCA=GND PD14 PORT D14...

  • Page 31: Sdma Bus Arbitration And Transfers

    Freescale Semiconductor, Inc. Chapter 5 SDMA Bus Arbitration and Transfers This chapter describes SDMA functions speciÞc to the MPC860T, particularly where the functionality differs from the MPC860. For a full discussion of SDMA bus arbitration and transfers, refer to the MPC860 PowerQUICC UserÕs Manual.

  • Page 32: Sdma Configuration Register (Sdcr)

    Freescale Semiconductor, Inc. 5.2.1 SDMA ConÞguration Register (SDCR) The SDMA conÞguration register (SDCR), shown in Figure 5-2, is used to conÞgure all 16 SDMA channels. It is always read/write in supervisor mode, although writing to the SDCR is not recommended unless the CPM is disabled. SDCR interacts with the DMA controllers in the FEC.

  • Page 33: Programming Model

    Freescale Semiconductor, Inc. Chapter 6 Programming Model This chapter gives an overview of the MPC860T implementation of the Fast Ethernet controller (FEC) registers, buffer descriptors (BDs), and initialization. 6.1 Overview The FEC software model is similar to that used by the 10-Mbps Ethernet implemented on the MPC860 core device.

  • Page 34: Ram Perfect Match Address Low Register (Addr_Low)

    Freescale Semiconductor, Inc. Table 6-1. FEC Parameter RAM Memory Map (Continued) Address Name Description Section 0xE40 ECNTRL Ethernet control register 6.2.8 0xE44 IEVENT Interrupt event register 6.2.9 0xE48 IMASK Interrupt mask register 6.2.9 0xE4C IVEC Interrupt level and vector status 6.2.10...

  • Page 35: Addr_High Register

    Freescale Semiconductor, Inc. Table 6-2 describes the ADDR_LOW Þelds. Table 6-2. ADDR_LOW Field Descriptions Bits Name Description 0Ð31 ADDR_LOW Bytes in the 6-byte address: 0 (bits 0Ð7), 1 (bits 8Ð15), 2 (bits 16Ð23) and 3 (bits 24Ð31) 6.2.2 RAM Perfect Match Address High (ADDR_HIGH) The ADDR_HIGH register, shown in Figure 6-2, is written by and must be initialized by the user.

  • Page 36: Ram Hash Table Low (Hash_Table_Low)

    Freescale Semiconductor, Inc. Bits Field HASH_HIGH Reset UndeÞned Read/write Addr 0xE08 Bits Field HASH_HIGH Reset UndeÞned Read/write Addr 0xE0A Figure 6-3. HASH_TABLE_HIGH Register Table 6-4 describes HASH_TABLE_HIGH Þelds. Table 6-4. HASH_TABLE_HIGH Field Descriptions Bits Name Description 0Ð31 HASH_HIGH Contains the upper 32 bits of the 64-bit hash table used in address recognition for receive frames with a multicast address.

  • Page 37: R_Des_Start Register

    Freescale Semiconductor, Inc. Table 6-5 describes HASH_TABLE_LOW Þelds. Table 6-5. HASH_TABLE_LOW Field Descriptions Bits Name Description 0Ð31 HASH_LOW Contains the lower 32 bits of the 64-bit hash table used in address recognition for receive frames with a multicast address. HASH_LOW[0] contains hash index bit 31. HASH_LOW[31] contains hash index bit 0.

  • Page 38: X_Des_Start Register

    Freescale Semiconductor, Inc. Bits Field X_DES_START Reset UndeÞned Read/write Addr 0xE14 Bits Field X_DES_START Reset UndeÞned Read/write Addr 0xE16 Figure 6-6. X_DES_START Register Table 6-7 describes X_DES_START Þelds. Table 6-7. X_DES_START Field Descriptions Bits Name Description 0Ð29 X_DES_START Pointer to start of TxBD queue.

  • Page 39: Ethernet Control Register (Ecntrl)

    Freescale Semiconductor, Inc. Bits Field Ñ Reset UndeÞned Read/write Addr 0xE18 Bits Field Ñ R_BUFF_SIZE Ñ Reset UndeÞned Read/write Addr 0xE1A Figure 6-7. R_BUFF_SIZE Register Table 6-8 describes R_BUFF_SIZE Þelds. Table 6-8. R_BUFF_SIZE Field Descriptions Bits Name Description 0Ð20 Ñ...

  • Page 40: Interrupt Event (I_Event)/Interrupt Mask Register (I_Mask)

    Freescale Semiconductor, Inc. Table 6-9 describes ECNTRL Þelds. Table 6-9. ECNTRL Field Descriptions Bits Name Description 0Ð7 Ñ Reserved. These Þelds may return unpredictable values and should be masked on a read. Users should always write these Þelds to zero.

  • Page 41: Ethernet Interrupt Vector Register (Ivec)

    Freescale Semiconductor, Inc. and RFINT to notify at the end of frame. Table 6-10. I_EVENT/I_MASK Field Descriptions Bits Name Description HBERR Heartbeat error. When I_EVENT[HBC] is set, this interrupt indicates that heartbeat was not detected within the heartbeat window following a transmission.

  • Page 42: Rxbd Active Register (R_Des_Active)

    Freescale Semiconductor, Inc. Bits Field ILEVEL Ñ Reset 0000_0000_0000_0000 Read/write Addr 0xE4C Bits Field Ñ IVEC Ñ Reset 0000_0000_0000_0000 Ñ Read only Ñ Addr 0xE4E Figure 6-10. IVEC Register Table 6-11 describes IVEC Þelds. Table 6-11. IVEC Field Descriptions Bits...

  • Page 43: Txbd Active Register (X_Des_Active)

    Freescale Semiconductor, Inc. Bits Field Ñ R_DES_ACTIVE Ñ Reset 0000_0000_0000_0000 Read/write Addr 0xE50 Bits Field Reset 0000_0000_0000_0000 Read/write Addr 0xE52 Figure 6-11. R_DES_ACTIVE Register Table 6-12 describes R_DES_ACTIVE Þelds. Table 6-12. R_DES_ACTIVE Field Descriptions Bits Name Description 0Ð6 Ñ Reserved.

  • Page 44: Mii Management Frame Register (Mii_Data)

    Freescale Semiconductor, Inc. Bits Field Ñ X_DES_ACTIVE Ñ Reset 0000_0000_0000_0000 Read/write Addr 0xE54 Bits Field Ñ Reset 0000_0000_0000_0000 Read/write Addr 0xE56 Figure 6-12. X_DES_ACTIVE Register Table 6-13 describes X_DES_ACTIVE Þelds. Table 6-13. X_DES_ACTIVE Field Descriptions Bits Name Description 0Ð6 Ñ...

  • Page 45: Mii_Data Register

    Freescale Semiconductor, Inc. Bits Field Reset UndeÞned Read/write Addr 0xE80 Bits Field DATA Reset UndeÞned Read/write Addr 0xE82 Figure 6-13. MII_DATA Register Table 6-14 describes MII_DATA Þelds. Table 6-14. MII_DATA Field Descriptions Bits Name Description 0Ð1 Start of frame delimiter. Must be programmed to 01 for a valid MII management frame.

  • Page 46: Mii_Speed Register

    Freescale Semiconductor, Inc. completes. At this time the contents of MII_DATA match the original value written except for the DATA Þeld, whose contents have been replaced by the value read from the PHY register. Writing to MII_DATA during frame generation alters the frame contents. Software should use the MII_DATAIO_COMPL interrupt to avoid writing to the MII_DATA register during frame generation.

  • Page 47: Fifo Receive Bound Register (R_Bound)

    Freescale Semiconductor, Inc. be non-zero to source a read or write management frame. After the management frame is complete, MII_SPEED may optionally cleared to turn off the MDC. The MDC generated has a 50% duty cycle except when MII_SPEED is changed during operation (changes take effect following either a rising or falling edge of MDC).

  • Page 48: Fifo Receive Start Register (R_Fstart)

    Freescale Semiconductor, Inc. Table 6-17. R_BOUND Field Descriptions Bits Name Description 22Ð29 R_BOUND Read-only. Highest valid FIFO RAM address. 30Ð31 Ñ Reserved. Should be written to zero by the host processor. 6.2.16 FIFO Receive Start Register (R_FSTART) The R_FSTART register, shown in Figure 6-16, is programmed by the user to indicate the starting address of the receive FIFO.

  • Page 49: Fifo Transmit Start Register (X_Fstart)

    Freescale Semiconductor, Inc. for the system bus. Setting the watermark to a high value lowers the risk of a transmit FIFO underrun due to system bus contention. Bits Field Ñ Reset 0000_0000_0000_0000 Read/write Addr 0xED0 Bits Field Ñ X_WMRK Reset...

  • Page 50: Dma Function Code Register (Fun_Code)

    Freescale Semiconductor, Inc. Bits Field Ñ Reset 0000_0000_0000_0000 Read/write Addr 0xEEC Bits Field Ñ X_FSTART Ñ Reset 0000_0 Microcode dependent Read/write Addr 0xEEE Figure 6-18. X_FSTART Register Table 6-20 describes X_FSTART Þelds. Table 6-20. X_FSTART Field Descriptions Bits Name Description 0Ð21...

  • Page 51: Receive Control Register (R_Cntrl)

    Freescale Semiconductor, Inc. Table 6-21 describes FUN_CODE Þelds. Table 6-21. FUN_CODE Field Descriptions Bits Name Description Ñ Reserved. This bit reads as zero. 1Ð2 DATA_BO Byte order. Supplied to the SDMA interface during receive and transmit data DMA transfers. 00 Reserved 01 PowerPC little-endian byte ordering.

  • Page 52: Receive Hash Register (R_Hash)

    Freescale Semiconductor, Inc. Table 6-22 describes R_CNTRL Þelds. Table 6-22. R_CNTRL Field Descriptions Bits Name Description 0Ð26 Ñ Reserved. This bit reads as zero. BC_REJ Broadcast frame reject. If set, frames with DA + 0xFFFF_FFFF_FFFF are rejected unless the PROM bit set. If both BC_REJ and PROM = 1, frames with broadcast DA are accepted and RxBD[M] is set.

  • Page 53: Transmit Control Register (X_Cntrl)

    Freescale Semiconductor, Inc. Table 6-22 describes R_HASH Þelds. Table 6-23. R_HASH Field Descriptions Bits Name Description 0Ð7 Ñ Reserved for internal use. When read, these bits are unpredictable. 8Ð20 Ñ Reserved. These bits are read as zeros. 21Ð31 MAX_FRAME_LENGTH User read/write Þeld. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame.

  • Page 54: Initialization Sequence

    Freescale Semiconductor, Inc. Table 6-24. X_CNTRL Field Descriptions Bits Name Description Graceful transmit stop. When GTS is set, the MAC stops transmission after any frame being transmitted is complete and INTR_EVENT[GRA] is set. If frame transmission is not underway, the GRA interrupt is asserted immediately.

  • Page 55: Descriptor Controller Initialization

    Freescale Semiconductor, Inc. exact values depend on the application. The sequence resembles that shown in Table 6-27. Table 6-27. User Initialization (before Setting ECNTRL[ETHER_EN]) Step Description Set IMASK Clear IEVENT Set IVEC (deÞne ILEVEL) Set R_FSTART (optional) Set X_FSTART (optional)

  • Page 56: Buffer Descriptors (Bds)

    Freescale Semiconductor, Inc. (though these steps could also be done before setting ETHER_EN). Table 6-27. User Initialization (after Setting ECNTRL[ETHER_EN]) Step Description Fill RxBD ring with empty buffers Set R_DES_ACTIVE 6.4 Buffer Descriptors (BDs) Data for Fast Ethernet frames must reside in memory external to the MPC860T device.

  • Page 57: Receive Buffer Descriptor (Rxbd)

    Freescale Semiconductor, Inc. DATA LENGTH RX BUFFER POINTER A[0Ð15] RX BUFFER POINTER A[16Ð31] Figure 6-23. Receive Buffer Descriptor (RxBD) The RxBD format is shown in Table 6-27. Table 6-27. Receive Buffer Descriptor (RxBD) Field Description Bits Name Description Empty. Written by the FEC and user. Note that if the software driver sets RxBD[E], it should then write to R_DES_ACTIVE.

  • Page 58: Ethernet Transmit Buffer Descriptor (Txbd)

    Freescale Semiconductor, Inc. Table 6-27. Receive Buffer Descriptor (RxBD) Field Description (Continued) Bits Name Description Overrun, written by FEC. A receive FIFO overrun occurred during frame reception. If OV = 1, the other status bits, M, LG, NO, SH, CR, and CL lose their normal meaning and are cleared.
  • Page 59 Freescale Semiconductor, Inc. Table 6-29. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued) Bits Name Description Wrap, written by user. 0 The next BD is found in the consecutive location 1 The next BD is found at the location deÞned in X_DES_START.
  • Page 60 Freescale Semiconductor, Inc. 6-28 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.com...

  • Page 61: Electrical Characteristics

    Freescale Semiconductor, Inc. Chapter 7 Electrical Characteristics This chapter contains detailed information on DC and AC electrical characteristics and AC timing speciÞcations for the MPC860T MII signals and a MPC860T pinout diagram. For information on maximum ratings, thermal characteristics, power considerations, and layout practices, see the MPC860 PowerQUICC Hardware SpeciÞcations.

  • Page 62: Mii Receive Signal Timing Diagram

    Freescale Semiconductor, Inc. RX_CLK (input) RXD[3:0] (inputs) RX_DV RX_ER Figure 7-1. MII Receive Signal Timing Diagram The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the RX_CLK frequency - 1%.

  • Page 63: Mii Async Inputs Signal Timing (Crs, Col)

    Freescale Semiconductor, Inc. TX_CLK (input) TXD[3:0] (outputs) TX_EN TX_ER Figure 7-2. MII Transmit Signal Timing Diagram 7.3.3 MII Async Inputs Signal Timing (CRS, COL) Table 7-3 provides information on the MII async inputs signal timing, shown in Figure 7-3. Table 7-3. MII Async Inputs Signal Timing...

  • Page 64: Mii Serial Management Channel Timing (Mdio,Mdc)

    Freescale Semiconductor, Inc. 7.3.4 MII Serial Management Channel Timing (MDIO,MDC) Table 7-4 provides information on the MII serial management channel signal timing, shown in Figure 7-4. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

  • Page 65: Mpc860T Pin Assignments

    Freescale Semiconductor, Inc. 7.4 MPC860T Pin Assignments Figure 7-5 shows the MPC860T pin assignments. Pins that support the FEC are shown in black. M_RxD0M_Rx_CLKM_TxD1M_Tx_CLK D0 VDDL CLKOUT IPA3 VSSSYN1 M_RxD2 M_RxD1 M_TxD0 M_Rx_DV M_Tx_EN IRQ0 D13 PB14 M_RxD3 M_TxD2 M_TxD3...
  • Page 66 Freescale Semiconductor, Inc. MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.com...
  • Page 67 Freescale Semiconductor, Inc. MOTOROLA Chapter 7. Electrical Characteristics For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.com...
  • Page 68 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...

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