Reference Information - Samsung DVD-812 Service Manual

2. Reference Information

2-1 IC Descriptions
2-1-1 AIC1 (AK4393 ; Digital-to-Analog Converter)
Serial
Input Control
Serial
Left/Right Clock
Input
Bit Clock
Interface
Serial Data
Power Down
Control
Soft Mute
Register
Double
Speed Select
No. Pin Name
1 DVSS
2 DVDD
3 MCLK
4 PD
5 BICK
6 SDATA
7 LRCK
8 SMUTE
(or CS)
9 DFS
10 DEM0
(or CCLK)
11 DEM1
(or CDTI)
12 DIF0
13 DIF1
14 DIF2
15 BVSS
16 VREFL
17 VREFH
18 AVDD
19 AVSS
20 AOUTR-
21 AOUTR+
22 AOUTL-
23 AOUTL+
24 VCOM
25 P/S
26 CKS0
27 CKS1
28 CKS2
Samsung Electronics
Left Channel
De-emphasis 8X Multi-bit ˘•
Soft Mute Interpolator Modulator
De-emphasis 8X Multi-bit ˘•
Soft Mute Interpolator Modulator
Right Channel
De-emphasis
Control
I/O Pin Function and Description
- Digital Ground. Digital ground is 0V.
- Digital Supply.
I Master Clock Input.
I Power-down and Reset. When low the AK4393 is in Power-down Mode and held in reset.
The AK4393 should always be reset after power-up.
I Audio Serial Data Clock Input.
I Serial Data Input.
I Left/Right Clock Input.
I Soft Mute Input or Chip Select Input. If the P/S pin (pin 25) is high, SMUTE controls the
soft mute function as follows:
- When SMUTE goes high, the soft mute cycle is initiated.
- When SMUTE goes low, the output mute is slowly released.
If the P/S pin is low, SMUTE is the Chip Select Input for the Serial Control Mode. Chip
select is active when SMUTE is low.
I Double Sampling Speed Input. When low, this pin defines the Normal Speed Mode, and
128 x F oversampling is implemented. When high, the DFS pin defines the Double Speed
s
Mode, implemented with 64 x F
I De-emphasis Enable #0 or Control Data Clock Input. If the P/S pin (pin 25) is high,
DEM0 is used to select the De-emphasis Mode according to Table 3. If the P/S pin os low
DEM0 is the clock input for the Serial Control Mode.
I De-emphasis Enable #1 or Control Data Input. If the P/S pin (pin 25) is high, DEM1 is
used to select the De-emphasis Mode according to Table 3. If the P/S pin is low, DEM1 is
the control data input for the Serial Control Mode.
I Digital Input Format Select #0.
I Digital Input Format Select #1.
I Digital Input Format Select #2.
- Substrate Ground Pin.
I Low Level Voltage Reference Input.
I High Level Voltage Reference Input.
- Analog Supply.
- Analog Ground.
O Right Channel Negative Output.
O Right Channel Positive Output.
O Left Channel Negative Output.
O Left Channel Positive Output.
O Common Voltage Output.
I Parallel/Serial Control Mode Select Input.
implemented. If High, the Parallel Control Mode is selected. This pin has an internal
pull-up.
I Master Clock Select #0.
I Master Clock Select #1.
I Master Clock Select #2.
Switched Right Output +
Right Output -
Capacitor Filter
Left Output +
Switched
Left Output -
Capacitor Filter
Clock Divider
Master Clock Clock Control
3.3V or 5.0V nominal.
A clock input of 64fs or more is recommended.
Defines the sampling rate, F
oversampling. This pin features an internal pull-down.
s
Substrate ground is 0V.
Normally connected to analog ground.
Normally connected to analog supply.
Analog supply is 5V nominal.
Analog ground is 0V.
Common voltage output is 2.6V nominal.
If Low, the Serial Control Mode is
DVSS
1
DVDD
2
MCLK
3
PD
4
BICK
5
SDATA
6
LRCK
7
SMUTE
8
DFS
9
DEM0
10
DEM1
11
DIF0
12
DIF1
13
DIF2
14
.
s
CKS2
28
CKS1
27
CKS0
26
P/S
25
VCOM
24
AOUTL+
23
AOUTL-
22
AOUTR+
21
AOUTR-
20
AVSS
19
AVDD
18
VREFH
17
VREFL
16
BVSS
15
2-1