ViewSonic VG800-2 Service Manual page 41

5. DDC 2 B
ICM6 & ICM7 (24LC21A) can continuously transmit its extended identification, "EDID" using
DDC1 communication channel. In addition, the monitor can respond to a requests for EDID, or
complete VDIF, to be transmitted using DDC2, level B commands. Pin6 SCL is clock input for DDC
2B, pin5 SDA for data input, and pin7 VCLK is clock input for DDC1.
In DDC1 data transfer (UNI-directional mode), the VCLK input pin is used as an input clock
for data transmission and SDA output pin is used as serial data line the SCL pin will hold high.
The DDC2B node (BI-directional mode) BUS consists of two wires. SCL is for the data
transmission clock and SDA is for the data line.
6. Synchronous DRAM
ICM12,13,14(K4S161622D) is 16,777,216 bits synchronous high data rate Dynamic RAM
organized as 2 x 524,288 words by 16 bits, Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory
PIN DESCRIPTION:
ViewSonic Corporation
38
Confidential – Do Not Copy
VG800b