ViewSonic VG800-2 Service Manual page 39

The external frame buffer provides the storage required for the frame rate conversion
process and the integrated OSD. The gm5020 is able to operate with 16Mbit or 64Mbit
Synchronous DRAM (SDRAM) devices and/or 16Mbit or 32Mbit Synchronous Graphics RAM
(SGRAM) devices. The FRC data bus width is programmable to 32 or 48-bits. Generally, 32 bits
is sufficient for XGA and 48 bits is sufficient for SXGA.
The gm5020 OSD controller supports both character-mapped and bitmapped modes. A user
programmable palette of 256 true colors (255 colors, + 1 transparent) is available.
In character mapped mode, a maximum of four colors per character are available.
In 8-bit bitmapped mode, any pixel can be assigned any one of 256 user-defined true colors.
In 4-bit bitmapped mode, any pixel can be assigned any one of 16 user-defined true colors
(15 colors plus one transparent).
The gm5020 incorporates an embedded microprocessor, or OCM (On-Chip
Microprocessor).This processor is intended to simplify the gm5020 system software
implementation by providing embedded macro functions such as OSD menu configurations. It is
not intended to replace the system microprocessor.
An arbitration mechanism handles the register access requests from the OCM and the
system.micro.
4. LVDS Transmitter
ICM15,16 (SN75LVDS83)
clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit.
These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted
over five balanced-pair conductors for receipt by a compatible receiver,
ViewSonic Corporation
FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers,a
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VG800b