Interface Information; Table 4. Pin Settings - Planar EL240.128.45 ICEBrite User Manual

Interface Information

This Small Graphics Display (SGD) incorporates an interface that is
compatible with the 8-bit microprocessor interfaces found in comparable
LCD displays with built-in controllers. The display incorporates a built-in
RAiO RA8835A standard LCD controller.

Table 4. Pin Settings.

Signal
D0 to D7
SEL1
/RD or E
/WR or
R//W
/RES
READY
/CS
A0
SELF-
TEST
VL (+5V)
VH(+12V)
LUMA
GND
8 EL240.128.45 Operations Manual (020-0345-00C)
Functional Description
Pins 13-20: Tristate input/output pins. Connect to an 8- or 16-bit µP-bus.
Pin 21: µP-interface select. Both 8080-family and 6800-family processors are
supported. SEL1 should be tied directly to V
SEL1 Interface
0 8080 family
1 6800 family
Pin 8: With the 8080 interface, this signal acts as the active-LOW read strobe.
With the 6800 interface, this signal acts as the active-HIGH enable clock. Data
is read from or written to the display when this clock goes HIGH.
Pin 7: With the 8080 interface, this signal acts as the active-LOW write strobe.
The bus data is latched on the rising edge of this signal. With the 6800
interface, this signal acts as the read/write control signal. Data is read from the
display if this signal is HIGH, and written to the display if it is LOW.
Pin 6: When low resets RA8835A, must be high or unconnected in normal
operation
Pin 22: OUTPUT When data for Row 128 is written to display drivers this
signal goes high. While the signal is high it is possible to write data to
RA8835A memory so that it does not cause disturbances to display data. This
signal goes low at latest 3.5 µs before when loading of Row 1 data begins.
Signal READY output is CMOS with 100 Ω series resistor.
Pin 9: Chip select. This active-LOW input enables the RA8835A. It is usually
connected to the output of an address decoder device that maps the RA8835A
into the memory space of the controlling microprocessor.
Pin 10: A0, in conjunction with the /RD and /WR or R//W and E signals, control
the type of access to the display, as shown below.
8080 Family Interface
A0 /RD /WR
0 0 1
1 0 1
0 1 0
1 1 0
6800 Family Interface
A0 /RD /WR
0 1 1
1 1 1
0 0 0
1 0 1
Pin 11: This pin should be connected to GND for normal display operation.
When high, display operates in SELFTEST mode
Pin 5: +5 V logic supply voltage
Pins 1 and 2: +12 V supply for DC-DC converter and display analog circuits
Pin 24: Luminance control input
Pins 3, 4, 12, and 23: Signal return for logic and power supplies
or GND to prevent noise.
L
A0 /RD /WR
A0 /RD /WR
A0 E R//W
Function
Status flag read
Display data and
Display data and
Command write
Function
Status flag read
Display data and
Display data and
Command write
/CS
/CS
/CS
cursor address read
parameter write
cursor address read
parameter write