Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Related Manuals for MSI D3061
Summary of Contents for MSI D3061
- Page 1 D3061 MS-S3891 Server Motherboard User Guide...
-
Page 2: Table Of Contents
Contents Regulatory Notices ......................4 Safety Information ......................7 Specifications ........................9 Overview of Components ....................11 Block Diagram .......................12 CPU Socket ........................14 Assembly Overview ....................15 Installing CPU & Heatsink ................... 16 Memory Slots .........................19 CPU0_DIMM_A1/A2~H1/H2: DDR5 DIMM Slots ............19 Recommended Memory Population ................. 20 General Memory Population Rules ............... - Page 3 JPICPWR5: For Storage Backplane (6-Pin) ............31 JPWR1~2: 4-Pin Power Connectors ................31 Cooling Connectors ......................32 FAN0: 4-Pin Fan Header (debug only) ................ 32 JCOOL2: 4-Pin Liquid Leak Detection Header ............32 JCOOL3: 6-Pin Liquid Cooling Header ............... 32 USB Connectors ......................33 JUSB3: USB 3.2 Gen 1 Connector ................
-
Page 4: Regulatory Notices
Regulatory Notices WEEE Statement Under the European Union ( “EU” ) Directive on Waste Electrical and Electronic Equipment, Directive 2012/19/EU, products of “electrical and electronic equipment” cannot be discarded as municipal waste anymore and manufacturers of covered electronic equipment will be obligated to take back such products at the end of their useful life. -
Page 5: Chemical Substances Information
Chemical Substances Information In compliance with chemical substances regulations, such as the EU REACH Regulation (Regulation EC No. 1907/2006 of the European Parliament and the Council), MSI provides the information of chemical substances in products at: https://csr.msi.com/global/index Battery Information Please take special precautions if this product comes with a battery. -
Page 6: Environmental Policy
US. Copyright and Trademarks Notice Copyright © Micro-Star Int’ l Co., Ltd. All rights reserved. The MSI logo used is a registered trademark of Micro-Star Int’ l Co., Ltd. All other marks and names mentioned may be trademarks of their respective owners. -
Page 7: Safety Information
Safety Information Please read and follow these safety instructions carefully before ⚠ installing, operating or performing maintenance on the server. General Safety Instructions ● Always read the safety instructions carefully. ● Keep this User Guide for future reference. ● Keep this equipment away from humidity. ●... -
Page 8: Assembly And Installation
Assembly and Installation This equipment must be installed in restricted access areas by qualified personnel to comply with safety standards set by the NEC and IEC 62368-1, Third Edition, for Information Technology Equipment. Lifting and Placement ● WARNING: This server is heavy. ●... -
Page 9: Specifications
Specifications Model D3061 Form factor DC-MHS M-DNO Type-2 HPM Dimensions 305.59mm x 210mm Single Intel® Xeon® 6700E-series, 6500P-series and 6700P-series processors, Processor TDP up to 350W Socket 1 x Intel® LGA 4710 (Socket E2) ● 16 x DDR5 DIMM slots, 8 channels (2DPC), RDIMM/ RDIMM-3DS/ MRDIMM* - Max Frequency: »... - Page 10 Model D3061 ● 3 x 12-pin PICPWR power connectors (for PDB* and PCIe slot) ● 1 x 6-pin PICPWR power connectors Power ● 2 x 4-pin PCIPWR power connectors (for PCIe slot power supply) Connectors *PDB: The term “PDB” stands for power distribution board.
-
Page 11: Overview Of Components
Overview of Components OCP0 DC-SCM JCOOL3 JCOOL2 FBP_I2C_1 FBP_I2C_2 JPWR1 JPASSWORD_C_1 JTAG_SEL2 LED_H1 JPWR2 LED_L1 JPICPWR5 M2_1 JPICPWR3 JBAT1 M2_2 JMCIO4 JMCIO1 BAT1 FAN0 JBAT2 JMCIO3 JMCIO2 CPU0 JCHASSIS1 JBAT7 JMCIO8 JMCIO5 JIPMB1 JUSB3 JPDB_MGT1 JMCIO7 JMCIO6 JFP2 JFP1 JPICPWR1 JPICPWR2... -
Page 12: Block Diagram
Block Diagram CPU0 DDR5 CH A~D 8 x DIMM Slots 8 x DIMM Slots DDR5 CH E~H (2DPC) (2DPC) LGA 4710 (Socket E2) CPU0_DIMM_A1/ A2 CPU0_DIMM_E1/ E2 CPU0_DIMM_D1/ D2 CPU0_DIMM_H1/ H2 PCIe 5.0 (x8) PCIe 5.0 (x8) (0-7) 1 x MCIO 8i (7-0) 1 x MCIO 8i JMCIO1... -
Page 13: Component Contents
Component Contents Component Page CPU Socket Memory Slots CPU0_DIMM_A1/A2~H1/H2: DDR5 DIMM Slots Storage Connectors M2_0~1: M.2 Slots (M Key, 2280/ 22110) Expansions JMCIO1~8: MCIO 8i Connectors Power Connectors JPICPWR1~3,5 : 12V PICPWR Power Connectors JPWR1~2: 4-Pin Power Connectors Cooling Connectors FAN0: 4-Pin Fan Header (debug only) JCOOL2: 4-Pin Liquid Leak Detection Header JCOOL3: 6-Pin Liquid Cooling Header... -
Page 14: Cpu Socket
CPU Socket CPU0 Important ⚠ Overheating will seriously damage the CPU and system. Always make sure the ● cooling fan can work properly to protect the CPU from overheating. Make sure that you apply an even layer of thermal paste (or thermal tape) between the CPU and the heatsink to enhance heat dissipation. -
Page 15: Assembly Overview
Assembly Overview Important ⚠ Illustrations are for demonstration purposes only; actual parts may vary. 1U EVAC Heatsink 2U EVAC Heatsink Processor Heatsink Module (PHM) Processor Carrier Processor Processor Socket Socket Cover Bolster Plate Important ⚠ Please check the instruction that come with your heatsink and thermal paste for ●... -
Page 16: Installing Cpu & Heatsink
Installing CPU & Heatsink 1. Place the processor carrier on top of the processor in the tray with their pin 1 indicators aligned. If installed properly, the CPU will snap into the carrier’ s side latches and the carrier will latch firmly to it. No Shim Shim CPU Carrier: E2A... - Page 17 4. Check the heatsink for a diagonally cut corner or the #1clip on the heatsink label if present. Align the processor carrier’ s Pin 1 indicator with the heatsink’ s cut corner (#1 clip), then gently press the heatsink down to engage the carrier’ s latching mechanism to the heatsink at four corners.
- Page 18 7. Flip 4 anti-tilt wires to the locked position (outward) and make sure the wires are firmly secure. 4 x anti-tilt wires locked Important ⚠ Ensure the 4 anti-tilt wires rotate and lock into the designated positions on the stepped flanges, as specified in the table below for each CPU carrier.
-
Page 19: Memory Slots
Memory Slots CPU0_DIMM_A1/A2~H1/H2: DDR5 DIMM Slots CPU0... -
Page 20: Recommended Memory Population
Recommended Memory Population Please read the following Guidelines before populating memory. ⚠ General Memory Population Rules ● Single DIMM Type Usage: Only one type of DIMM is allowed across the system. Mixing different DIMM types is not permitted. - Example: All DDR5 RDIMMs or all MRDIMMs. ●... -
Page 21: Dimms Population (X4/X8)
DIMMs Population (x4/x8) Intel® Xeon® 6700E Series DIMM population within IMC DDR Type Config Set A (x8) Config Set B (x4) Slot 1, Slot 2 Slot 1, Slot 2 x8, None x4, None RDIMM x4, x4 Intel® Xeon® 6700P/ 6500P Series DIMM population within IMC DDR Type Config Set A (x8) -
Page 22: Key Parameters For Dimm
Key Parameters for DIMM Intel® Xeon® 6700E Series Speed (MT/s); Voltage (V); DIMM Capacity (GB) Ranks & DIMMs per Channel (DPC) DDR Type DIMM DRAM Density 1DPC 2DPC & Data Width 16 Gb 24 Gb 32 Gb 1.1 V 1DPC 2DPC 1DPC 2DPC... -
Page 23: Dimm Configuration
DIMM Configuration Intel® Xeon® 6700E Series Slot 1 Slot 2 Slots DIMMs DRAM DIMM Memory DIMM DIMM DIMM DIMM Density Type Channel Channel Organization Channels Ranks & Capacity Ranks & Capacity (Gb) (SPC) (DPC) Width (GB) Width (GB) 2Rx8 32 GB 1 or 2 1Rx4 32 GB... -
Page 24: Ddr5 Only Dimm Configuration Diagram
DDR5 Only DIMM Configuration Diagram IMC7 IMC6 IMC5 IMC4 IMC0 IMC1 IMC2 IMC3 IMC# IMC7 IMC6 IMC5 IMC4 IMC0 IMC1 IMC2 IMC3 Channel Chan 7 Chan 6 Chan 5 Chan 4 Chan 0 Chan 1 Chan 2 Chan 3 DDR5 H1 H2 G1 G2 B2 B1 C2 C1 D2 D1 “V”... -
Page 25: Installing Memory Modules
Installing Memory Modules 1. Open the side clips to unlock the DIMM slot. 2. Insert the DIMM vertically into the slot, ensuring that the off-center notch at the bottom aligns with the slot. 3. Push the DIMM firmly into the slot until it clicks and the side clips automatically close. -
Page 26: Storage Connectors
Storage Connectors Storage Speed M2_1 Name Description M2_2 M2_1~2 PCIe 5.0 x2, 32GT/s CPU0 M2_0~1: M.2 Slots (M Key, 2280/ 22110) Please install the M.2 solid-state drive (SSD) into the M.2 slot as shown below. 1. Adjust the M.2 board latch to fit your M.2 SSD size. -
Page 27: Expansions
Expansions Expansions Speed Name Description JMCIO1 JMCIO1~8 PCIe 5.0 x8, 32 GT/s JMCIO2 JMCIO3 JMCIO4 JMCIO5 JMCIO6 JMCIO7 JMCIO8 JMCIO1~8: MCIO 8i Connectors These are vertical 74-pin Mini Cool Edge IO (MCIO) connectors, which support PCIe 5.0 x8 32GT/s interface JMCIO1~8 P5E_CPU_PE_NVME_RX_D+ P5E_CPU_PE_NVME_TX_D+... - Page 28 P5E_CPU_PE_NVME_RX_D+ P5E_CPU_PE_NVME_TX_D+ P5E_CPU_PE_NVME_RX_D- P5E_CPU_PE_NVME_TX_D- P5E_CPU_PE_NVME_RX_D+ P5E_CPU_PE_NVME_TX_D+ P5E_CPU_PE_NVME_RX_D- P5E_CPU_PE_NVME_TX_D- P5E_CPU_PE_RX_D+ P5E_CPU_PE_NVME_TX_D+ P5E_CPU_PE_RX_D- P5E_CPU_PE_NVME_TX_D+ SMB_MCIOP_CPU_SCL FM_MCIO_CPU_FPGA_FLEXIO_3A SMB_MCIOP_CPU_SDA FM_MCIO_CPU_FPGA_FLEXIO_4A USB_HUB_MCIO_CPU_PE_D+ FM_MCIO_CPU_FPGA_FLEXIO_1A USB_HUB_MCIO_CPU_PE_D- FM_MCIO_CPU_FPGA_FLEXIO_2A P5E_CPU_PE_RX_D+ P5E_CPU_PE_NVME_TX_D+ P5E_CPU_PE_RX_D- P5E_CPU_PE_NVME_TX_D- P5E_CPU_PE_RX_D+ P5E_CPU_PE_NVME_TX_D+ P5E_CPU_PE_RX_D- P5E_CPU_PE_NVME_TX_D-...
-
Page 29: Power Connectors
Power Connectors JPWR1 JPICPWR3 JPICPWR5 JPWR2 JPICPWR2 JPICPWR1 JPICPWR1~3,5 : 12V PICPWR Power Connectors The PICPWR (Platform Infrastructure Connectivity Power) connector enables the HPM (Host Processor Module) to supply power and manage sideband signals to peripherals, including PCIe devices (JPICPWR3), the storage backplane (JPICPWR5), and the Power Distribution Board (JPICPWR1~2). -
Page 30: Jpicpwr2: For Power Distribution Board (12-Pin)
JPICPWR2: For Power Distribution Board (12-Pin) Power Signals +12V +12V +12V +12V JPICPWR2 +12V +12V Sideband Management Signals FM_HPM_SOUTH_6_PICPWR_B_SB1 FM_HPM_SOUTH_6_PICPWR_A_SB1 (SB*) (SB*) FM_HPM_SOUTH_6_PICPWR_B_SB2 FM_HPM_SOUTH_6_PICPWR_A_SB2 FM_HPM_SOUTH_6_PICPWR_B_SB3 FM_HPM_SOUTH_6_PICPWR_A_SB3 FM_HPM_SOUTH_6_PICPWR_B_SB4 SB10 FM_HPM_SOUTH_6_PICPWR_A_SB4 SMB_JPICPWR2_B_SCL SB11 SMB_JPICPWR2_A_SCL SMB_JPICPWR2_B_SDA SB12 SMB_JPICPWR2_A_SDA *SB: The term SB stands for “sideband” . JPICPWR3: For PCIe Devices (12-Pin) Power Signals +12V... -
Page 31: Jpicpwr5: For Storage Backplane (6-Pin)
JPICPWR5: For Storage Backplane (6-Pin) Power Signals +12V JPICPWR5 +12V +12V Sideband Management Signals FM_HPM_PICPWR_B FM_HPM_PICPWR_B (SB*) (SB*) FM_HPM_PICPWR_B SMB_PICPWR_A_SCL FM_HPM_PICPWR_B SMB_PICPWR_A_SDA *SB: The term “SB” stands for sideband. JPWR1~2: 4-Pin Power Connectors This connector provides power output to PCIe slot. P12V P3V3 JPWR1~2... -
Page 32: Cooling Connectors
Cooling Connectors JCOOL3 JCOOL2 FAN0 FAN0: 4-Pin Fan Header (debug only) The fan header supports cooling fans with +12V. When connecting the wire to the connectors, always note that the red wire is the positive and should be connected to the +12V;... -
Page 33: Usb Connectors
USB Connectors JUSB3 JUSB3: USB 3.2 Gen 1 Connector The USB (Universal Serial Bus) port is for attaching USB devices such as keyboard, mouse, or other USB-compatible devices. It supports up to 5Gbps and backward compatibility with USB 2.0 devices (480 Mbps). P5V_USB_1 USB2_P3_ESD_D+ USB3_P2_ESD_RX-... -
Page 34: Other Connectors And Components
Other Connectors and Components JFP1~2: DC-MHS Control Panel Header The DC-MHS control panel header for M-PESTI connects the HPM to the server’ s front panel, enabling essential controls such as power, LED indicators, buttons, and sideband signals for management and monitoring. ●... -
Page 35: Jpdb_Mgnt: Pdb Management Header
JPDB_MGNT: PDB Management Header The PDB Management header connects to the power distribution board (PDB). P12V_STBY_PSU P12V_STBY_PSU JPDB_MGNT ISENSE_I_PSYS VSENSE_LOCAL_V_PSYS P12V_STBY_PSU P12V_STBY_PSU SGPIO_LD SGPIO_CK SGPIO_DO SGPIO_DI SMB_PS_CLK SMB_PS_DAT JPDB_MGNT... -
Page 36: J1: Power Button Header
J1: Power Button Header This header is provided to connect the system power button. FP_PWR_BTN_N J2: Reset Button Header This header is provided to connect the system reset button. FM_RST_BTN_N JIPMB1: IPMB Header This header is used to connect the Intelligent Platform Management Bus. SMB_IPMB_LVC5_CON_SDA JIPMB1 SMB_IPMB_LVC5_CON_SCL... -
Page 37: Jvroc1: Vroc Connector
JVROC1: VROC Connector Intel® Virtual RAID on CPU (Intel® VROC) is a hybrid RAID solution specifically designed for NVMe SSDs connected directly to the CPU. PU_KEY_CONN_PIN2_R JVROC1 FM_PCH_SATA_RAID_KEY_R FBP_I2C_1~3: I2C Headers I²C (Inter-Integrated Circuit) headers connect to the System Management Bus (SMBus), FBP_I2C_1~3 are for the backplane. -
Page 38: Ocp: Ocp 3.0 Mezzanine Slot
OCP: OCP 3.0 Mezzanine Slot This slot enables the deployment of a wide variety of additional options through OCP (Open Compute Project) network interface cards (NICs) or other expansion cards. OCP: OCP 3.0 SFF (PCIe 5.0 x16) Top Side (B Pins) OB14 OA14 Bottom Side (A Pins) - Page 39 Top Side (B Pins) Bottom Side (A Pins) Mechanical Key P12V_AUX_OCP0 P12V_AUX_OCP0 P12V_AUX_OCP0 P12V_AUX_OCP0 P12V_AUX_OCP0 P12V_AUX_OCP0 PD_OCP0_NIC_BIF0_N SMB_CPU0_PE0_OCP0_LVC3_SCL PD_OCP0_NIC_BIF1_N SMB_CPU0_PE0_OCP0_LVC3_SDA PD_OCP0_NIC_BIF2_N RST_BMC_PCIE_MUX_R_LVC3_N RST_CPU0_PE0_OCP0_PERST0_N PD_CPU0_OCP0_NIC_PRSNTA_N P3V3_AUX_OCP0 RST_CPU0_PE0_OCP0_PERST1_N FM_OCP_NIC_AUX_PWR_LVC3_R_EN FM_CPU0_OCP0_NIC_PRSNTB2_N CLK_100M_CPU0_OCP0_0_DN CLK_100M_CPU0_OCP0_1_DN CLK_100M_CPU0_OCP0_0_DP CLK_100M_CPU0_OCP0_1_DP P5E_CPU0_PE0_OCP_TX_DN15 P5E_CPU0_PE0_OCP_RX_DN15 P5E_CPU0_PE0_OCP_TX_DP15 P5E_CPU0_PE0_OCP_RX_DP15 P5E_CPU0_PE0_OCP_TX_DN14 P5E_CPU0_PE0_OCP_RX_DN14 P5E_CPU0_PE0_OCP_TX_DP14 P5E_CPU0_PE0_OCP_RX_DP14 P5E_CPU0_PE0_OCP_TX_DN13 P5E_CPU0_PE0_OCP_RX_DN13 P5E_CPU0_PE0_OCP_TX_DP13...
- Page 40 Top Side (B Pins) Bottom Side (A Pins) P5E_CPU0_PE0_OCP_TX_DP8 P5E_CPU0_PE0_OCP_RX_DP8 FM_CPU0_OCP0_NIC_PRSNTB0_N FM_CPU0_OCP0_NIC_PRSNTB1_N Mechanical Key P5E_CPU0_PE0_OCP_TX_DN7 P5E_CPU0_PE0_OCP_RX_DN7 P5E_CPU0_PE0_OCP_TX_DP7 P5E_CPU0_PE0_OCP_RX_DP7 P5E_CPU0_PE0_OCP_TX_DN6 P5E_CPU0_PE0_OCP_RX_DN6 P5E_CPU0_PE0_OCP_TX_DP6 P5E_CPU0_PE0_OCP_RX_DP6 P5E_CPU0_PE0_OCP_TX_DN5 P5E_CPU0_PE0_OCP_RX_DN5 P5E_CPU0_PE0_OCP_TX_DP5 P5E_CPU0_PE0_OCP_RX_DP5 P5E_CPU0_PE0_OCP_TX_DN4 P5E_CPU0_PE0_OCP_RX_DN4 P5E_CPU0_PE0_OCP_TX_DP4 P5E_CPU0_PE0_OCP_RX_DP4 P5E_CPU0_PE0_OCP_TX_DN3 P5E_CPU0_PE0_OCP_RX_DN3 P5E_CPU0_PE0_OCP_TX_DP3 P5E_CPU0_PE0_OCP_RX_DP3 P5E_CPU0_PE0_OCP_TX_DN2 P5E_CPU0_PE0_OCP_RX_DN2 P5E_CPU0_PE0_OCP_TX_DP2 P5E_CPU0_PE0_OCP_RX_DP2 P5E_CPU0_PE0_OCP_TX_DN1 P5E_CPU0_PE0_OCP_RX_DN1 P5E_CPU0_PE0_OCP_TX_DP1 P5E_CPU0_PE0_OCP_RX_DP1 P5E_CPU0_PE0_OCP_TX_DN0...
-
Page 41: Dc-Scm: Dc-Scm 2.0 Edge Slot
DC-SCM: DC-SCM 2.0 Edge Slot The slot links the Datacenter Secure Control Module (DC-SCM) to the motherboard, enabling centralized power, management, and security control across server hardware. This standardized interface allows easy upgrades and compatibility across various platforms. DC-SCM: DC-SCM 2.0 (PCIe 5.0 x1, from CPU0) Top Side (B Pins) OB14... - Page 42 Top Side (B Pins) Bottom Side (A Pins) Mechanical Key CLK_66M_ESPI_CPU0_LVC18 P12V_AUX_SCM ESPI_CPU0_CS0_SCM_N P12V_AUX_SCM RST_ESPI_CPU0_LVC18_N P12V_AUX_SCM ESPI_CPU0_IO0_LVC18 P12V_AUX_SCM ESPI_CPU0_IO1_LVC18 ESPI_CPU0_IO2_LVC18 ESPI_CPU0_IO3_LVC18 IRQ_ESPI_CPU0_ALERT0_FPGA_LVC18_N BMC_JTAG_LVC3_TCK BMC_JTAG_LVC3_TDI BMC_JTAG_LVC3_TDO BMC_JTAG_LVC3_TMS SPI_CPU0_CLK_DCSCM_LVC18_R1 SPI_CPU0_CS0_DCSCM_LVC18_R1_N FM_HPM_STBY_RST_N SPI_CPU0_IO0_DCSCM_LVC18_R1 FM_HPM_STBY_EN SPI_CPU0_IO1_DCSCM_LVC18_R1 SMB_CHASSIS_SENSOR_STBY_LVC3_SCL SPI_CPU0_IO2_DCSCM_LVC18_R1 SMB_CHASSIS_SENSOR_STBY_LVC3_SDA SPI_CPU0_IO3_DCSCM_LVC18_R1 SMB_HSBP_SCM_LVC3_R_SCL SPI_CPU0_CS1_DCSCM_LVC18_R1_N SMB_HSBP_SCM_LVC3_R_SDA LVDS_LVC18_TX_DN LVDS_LVC18_RX_DN LVDS_LVC18_TX_DP LVDS_LVC18_RX_DP...
- Page 43 Top Side (B Pins) Bottom Side (A Pins) I3C_MNG_SCM_LVC1_R_SCL I3C_MNG_SCM_LVC1_R_SDA Mechanical Key CLK3_50M_SCM_RMII_CLK SMB_PCIE_SCM_LVC3_R_SCL RMII3_SCM_CRS_DV_R SMB_PCIE_SCM_LVC3_R_SDA RMII3_SCM_TX_EN_R SMB_IPMB_LVC3_CLK RMII3_SCM_TXD0 SMB_IPMB_LVC3_DAT RMII3_SCM_TXD1 SMB_CPLD_UPDATE_SCM_LVC3_R_SCL RMII3_SCM_RXD0 SMB_CPLD_UPDATE_SCM_LVC3_R_SDA RMII3_SCM_RXD1 SMB_PMBUS1_LVC3_SCL VCC3_FRU_SCM SMB_PMBUS1_LVC3_SDA UART0_TX_SCM_HPM_DATA BMC_SMB_LVC18_CLK1 SMB_HOST_STBY_LVC3_SCL BMC_SMB_LVC18_DAT1 SMB_HOST_STBY_LVC3_SDA GND-31 DBP_ASD_SCM_PREQ_LVC3_R_N SPI_CPU0_TPM_CLK_LVC18_MUX_R1 DBP_ASD_SCM_PRDY_LVC3_R_N SPI_CPU0_TPM_CS_LVC18_MUX_R1_N SMB16_IPMB_LVC3_SCL SPI_CPU0_TPM_MOSI_LVC18_MUX_R1 SMB16_IPMB_LVC3_SDA SPI_CPU0_TPM_MISO_LVC18_MUX_R1 FM_SCM_PRSNT0_LVC3_N...
-
Page 44: Jchassis1: Chassis Intrusion Header
JCHASSIS1: Chassis Intrusion Header This header connects to the chassis intrusion switch cable, which monitors and detects any unauthorized opening in the server’ s chassis. When the chassis is opened, this header sends a signal to notify the Baseboard Management Controller (BMC) to record the intrusion event or trigger an alert for administrators. -
Page 45: Bat1: Cmos Battery
BAT1: CMOS Battery If the CMOS battery is out of charge, the time in the BIOS will be reset and the data of system configuration will be lost. In this case, you need to replace the CMOS battery. Replacing CMOS battery 1. -
Page 46: Jumpers
Jumpers Important ⚠ Avoid adjusting jumpers when the system is on; it will damage the motherboard. J_PASSWORD_C_1 J_TAG_SEL2 JBAT1 J_UART_SEL_1 JBAT2 JBAT7 Jumper Name Default Setting Description Password Clear Jumper J_PASSWORD_C_1 1-2: Normal (default) 2-3: Clear password JTAG Select Jumper JTAG_SEL_2 1-2: BMC to CPLD 2-3: BMC to CPU (default) -
Page 47: Onboard Leds
Onboard LEDs LED_H1, LED_L1: Port 80 Debug LEDs The Port 80 Debug LEDs display progress and error codes during and after POST (Power-On Self Test). Hexadecimal Character Table Hexadecimal LED display Hexadecimal LED display... - Page 48 EPS.MSI.COM MSI.COM...
Need help?
Do you have a question about the D3061 and is the answer not in the manual?
Questions and answers