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TA785GE/TA785GE 128M BIOS Manual
DRAM Timing Configuration
DRAM Timing Config uration
Mem ory CLK
CAS Latency(Tcl)
RAS /CAS Delay(Tr cd)
Row Precharge Ti me(Trp)
Min Active RAS(T ras)
RAS /RAS Delay(Tr rd)
Row Cycle (Trc)
Com mand Rate(CR)
Wri te Recover Ti me(Twr)
> Memory Configuratio n
> ECC Configuratio n
Memor y Clock Mode
DRAM Timing Mode
vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc.
Memory Configuration
Memor y Configurati on
Bank Interleaving
Chann el Interleavi ng
Enabl e Clock to Al l DIMMs
MemCl k Tristate C3 /ATLVID
Memor y Hole Remapp ing
DCT U nganged Mode
Power Down Enable
vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc.
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
perform ance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options:
Auto (Default) / Disabled
BIOS S ETUP UTILITY
T-Series
[ Auto]
[ Auto]
BIOS S ETUP UTILITY
T-Series
[ Auto]
[ XOR of Addre ss bit]
[ Disabled]
[ Disabled]
[ Enabled]
[ Always]
[ Disabled]
35
S elect Screen
S elect Item
G o to Sub Scr een
En ter
F1
G eneral Help
F1 0
S ave and Exit
ES C
E xit
Enab le Bank Memo ry
Inte rleaving
S elect Screen
S elect Item
+-
C hange Option
F1
G eneral Help
F1 0
S ave and Exit
ES C
E xit
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