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PCI-6052E
Programmer's manual
National Instruments PCI-6052E Programmer's Manual
Register-level programmer manual, multifunction i/o boards for pci bus computers, register-level
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User manual
(265 pages)
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
About this Manual
Conventions Used in this Manual
Organization of this Manual
Customer Communication
Related Documentation
Chapter 1 General Description
General Characteristics
Chapter 2 Theory of Operation
Figure 2-1. PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram
Functional Overview
Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram
Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram
Figure 2-4. PCI-6032E and PCI-6033E Block Diagram
Figure 2-5. PCI-MIO-16XE-50 Block Diagram
PCI Interface Circuitry
Analog Input and Timing Circuitry
Figure 2-6. PCI Bus Interface Circuitry Block Diagram
Analog Input Circuitry
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram
Table 2-1. PGIA Gain Set Verses Board
Data Acquisition Timing Circuitry
Single-Read Timing
Data Acquisition Sequence Timing
Figure 2-8. ADC Timing
Figure 2-9. Timing of Scan in Example 1
Figure 2-10. Multirate Scanning of Two Channels
Figure 2-11. Multirate Scanning of Two Channels with 1:X Sampling Rate
Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate
Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate
Figure 2-14. Multirate Scanning Without Ghost
Figure 2-16. Successive Scans Using Ghost
Posttrigger and Pretrigger Acquisition
Table 2-2. Analog Input Configuration Memory
Analog Triggering
Analog Output and Timing Circuitry
Figure 2-17. Analog Output Circuitry Block Diagram
Analog Output Circuitry
Analog Output Timing Circuitry
Single-Point Output
Waveform Generation
Digital I/O Circuitry
Figure 2-18. DAQ-STC Counter Diagram
Timing I/O Circuitry
RTSI Bus Interface Circuitry
Figure 2-19. RTSI Bus Interface Circuitry Block Diagram
Chapter 3 Register Map and Descriptions
Register Map
Table 3-1. PCI E Series Register Map
Register Sizes
Register Descriptions
Misc Register Group
Table 3-2. PCI E Series Windowed Register Map
Serial Command Register
Misc Command Register
Status Register
Analog Input Register Group
ADC FIFO Data Register
Configuration Memory Low Register
Table 3-3. PGIA Gain Selection
Configuration Memory High Register
Table 3-4. Calibration Channel Assignments
Table 3-5. Differential Channel Assignments
Table 3-6. Nonreferenced Single-Ended Channel Assignments
Table 3-7. Referenced Single-Ended Channel Assignments
Analog Output Register Group
Table 3-8. Auxiliary Channel Assignments
Table 3-9. Channel Assignments
AO Configuration Register
DAC FIFO Data Register
DAC0 Direct Data Register
DAC1 Direct Data Register
DMA Control Register Group
AI AO Select Register
G0 G1 Select Register
DAQ-STC Register Group
FIFO Strobe Register Group
ADC FIFO Clear Register
Configuration Memory Clear Register
DAC FIFO Clear Register
Chapter 4 Programming
Pcl Local Bus
PCI Initialization for the IBM Compatible System
Re-Mapping the PCI E Series Board
PCI Initialization for the Macintosh
Programming Examples
Windowing Registers
Digital I/O
Example 1
Example 2
Analog Input
Example 1
Example 2
Example 3
Example Program
Example 4
Programming the MITE for Different DMA Transfers
Call the Function Number_Of_Scans to Load the Number of Scans
AI Configuration Start = 1; Ai_Sc_Load_A_Registers (24 Bits) Number of Posttrigger Scans -1 = 4; Ai_Command_1_Register
AI SC Load = 1
Joint_Reset_Register
Example 5
Perform Analog Input Example 1 Step 1
Perform Analog Input Example 1 Step 2 for each Channel in the Scan List. Only Channel 0 Has Last Channel Set to
Perform Analog Input Example 1 Steps
Example 6
Example 7
Joint_Reset_Register
Example 8
AI Configuration Start = 0; AI Configuration End = 1; the Function Ai_Scan_Start
Perform Analog Input Example 1 Step
Example 9
The Function Ai_Scan_Start Selects the Scan Start Event
AI Configuration Start = 0; AI Configuration End
AI Configuration Start = 1
Ai_Command_1_Register
Joint_Reset_Register
Analog Output
Example 1
Example 2
Example 2
Example 3
Example 3
Example 4
Example 5
Example Program
General-Purpose Counter/Timer
Example 1
Example 2
Example 3
Analog Triggering
RTSI Trigger Lines Programming Considerations
Figure 4-1. Analog Trigger Structure
Interrupt Programming
Interrupt Sharing
DMA Programming
Figure 4-2. DMA Structure
The Link Chaining Mode for DMA Transfer
Figure 4-3. DMA Link Chaining Mode Structure
Chapter 5 Calibration
About the EEPROM
Figure 5-1. EEPROM Read Timing
Table 5-1. PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6071E EEPROM Map
Table 5-2. PCI-MIO-16XE-50 EEPROM Map
Table 5-3. PCI-MIO-16XE-10, PCI-6031E, PCI-6032E and PCI-6033E EEPROM Map
Table 5-4. PCI-6023E EEPROM Map
Table 5-5. PCI-6024E and PCI-6025E EEPROM Map
Table 5-6. PCI-6052E EEPROM Map
Calibration Dacs
Figure 5-2. Calibration AC Write Timing
NI-DAQ Calibration Function
Appendix A Customer Communication
Glossary
Index
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Quick Links
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General Characteristics
2
Figure 2-1. Pci-Mio-16E-1, Pci-Mio-16E-4, and Pci-6071E Block Diagram
3
Figure 2-3. Pci-6023E, Pci-6024E, and Pci-6025E Block Diagram
4
Pci Interface Circuitry
Download this manual
See also:
User Manual
DAQ
PCI E Series Register-Level
Programmer Manual
Multifunction I/O Boards for PCI Bus Computers
PCI E Series RLPM
November 1998 Edition
Part Number 341079B-01
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