NSING N32L40 Series User Manual

32-bit arm cortex-m4f microcontroller

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N32L40x series

32-bit ARM® Cortex

-M4F microcontroller

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Page 1 N32L40x series ® 32-bit ARM® Cortex -M4F microcontroller User manual 1 / 677...
Page 2: Table Of Contents
Contents 1 Abbreviations in the text ..............................1 Describes the list of abbreviations used in the register table ..................1 Available peripherals ..............................1 2 Memory and bus architecture ............................2 System architecture..............................2 Bus architecture ..............................2 Bus address mapping ............................3 Boot management ..............................
Page 3 RTC clock ................................ 58 Watchdog clock ............................... 58 Clock output (MCO) ............................58 RCC Registers ................................59 RCC register overview ............................59 Clock Control Register (RCC_CTRL) ......................60 Clock Configuration Register (RCC_CFG) ....................... 62 Clock Interrupt Register (RCC_CLKINT) ......................65 APB2 Peripheral Reset Register (RCC_APB2PRST) ..................
Page 4 Nested vector interrupt register ..........................124 SysTick calibration value register........................124 Interrupt and exception vectors ........................124 External interrupt/event controller (EXTI) ......................127 Introduction ..............................127 Main features ..............................127 Functional description ............................. 128 EXTI line image .............................. 129 EXTI registers ................................ 130 EXTI registers overview ..........................
Page 5 CRC32 independent data register (CRC_CRC32IDAT).................. 155 CRC32 control register (CRC_CRC32CTRL) ....................156 CRC16 control register (CRC_CRC16CTRL) ....................156 CRC16 input data register (CRC_CRC16DAT) ....................157 CRC cyclic redundancy check code register (CRC_CRC16D) ............... 157 LRC result register (CRC_LRC) ........................158 9 Cryptographic algorithm hardware acceleration engine (SAC) ................
Page 6 Capture/compare register 5 (TIMx_CCDAT5) ....................223 Capture/compare register 6 (TIMx_CCDAT6) ....................224 11 General-purpose timers (TIM2, TIM3, TIM4, TIM5 and TIM9) ................225 General-purpose timers introduction ........................225 Main features of General-purpose timers ......................... 225 General-purpose timers description ......................... 226 Time-base unit ..............................
Page 7 Control Register 2 (TIMx_CTRL2)....................... 284 DMA/Interrupt Enable Registers (TIMx_DINTEN) ..................285 Status Registers (TIMx_STS) ........................285 Event Generation registers (TIMx_EVTGEN) ....................286 Counters (TIMx_CNT) ..........................286 Prescaler (TIMx_PSC) ..........................286 Automatic reload register (TIMx_AR) ......................287 13 Low Power Timer (LPTIM) ............................288 Introduction ................................
Page 8 Tamper detection ............................318 Daylight saving time configuration ......................319 RTC reset ..............................319 RTC sub-second register shift operation ...................... 319 RTC digital clock precision calibration ....................... 319 RTC low power mode ..........................321 RTC Registers ............................... 321 RTC Register overview ..........................321 RTC Calendar Time Register (RTC_TSH) ....................
Page 9 WWDG control register (WWDG_CTRL) ....................351 WWDG config register (WWDG_CFG) ....................... 351 WWDG status register (WWDG_STS) ......................352 17 Analog to digital conversion (ADC) ..........................353 Introduction ................................353 Main features ................................353 Function Description............................... 354 ADC clock ..............................355 ADC switch control ............................
Page 10 DAC trigger ..............................386 DAC conversion ............................387 DAC output voltage ............................387 DMA requests ..............................387 The noise ............................... 388 Triangular wave generation ........................... 389 DAC register ................................. 390 DAC registers overview ..........................390 DAC control register (DAC_CTRL) ......................391 DAC software trigger register (DAC_SOTTR) .....................
Page 11 OPAMP Control Status Register (OPAMP2_CS) ..................417 OPAMP Lock register (OPAMP_LOCK) ...................... 419 21 Liquid Crystal Display Controller (LCD) ........................ 420 Introduction ................................420 Main features ................................ 420 Functional block diagram ............................. 421 Functional description ............................422 Frequency generator ............................422 Common end driver ............................
Page 12 Function description ............................. 478 USART frame format ............................ 479 Transmitter..............................480 Receiver ................................. 482 Generation of fractional baud rate ......................... 485 Receiver’s tolerance clock deviation ......................486 Parity control ..............................487 DMA application ............................488 Hardware flow control ........................... 490 Multiprocessor communication ........................
Page 13 S features ..............................535 SPI function description ............................536 General description ............................536 SPI work mode .............................. 539 Status flag ..............................545 Disabling the SPI ............................546 SPI communication using DMA ........................547 CRC calculation............................. 548 Error flag ............................... 549 SPI interrupt ..............................
Page 14 CAN register address overview ........................595 CAN control and status register ........................598 CAN mailbox register ............................ 609 CAN filter register ............................614 27 Universal serial bus full-speed device interface (USB_FS_Device) ............... 618 Introduction ................................618 Main features ................................ 618 Clock configuration ..............................
Page 15 List of tables Table 2-1 List of peripheral register addresses ......................4 Table 2-2 List of boot mode ............................7 Table 2-3 Flash bus address list ........................... 8 Table 2-4 Option byte list ............................13 Table 2-5 Read protection configuration list ......................15 Table 2-6 Flash read-write-erase permission control table ..................
Page 16 Table 5-24 SPI2/I2S2 alternate function remapping ....................105 Table 5-25 COMP1 alternate function remapping ....................105 Table 5-26 COMP2 alternate function remapping ....................105 Table 5-27 EVENTOUT alternate function remapping ................... 106 Table 5-28 RTC alternate function remapping ......................106 Table 5-29 LCD alternate function remapping ......................
Page 17 Table 11-2 Register overview ..........................255 Table 11-3 TIMx internal trigger connection ......................262 Table 11-4 Output control bits of standard OCx channel ..................272 Table 12-1 Register overview ..........................283 Table 13-1 Pre-scaler division ratios ........................290 Table 13-2 9 trigger inputs corresponding to LPTIM_CFG.TRGSEL[2:0] bits ............291 Table 13-3 Encoder counting scenarios ........................
Page 18 Table 23-3 Error calculation when setting baud rate ....................486 Table 23-4 when DIV_Decimal = 0. Tolerance of USART receiver ............... 487 Table 23-5 when DIV_Decimal != 0. Tolerance of USART receiver ..............487 Table 23-6 Frame format ............................487 Table 23-7 USART interrupt request ........................
Page 19 List of figures Figure 2-1 Bus architecture ............................2 Figure 2-2 Bus address map ............................4 Figure 3-1 Power supply block diagram ........................33 Figure 3-2 Brown-out reset (BOR) waveform ......................34 Figure 3-3 PVD threshold waveform ........................35 Figure 4-1 System reset generation ........................... 51 Figure 4-2 Clock Tree ..............................
Page 20 Figure 10-17 Capture/compare channel 1 main circuit .................... 175 Figure 10-18 Output part of channelx (x= 1,2,3, take channel 1 as example) ............176 Figure 10-19 Output part of channelx (x= 4) ......................176 Figure 10-20 PWM input mode timing........................178 Figure 10-21 Output compare mode, toggle on OC1 ....................
Page 21 Figure 11-18 Center-aligned PWM waveform (AR=8) ................... 244 Figure 11-19 Edge-aligned PWM waveform (APR=8) ................... 245 Figure 11-20 Example of One-pulse mode ......................246 Figure 11-21 Control circuit in reset mode ......................248 Figure 11-22 Block diagram of timer interconnection ..................... 249 Figure 11-23 TIM2 gated by OC1REF of TIM1 .....................
Page 22 Figure 17-7 Temperature sensor and VREFINT Diagram of the channel ............... 366 Figure 18-1 Block diagram of a DAC channel ......................384 Figure 18-2 Data register of single DAC channel mode ..................386 Figure 18-3 Time diagram of transitions with trigger disable ................. 387 Figure 18-4 LFSR algorithm for DAC ........................
Page 23 Figure 23-7 Transmission using DMA ........................489 Figure 23-8 Reception using DMA ......................... 490 Figure 23-9 hardware flow control between two USART ..................490 Figure 23-10 RTS flow control ..........................491 Figure 23-11 CTS flow controls ..........................492 Figure 23-12 Mute mode using idle line detection ....................493 Figure 23-13 Mute mode detected using address mark ...................
Page 24 duplex mode ................................543 Figure 25-9 Schematic diagram of TE/BUSY change during continuous transmission in slave unidirectional transmit- only mode ................................543 Figure 25-10 Schematic diagram of TE/BUSY change when BIDIRMODE = 0 and RONLY = 0 are transmitted discontinuously ................................ 545 Figure 25-11 Transmission using DMA ........................
Page 25 Figure 27-2 The user applications on the microcontrollers and the USB modules access Packet Buffer Memory . 620 Figure 27-3 The relationship between the buffer description table and the endpoint packet buffer ......621 Figure 27-4 Double buffered bulk endpoint example ....................624 Figure 27-5 Control transfer ............................
Page 26: Abbreviations In The Text
1 Abbreviations Abbreviations The following abbreviations are used in the description of registers: read/write(rw) Software can read and write this bit. read-only(r) Software can only read this bit. write-only(w) Software can only write this bit, and reading this bit will return the reset value. read/clear(rc_w1) Software can read this bit or clear it by writing' 1', and writing' 0' has no effect on this bit.
Page 27: Memory And Bus Architecture
2 Memory And Bus Architecture System Architecture Bus Architecture Figure 2-1 Bus Architecture TPIU Flash SW/JTAG Flash ICode Control iCache DCode Cortex-M4FP Core SBus Fmax:64MHz SRAM NVIC AFIO LPTIM EXTI EXTI AFIO TIM2 GPIOA GPIOA USART1 TIM3 GPIOB GPIOB UART4 GPIOA TIM4 GPIOC...
Page 28: Bus Address Mapping
• ® DCode bus: This bus connects the DCode bus of Cortex -M4F core with the data interface of flash memory (constant loading and debugging access). • SBus: This bus connects the SBus bus (peripheral bus) of Cortex ® -M4F core to the bus matrix, which coordinates the access between the core and DMA.
Page 29: Table 2-1 List Of Peripheral Register Addresses
Figure 2-2 Bus Address Map Reserved 0x4002_4800 – 0x5FFF_FFFF SAC SRAM 512B*2 0x4002_4400 – 0x4002_47FF 0x4002_4000 – 0x4002_43FF Reserved 0x4002_3400 – 0x4002_3FFF 0xE010_0000 – 0xFFFF_FFFF Reserved 0x4002_3000 – 0x4002_33FF Reserved 0x4002_2400 – 0x4002_2FFF FLASH Vendor Specific 511MB 0x4002_2000 – 0x4002_23FF Reserved 0x4002_1400 –...
Page 30 Address Range Peripherals 0x4002_0400 – 0x4002_07FF Reserved 0x4002_0000 – 0x4002_03FF 0x4001_8000 – 0x4001_FFFF Reserved 0x4001_5800 – 0x4001_7FFF Reserved 0x4001_5400 – 0x4001_57FF UART5 0x4001_5000 – 0x4001_53FF UART4 0x4001_4400 – 0x4001_4FFF Reserved 0x4001_3C00 – 0x4001_43FF SPI2/I2S2 0x4001_3800 – 0x4001_3BFF USART1 0x4001_3400 – 0x4001_37FF TIM8 0x4001_3000 –...
Page 31: Bit Banding
Address Range Peripherals 0x4000_2000 – 0x4000_23FF OPAMP 0x4000_1C00 – 0x4000_1FFF Reserved 0x4000_1800 – 0x4000_1BFF Reserved 0x4000_1400 – 0x4000_17FF TIM7 0x4000_1000 – 0x4000_13FF TIM6 0x4000_0C00 – 0x4000_0FFF TIM5 0x4000_0800 – 0x4000_0BFF TIM4 0x4000_0400 – 0x4000_07FF TIM3 0x4000_0000 – 0x4000_03FF TIM2 Bit banding ®...
Page 32: Boot Configuration
be re-sampled and the option byte boot configuration (USER2) will be re-sampled. After a startup delay has elapsed, the CPU fetches the top of stack value from address 0x0000_0000 and executes the code from the reset vector address indicated by address 0x0000_0004.Because of the Cortex®-M4F always gets the top-of stack value and reset vector from addresses 0x0000_0000 and 0x0000_0004, so boot is only suitable for booting from the CODE area, and address remapping is designed for boot space.
Page 33: Embedded Boot Loader
Specifies the start address for accessing Boot mode select pin memory space in boot mode Boot mode System nBOOT1 nBOOT0 BOOT0 pin nSWBOOT0 Main Flash SRAM Memory 0x2000 0000 0x1000 0000 Embedded boot loader The embedded boot-loader is stored in the System Memory and is used to reprogram the flash memory via the USART1 or USB-FS interface (Full-Speed USB device, DFU protocol).
Page 34 Memory Area Page Name Address Range Size Page 2 0x0800_1000 – 0x0800_17FF Page 63 0x0801_F800 – 0x0801_FFFF System memory area 0x1FFF_0000 – 0x1FFF_3FFF 16KB Information block System configuration area 0x1FFF_F000 – 0x1FFF_F7FF Option byte area 0x1FFF_F800 – 0x1FFF_F813 FLASH_AC 0x4002_2000 – 0x4002_2003 FLASH_KEY 0x4002_2004 –...
Page 35 the minimum block size for erasing is one page, which is 2KB. Write operation is divided into programming and erasing phases. When reading Flash, the number of waiting cycles for reading can be configured by the register. When using, it needs to be calculated in combination with the clock frequency of AHB interface.
Page 36 • Mass Erase Mass Erase process: • Check the FLASH_ STS.BUSY bit to confirm that there are no other flash operations in progress; • Set the FLASH_CTRL.MER bit to' 1'; • Set the FLASH_CTRL.START bit to' 1'; • Wait for the FLASH_ STS.BUSY bit to change to' 0'; •...
Page 37: Option Byte
• Read the erased option byte and verify it. Option byte area programming process: • Check the FLASH_ STS.BUSY bit to confirm that there are no other flash operations in progress; • Set the FLASH_CTRL.OPTWE bit to '1'; • Set the FLASH_CTRL.OPTPG bit to '1'; •...
Page 38: Table 2-4 Option Byte List
Table 2-4 Option Byte List [31:24] [15:8] [23:16] [7:0] Address Corresponding Corresponding Option byte Option byte complement code complement code 0x1FFF_F800 nUSER USER nRDP1 RDP1 0x1FFF_F804 nData1 Data1 nData0 Data0 0x1FFF_F808 nWRP1 WRP1 nWRP0 WRP0 0x1FFF_F80C nWRP3 WRP3 nWRP2 WRP2 0x1FFF_F810 nUSER2 USER2...
Page 39: Write Protect
− WRP3: write protection of pages 48-63, bit [0] corresponds to Page48 /49., bit [7] corresponds to Page62 / • Read protection L2 level option byte: RDP2 − Add protection function on the basis of L1, refer to the detailed description of read protection in setion 2.2.1.9;...
Page 40: Table 2-5 Read Protection Configuration List
Table 2-5 Read Protection Configuration List Read Protection Status RDP1 nRDP1 nRDP2 RDP2 L1 level 0xFF 0xFF RDP2! = 0xCC || nRDP2! = 0x33 Unprotected 0xA5 0x5A RDP2! = 0xCC || nRDP2! = 0x33 L2 level 0xXX 0xXX 0x33 0xCC L1 level Not the above three configurations •...
Page 41: Table 2-6 Flash Read-Write-Erase
− The following access operations to the flash memory will be prohibited: • Access main flash memory from built-in SRAM start execution code (including using DMA); • Access the main flash memory by JTAG, SWV (serial line observer), SWD (serial line debugging) and boundary scanning;...
Page 42 Read-Write- Read-Write- Read-Write- Flash option byte area Read-Write-Erase Erase Erase Erase Flash system memory Prohibit Prohibit Read-write-erase Prohibit area Read and Read and Read and SRAM (All) Read and write write write write First 4KB of flash Read-only Read-only Read-only main memory area Last 4KB of flash Read-write-...
Page 43 Flash system memory Prohibit Prohibit Read-write-erase Prohibit area Read and Read and Read and SRAM (All) Read and write write write write First 4KB of flash Prohibit Read-only Read-only Prohibit main memory area Last 4KB of flash Read-write- Prohibit Read-write-erase Prohibit main memory area erase...
Page 44 level Level Perform user JTAG/SWD Main Flash System Memory SRAM Access to areas First 4KB of flash Read-write- Read-write- Read-write- Read-write-erase main memory area erase erase erase Last 4KB of flash Read-write- Read-write- Read-write- Read-write-erase main memory area erase erase erase Flash main memory Allow...
Page 45: Icache
Flash main memory Allow Allow Allow area mass erase Flash option byte area Read-only Read-only Read-only Flash system memory Prohibit Read-write-erase Prohibit area Read and Read and SRAM (All) Read and write write write Note: . Erase here refers to flash page erase; iCache To achieve higher system performance, an instruction cache needs to be added between the high-speed CPU and the low-speed Flash to improve the instruction execution efficiency.
Page 46 − When using icache, there is no Write-Back(WB) or Write-Through(WT) selection when the CPU writes operation. Register description FLASH_AC.ICAHEN and FLASH_AC.ICAHRST are the iCache enable switch and iCache data clear switch respectively. FLASH_CAHR.LOCKSTRT and FLASH_CAHR.LOCKSTOP respectively control the enabling and data clearing of iCache.
Page 47: Sram
SRAM SRAM is mainly used for code operation to store variables and data or stacks during program execution. The maximum capacity is 24KB，it is divided into SRAM1 and SRAM2, of which SRAM1 is up to 16K bytes and SRAM2 is 8K bytes(SRAM2 supports parity check and needs to be initialized before use). SRAM supports read-write access of byte, half-word and word.
Page 48 Offset Register FLASH_OB2 BOR_LEV 018h Reserved Reserved Reserved Reset Value FLASH_OB Data1 Data0 Not Used 01Ch Reserved Reset Value FLASH_WRP WRPT 020h Reset Value FLASH_ECC 024h Reserved Reset Value 028h Reserved 02Ch FLASH_CAHR 030h Reserved Reset Value FLASH control and status register For abbreviations related to register descriptions, please refer tosection 1.1.
Page 49 Bit Field Name Description 1: Enable FLASH low-voltage working mode. Note: FLASH_AC.LATENCY must be greater than 0x02 to enable FLASH low voltage operation mode. LVMF FLASH low voltage working mode flag 0: FLASH is not working in low voltage working mode; 1: FLASH works in low voltage working mode.
Page 50 2.2.4.2.3 The FLASH OPTKEY register (FLASH_OPTKEY) Address offset: 0x08 Reset value: 0xXXXX XXXX Bit Field Name Description 31:0 OPTKEY Used to unlock the FLASH_CTRL.OPTWE bit. 2.2.4.2.4 The FLASH status register (FLASH_STS) Address offset: 0x0C Reset value: 0x0000 0000 Bit Field Name Description 31:8...
Page 51 Bit Field Name Description hardware sets this bit to '1', and writing '1' can clear this state. Note: Before programming, the FLASH_CTRL.START bit must be cleared. Reserved Reserved, the reset value must be maintained. BUSY Busy This bit indicates that a flash operation is in progress. At the beginning of flash operation, this bit is set to '1';...
Page 52 Bit Field Name Description correct key sequence is written in the FLASH_OPTKEY register, this bit is set to '1'. Software can clear this bit. SMPSEL Flash programming mode options 0: SMP1 mode. Before programming, you need to read the content of the address where the programming is located, and check whether it has been erased.
Page 53 Reset value: 0x0000 0000 Bit Field Name Description 31:0 FADD Flash address Select the address to be programmed when programming, and select the page to be erased when page erasing. Note: When the FLASH_STS.BUSY bit is '1', this register cannot be written. 2.2.4.2.7 The FLASH Option byte register 2 (FLASH_OB2) Address offset: 0x18 Reset value: 0x0c800000...
Page 54 Management. 2.2.4.2.8 Option byte register (FLASH_OB) Address offset: 0x1C Reset value: 0x03FF FFFC Bit Field Name Description RDPRT2 Read protection L2 level protection 0: Read protection L2 level is not enabled; 1: Read protection L2 level is enabled. Note: This bit is read-only. 30:26 Reserved Reserved, the reset value must be maintained.
Page 55 2.2.4.2.9 Write protection register (FLASH_WRP) Address offset: 0x20 Reset value: 0xFFFF FFFF Bit Field Name Description 31:0 WRPT Write protect This register contains the write protection option byte loaded by option byte area. 0: write protection takes effect; 1: Write protection is invalid. Note: These bits are read-only.
Page 56 Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. LOCKSTOP[3:0] iCache lock stop (see for detailed operation instructions 2.2.2.3.3 iCache locking Chapter). 0: disable 1: enable LOCKSTRT[3:0] iCache lock start. 0: disable 1: enable 31 / 652...
Page 57: Power Control (Pwr)
3 Power Control (PWR) General Description The PWR is power management unit to control status of different modules in different power modes. Its major function is to control MCU to enter different power modes and wakeup when events or interrupts happen. The MCU supports the following modes: RUN, LOW-POWER RUN, SLEEP, LOW-POWER SLEEP, STOP2 and STANDBY mode.
Page 58: Figure 3-1 Power Supply Block Diagram
voltage regulators power all digital circuits. The regulator is always enabled after reset. • The output voltage range of MR can be adjusted by PWR_CTRL1.MRSEL[1:0]. It is mainly used in RUN mode and SLEEP mode of MCU. MR is disabled when MCU is in LOW-POWER RUN, LOW-POWER SLEEP, STOP2, STANDBY mode.
Page 59: Power Supply Supervisor
Power Supply Supervisor Power on reset (POR) and brown out reset (BOR) Power-on reset (POR) and brown-out reset (BOR) circuits are integrated inside the chip. BOR is active in all power modes and cannot be disabled. Five BOR thresholds can be selected via the option byte. During power-on, the BOR will hold the chip in reset until the supply voltage (V ) reaches the specified threshold.
Page 60: Power Modes
Figure 3-3 PVD Threshold Waveform VDD/VDDA 100mV PVD threshold hysteresis PVD output Power Modes The MCU has 6 power modes: RUN, SLEEP, LOW POWER RUN, LOW POWER SLEEP, STOP2 and STANDBY. Different mode has different performance and power consumption. A summary of MCU power modes is shown below. Table 3-1 Power Modes Mode Regulator...
Page 61: Table 3-2 Blocks Running State
Mode Regulator Enter Exit Wakeup state need to be reconfigured, MSI = 4M WFI/WFE： 3 WKUP IO rising/falling 1）SCB_SCR.SLEEPDEEP = 1 edges, RTC alarm rising edge, STANDBY System reset 2）PWR_CTRL1.LPMSEL = NRST reset, IWDG reset, RTC “011” timestamp, tamper detection Notes: 1.
Page 62: Run Mode
Stop2 Standby Main Blocks LPUART TIM1/8 TIM2/3/4/5 TIM6/7 WWDG USART1/2/3 UART4/5 I2C1/2 SPI1/2 UCDR TempSensor OPAMP COMP TRNG GPIOs 3 pins Notes: 1. Y: Yes (Enable), O: Option, -: Not available. 2. Only COMP1 support STOP2 mode 3. 3 pins represent three wake-up IOs, PA8, PA0 and PC13. RUN Mode RUN mode is the normal operating mode of the MCU.
Page 63: Sleep Mode
Dynamic Voltage Regulation (MR) Steps to enter MR 1.0V: • Make sure the system clock is at most 64MHz. Note that if the current operating mode is LP RUN, then the maximum system clock is 4MHz; • Configure the FLASH read cycle to be greater than or equal to 2. This step is to avoid FLASH timing problem when entering the low-voltage mode;...
Page 64: Exiting Sleep Mode
from the lowest priority ISR. Exiting SLEEP Mode If the WFI instruction is used to enter the SLEEP mode, any NVIC interrupts can wake up the device from the SLEEP mode. If the WFE instruction is used to enter the SLEEP mode, MCU will exit the SLEEP mode immediately when the event occurs.
Page 65: Low Power Sleep Mode
• Turn on or off the digital peripheral clock according to actual needs; • Turn off unnecessary analog peripherals; • If FLASH is not used, in order to further reduce power consumption, user can configure FLASH_AC.SLMEN = 1 to put FLASH into sleep mode. Configuring FLASH_AC.SLMEN = 0 will restore the current state of FLASH.
Page 66: Entering Stop2 Mode
Entering STOP2 Mode To enter STOP2 mode, should be configured: SCB_SCR.SLEEPDEEP = 1, PWR_CTRL1.LPMSEL = "000~010". In STOP2 mode, if FLASH is being operated, entering STOP2 mode will be delayed until the memory access is completed. If the access to the APB area is in progress, entering the STOP2 mode will be delayed until the APB access is completed.
Page 67: Exiting Standby Mode
• RTC optional: It can be turned on by RCC_LDCTRL.RTCEN. • Internal RC oscillator (LSI RC) optional: It can be turned on by RCC_CTRLSTS.LSIEN. • External 32.768kHz crystal oscillator (LSE OSC) optional: It can be turned on by RCC_LDCTRL.LSEEN bit. Unneeded analog peripherals such as ADC and DAC can be disabled when entering STANDBY mode to avoid unnecessary power consumption.
Page 68: Power Control Register 1 (Pwr_Ctrl1)
Offset Register Reset Value PWR_CTRL2 004h Reserved Reset Value PWR_CTRL3 008h Reserved Reset Value PWR_STS1 00Ch Reserved Reserved Reserved Reset Value PWR_STS2 010h Reserved Reset Value PWR_STSCLR 014h Reserved Reserved Reset Value Power Control Register 1 (PWR_CTRL1) Address offset: 0x00 Reset value: 0x0000 0700 (reset by wakeup from STANDBY mode) Bit Field Name...
Page 69: Power Control Register 2 (Pwr_Ctrl2)
Bit Field Name Description DRBP Disable RTC, backup registers and write protection of RCC_LDCTRL register. In the reset state, the RTC, backup registers and RCC_LDCTRL registers are protected from illegal writes. This bit must be set to enable write access to these registers. 0: Disable access to RTC, backup registers and RCC_LDCTRL 1: Enable access to RTC, backup registers and RCC_LDCTRL Note: This bit must remain 1 if HSE is divided by 32 as the RTC clock.
Page 70: Power Control Register 3 (Pwr_Ctrl3)
Bit Field Name Description 0: Disable PVD 1: Enable PVD Power Control Register 3 (PWR_CTRL3) Address offset: 0x08 Reset value: 0x0007 0700 (reset by wakeup from STANDBY mode) Bit Field Name Description 31:22 Reserved Reserved, the reset value must be maintained. PSTSTP2 Pin state bit in STOP2 mode.
Page 71 Bit Field Name Description 0: No retention 1: Retention Reserved Reserved, the reset value must be maintained. BGDTSTBY BANDGAP/BG_Buffer/IBIAS idle state bit in STANDBY mode. 0: Always on 1: Duty on BGDTSTP2 BANDGAP/BG_Buffer/IBIAS idle state bit in STOP2 mode. 0: Always on 1: Duty on BGDTLPR BANDGAP/BG_Buffer/IBIAS idle state bit in LP RUN mode.
Page 72: Power Status Register 1 (Pwr_Sts1)
Bit Field Name Description 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin will not wake the device from STANDBY mode. 1: WKUP pin is used to wake up STANDBY mode. Power Status Register 1 (PWR_STS1) Address offset: 0x0C Reset value: 0x0000 0000 (Power-on reset or PWR soft reset clear) Bit Field...
Page 73: Power Status Register 1 (Pwr_Sts1)
Bit Field Name Description 0: No wakeup event occurred 1: Wakeup event received from WKUP pin Power Status Register 2 (PWR_STS1) Address offset: 0x10 Reset value: 0x0000 0003 (Power-on reset or PWR soft reset clear) Bit Field Name Description 31:3 Reserved Reserved, the reset value must be maintained.
Page 74 Bit Field Name Description 31:9 Reserved Reserved, the reset value must be maintained. CLRSTBY Clear STANDBY flag. This bit always reads as 0. 0: No effect. 1: Clear PWR_STS1.STBYF flag. Reserved Reserved, the reset value must be maintained. CLRWKUP2 Clear WKUP2 wakeup flag. This bit always reads as 0.
Page 75: Reset And Clock Control (Rcc)
4 Reset And Clock Control (RCC) Reset Control Unit Supports the following three types of reset: • Power Reset • System Reset • Low power domain Reset Power Reset A power reset occurs in the following circumstances: • Power-on reset (POR reset). •...
Page 76: Software Reset
Software reset ® A software reset can be generated by setting the SYSRESETREQ bit in Cortex -M4F Application Interrupt and ® Reset Control Register. Refer to Cortex -M4F technical reference manual for further information. Low-power management reset Low-power management reset can be generated by using the following methods: •...
Page 77 • HSI oscillator clock,16MHz; • HSE oscillator clock, 4~32MHz; • MSI oscillator clock: The frequency can be configured to 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz, the default is 4MHz; Automatically enable the clock after power-on reset, system reset or wake-up from STANDBY mode; Configurable clock source for low power mode; •...
Page 78: Clock Tree Diagram
Clock Tree Diagram Figure 4-2 Clock Tree FLASH_CLK Clock Tree to Flash programming TRNG 1M Legend: Prescaler TRNG_CLK 1M HSE = High-speed external clock signal /2/4/ /32 TRNG1MSEL HSI = High-speed internal clock signal ADC 1M MSI = Multi-speed internal clock signal Prescaler ADC_CLK 1M LSE = Low-speed external clock signal...
Page 79: Hsi Clock
• HSE user external clock To reduce distortion of the clock output and shorten the start-up stablize time, the crystal/ceramic resonator and load capacitor must be placed as close as possible to the oscillator pins of the chip. The load capacitance value must be adjusted according to the chosen oscillator.
Page 80: Msi Clock
reset, the factory calibration value is loaded into the RCC_CTRL.HSICAL[8:0] bits. If the user application is subject to voltage or temperature variations, this may affect the accuracy of the RC oscillator. The HSI frequency can be trimmed by using the RCC_CTRL.HSITRIM[4:0] bits. The RCC_CTRL.HSIRDF bit flag indicates if the HSI RC oscillator is stable.
Page 81: Lse Clock
Figure 4-4 PLL Clock Source Selection PLLHSIPRE PLLSRC PLLMULFCT x2,x3,...x16, x17...x32 PLLCLK PLLDIVCLKEN PLLHSEPRES If the PLL interrupt is enabled in the clock interrupt register, an interrupt request can be generated when the PLL is ready. If the USB interface needs to be used in the application, the PLL must be set to output 48MHz clocks to provide the 48MHz USBCLK clock.
Page 82: System Clock (Sysclk) Selection
bit is set by hardware. An interrupt can be generated if enabled in the Clock Interrupt Register (RCC_CLKINT). LSI Calibration The internal low-speed oscillator LSI can be calibrated to compensate for its frequency offset to obtain an RTC time base with acceptable accuracy, and an independent watchdog (IWDG) timeout (when these peripherals are clocked from the LSI).
Page 83: Lse Clock Security System (Lsecss)
MSI oscillator and the disabling of the external HSE oscillator. If HSE clock (divided or not) is selected as PLL input clock then upon HSE clock failure, the PLL will be turned off. LSE Clock Security System (LSECSS) The LSE clock security system is activated by enabling the RCC_LDCTRL.LSECLKSSEN bit. The RCC_LDCTRL.LSECLKSSEN bit can be cleared by a hardware reset or RTC software reset or after detection of an LSE fault.
Page 84: Rcc Registers
• • • • • The clock selection is controlled by RCC_CFG.MCO[2:0] bits. The MCO output clock frequency division selection is realized by configuring the RCC_CFG.MCOPRES[3:0] bits.  Note: MCO outputs LSE with a duty cycle of about of 50% RCC Registers The RCC registers are accessible through AHB bus.
Page 85: Clock Control Register (Rcc_Ctrl)
Offset Register RCC_APB1PCLKEN 01Ch Reserved Reset Value RCC_LDCTRL 020h Reserved Reserved Reset Value RCC_CTRLSTS MSITRIM[7:0] MSICAL[7:0] 024h Reset Value RCC_AHBPRST 028h Reserved Reserved Reset Value ADCHPRES RCC_CFG2 RNGCPRES[4:0] ADC1MPRES[4:0] ADCPLLPRES[4:0] [3:0] 02Ch Reserved Reset Value RCC_CFG3 TRNG1MPRES[4:0] 030h Reserved Reserved Reset Value RCC_RDCTRL 034h...
Page 86 Bit Field Name Description 31:26 Reserved Reserved, the reset value must be maintained. PLLRDF PLL clock ready flag Set by hardware once PLL is ready. 0: PLL is not ready 1: PLL is ready PLLEN PLL enable Set and cleared by software. When entering the stop2 mode, it is cleared by hardware. This bit cannot be cleared when PLL is used as the system clock.
Page 87: Clock Configuration Register (Rcc_Cfg)
Bit Field Name Description HSITRIM[4:0] Internal high-speed clock correction value Written by software. The values of these bits will be added to the HSICAL[8:0] bits in order to form the final value for calibrating the frequency of the internal HSI RC oscillator.
Page 88 Bit Field Name Description 1010: MCO clock divided by 6, duty cycle 50% 1011: MCO clock divided by 8, duty cycle 50% 1100: MCO clock divided by 10, duty cycle 50% 1101: MCO clock divided by 12, duty cycle 50% 1110: MCO clock divided by 14, duty cycle 50% 1111: MCO clock divided by 16, duty cycle 50% PLLMULFCT[4]...
Page 89 Bit Field Name Description 01000: PLL input clock × 10 01001: PLL input clock × 11 01010: PLL input clock × 12 01011: PLL input clock × 13 01100: PLL input clock × 14 01101: PLL input clock × 15 01110: PLL input clock ×...
Page 90: Clock Interrupt Register (Rcc_Clkint)
Bit Field Name Description 111: HCLK divided by 16 10:8 APB1PRES[2:0] APB low-speed (APB1) prescaler Set and cleared by software to configure the division factor of APB1 clock (PCLK1). Make sure that PCLK1 does not exceed 16MHz. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8...
Page 91 Bit Field Name Description 31:27 Reserved Reserved, the reset value must be maintained. LSESSICLR LSE Clock security system interrupt clear. This bit is set by software to clear the LSESSIF flag. 0: No effect 1: Clear LSESSIF flag LSESSIEN LSE Clock Security System (CSS) interrupt enable Set and cleared by software to enable/disable interrupt caused by LSE CSS detection.
Page 92 Bit Field Name Description Set by the software to clear the HSIRDIF flag. 0: Not used 1: Clear the HSIRDIF flag LSERDICLR LSE ready interrupt clear Set by the software to clear the LSERDIF flag. 0: Not used 1: Clear LSERDIF flag LSIRDICLR LSI ready interrupt clear Set by software to clear the LSIRDIF flag.
Page 93 Bit Field Name Description 0: Disable LSI ready interrupt 1: Enable LSI ready interrupt CLKSSIF Clock security system interrupt flag Set by hardware when a failure is detected in the external HSE oscillator. 0: No clock security system interrupt caused by HSE clock failure 1: Clock security system interrupt caused by HSE clock failure MSIRDIF MSI ready interrupt flag.
Page 94: Apb2 Peripheral Reset Register (Rcc_Apb2Prst)
APB2 Peripheral Reset Register (RCC_APB2PRST) Address offset: 0x0c Reset value: 0x0000 0000 Bit Field Name Description 31:20 Reserved Reserved, the reset value must be maintained. SPI2RST SPI2 reset Set and cleared by software. 0: Clear the reset 1: Reset SPI2 UART5RST UART5 reset Set and cleared by software.
Page 95: Apb1 Peripheral Reset Register (Rcc_Apb1Prst)
Bit Field Name Description 0: Clear the reset 1: Reset TIM1 timer 10:6 Reserved Reserved, the reset value must be maintained. IOPDRST GPIO port D reset. Set or cleared by software. 0: Clear the reset 1: Reset GPIO port D IOPCRST GPIO port C reset.
Page 96 Bit Field Name Description DACRST DAC interface reset. Set or cleared by software. 0: Clear the reset 1: Reset the DAC interface PWRRST Power interface reset Set and cleared by software. 0: Clear the reset 1: Reset the power interface 27:26 Reserved Reserved, the reset value must be maintained.
Page 97: Ahb Peripheral Clock Enable Register (Rcc_Ahbpclken)
Bit Field Name Description 0: Clear the reset 1: Reset window watchdog Reserved Reserved, the reset value must be maintained. TIM9RST TIM9 reset. Set or cleared by software. 0: clear the reset 1: Reset TIM9 Reserved Reserved, the reset value must be maintained. COMPRST COMP reset Set and cleared by software.
Page 98 Reset value: 0x0000 0014 Bit Field Name Description 31:13 Reserved Reserved, the reset value must be maintained. ADCEN ADC clock enable Set and cleared by software. 0: ADC clock disabled 1: ADC clock enabled SACEN SAC clock enable Set and cleared by software. 0: SAC clock disabled 1: SAC clock enabled...
Page 99: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Pclken)
Bit Field Name Description Reserved Reserved, the reset value must be maintained. DMAEN DMA clock enable Set and cleared by software. 0: DMA clock disabled 1: DMA clock enabled APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN) Address offset: 0x18 Reset value: 0x0000 0000 Bit Field Name Description...
Page 100 Bit Field Name Description software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled SPI1EN SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled TIM1EN TIM1 timer clock enable Set and cleared by software.
Page 101: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Pclken)
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN) Address offset: 0x1c Reset value: 0x0000 0100 USART3 USART2 OPAMPEN Reserved DACEN PWREN Reserved CANEN Reserved USBEN I2C2EN I2C1EN Reserved Reserved WWDG COMP Reserved Reserved TIM9EN Reserved COMPEN TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN FILTEN Bit Field Name...
Page 102 Bit Field Name Description 0: I2C2 clock disabled 1: I2C2 clock enabled I2C1EN I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled 20:19 Reserved Reserved, the reset value must be maintained. USART3EN USART3 clock enable Set and cleared by software.
Page 103: Low Power Domain Control Register (Rcc_Ldctrl)
Bit Field Name Description 0: TIM7 clock disabled 1: TIM7 clock enabled TIM6EN TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled TIM5EN TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled...
Page 104 Bit Field Name Description LDEMCRSTF Low power domain EMC reset flag. Set by hardware when a low-power domain EMC reset occurs, and cleared by software by writing the RCC_CTRLSTS.RMRSTF bit. 0: No low power domain EMC reset occurred 1: A low power domain EMC reset has occurred Reserved Reserved, the reset value must be maintained.
Page 105: Clock Control/Status Register (Rcc_Ctrlsts)
Bit Field Name Description 1: LSE oscillator bypassed LSERD External low-speed clock oscillator ready Set and cleared by hardware to indicate if the LSE oscillator is ready. After the LSEEN bit is cleared, LSERD goes low after 6 cycles of the LSE clock. 0: External low-speed oscillator not ready 1: External low-speed oscillator ready LSEEN...
Page 106 Bit Field Name Description 1: Independent watchdog reset occurred SFTRSTF Software reset flag Set by hardware when a software reset occurs. Cleared by software by writing to the RMRSTF bit. 0: No software reset occurred 1: Software reset occurred PORRSTF Power-on/power-down reset flag Set by hardware when a power-on/power-down reset occurs Cleared by software by writing to the RMRSTF bit.
Page 107: Ahb Peripheral Reset Register (Rcc_Ahbprst)
Bit Field Name Description 100: 1MHz 101: 2MHz 110: 4MHz (default) MSIRD The internal medium-speed clock is ready. Hardware will be set to 1 after MSI is stable. This bit takes 6 internal MSI oscillator clock cycles to clear after the MSIEN bit is cleared. 0: MSI not ready 1: MSI is ready MSIEN...
Page 108: Clock Configuration Register 2 (Rcc_Cfg2)
Bit Field Name Description 0: Clear the reset 1: Reset ADC SACRST SAC reset Set and cleared by software. 0: Clear the reset 1: Reset SAC Reserved Reserved, the reset value must be maintained. RNGCRST RNGC reset Set and cleared by software.
Page 109 Bit Field Name Description 23:18 Reserved Reserved, the reset value must be maintained. ADC1MSEL ADC 1M clock source selection. Set or cleared by software. 0: Select HSI oscillator clock as the input clock of ADC 1M 1: Select HSE oscillator clock as the input clock of ADC 1M 16:12 ADC1MPRES[4:0] ADC 1M clock prescaler...
Page 110: Clock Configuration Register 3 (Rcc_Cfg3)
Bit Field Name Description 0110: HCLK clock divided by 12 0111: HCLK clock divided by 16 1000: HCLK clock divided by 32 Others: HCLK clock divided by 32 Clock Configuration Register 3 (RCC_CFG3) Address offset: 0x30 Reset value: 0x0000 3800 Bit Field Name Description...
Page 111: Retention Domain Control Register (Rcc_Rdctrl)
Bit Field Name Description USBXTALESS USB external crystal oscillator selection mode 0: USB has external crystal oscillator mode 1: USB without external crystal oscillator mode UCDREN UCDR enable 0: UCDR bypass 1: UCDR enable Reserved Reserved, the reset value must be maintained. Retention Domain Control Register (RCC_RDCTRL) Address offset: 0x34 Reset value: 0x0000 0000...
Page 112: Pll And Hsi Configuration Register (Rcc_Pllhsipre)
Bit Field Name Description LPTIMEN LPTIMclock enable. Set or cleared by software. 0: Disable LPTIM clock 1: Enable LPTIM clock Reserved Reserved, the reset value must be maintained. LPUARTSEL LPUART clock source selection. Set or cleared by software. 00: Select APB as input clock 01: Select the system clock as the input clock 10: Select HSI (16MHz) as input clock 11: Select LSE as input clock...
Page 113: Sram Control/Status Register (Rcc_Sram_Ctrlsts)
Bit Field Name Description written only when PLL is disabled. 0: HSI clock not divided 1: HSI clock divided by 2 SRAM Control/Status Register (RCC_SRAM_CTRLSTS) Address offset: 0x44 Reset value: 0x0000 0000 Bit Field Name Description 31:6 Reserved Reserved, the reset value must be maintained. ERR2STS SRAM2 parity error status bit.
Page 114: Gpio And Afio
5 GPIO And AFIO Summary GPIO (General purpose input/output), and AFIO (Alternate-function input/output)are available for flexible pin configuration. The chip supports up to 64 GPIOs, which are divided into 4 groups (GPIOA/GPIOB/GPIOC/GPIOD). Each GPIO pin can be independently configured as an output, input or alternate peripheral function port. Except for the analog pins, other GPIO pins have high current capacity.
Page 115: I/O Function Description
Figure 5-1 Basic Structure Of I/O Port DDIOx Write Bit set/clear register P-MOS Output data DDIOx register Output Read / Write control Pull N-MOS Alternate function output From on-chip peripheral Push-pull, open-drain or disabled I/O Pin Pull diode down On / Off Read Input data register...
Page 116: Table 5-2 Input And Output Characteristics Of Different Configurations
PMODE[1:0] POTYPE PUPD[1:0] I/O Configuration Alternate function open-drain pull-up Alternate function open-drain pull-down Reserved Input floating pull-up Input pull-down Input Reserved Analog Reserved The input and output characteristics of I/O under different configurations are shown in the following table： Table 5-2 Input And Output Characteristics Of Different Configurations Alternate Feature GPIO Input...
Page 117: Figure 5-2 Input Floating/Pull-Up/Pull-Down Configuration
• Schmitt trigger input is activated • Whether the pull-up and pull-down resistors are connected depends on the configuration of the GPIOx_PUPD register • Output buffer is disabled • The data appearing on the I/O pin is sampled into the input data register •...
Page 118: Figure 5-3 Output Mode Configuration
• Read access to input data register for I/O status • The read access to the output data register gets the last written value Figure 5-3 Output Mode Configuration DDIOx P-MOS Write DDIOx Bit set/clear register Output data Output register control Pull N-MOS...
Page 119: Analog Mode
Figure 5-4 Alternate Function Configuration DDIOx Write Bit set/clear register P-MOS Output data DDIOx register Output Read / Write control Pull N-MOS From on-chip peripheral Alternate function output Push-pull or open-drain I/O Pin Pull diode down Read Input data register TTL Schmitt trigger Alternate function input To on-chip peripheral...
Page 120: Status After Reset
Figure 5-5 High Impedance Analog Mode Configuration Write Bit set/clear register Output data register Read / Write Analog From on-chip peripheral I/O Pin diode Read Input data register TTL Schmitt trigger Analog To on-chip peripheral Status After Reset During and after reset, the alternate function is not turned on, and the I/O port is configured to analog function mode (GPIOx_PMODE.PMODEx[1:0]=11b).
Page 121: External Interrupt/Wake-Up Line
operation of the data register (GPIOx_POD) can be realized, and one or more bits can be set/reset. The bit written with '1' is set or cleared accordingly, and the bit not written with '1' will not be changed. The software does not need to disable interrupts, and is completed in a single APB2 write operation.
Page 122: Table 5-3 Debug Port Image
mapped to the GPIO port, as shown in the following table. Alternate Function GPIO Port Remap JTMS/SWDIO PA13 JTCK/SWCLK PA14 JTDI PA15 JTDO NJTRST If you need to use its GPIO function during debugging, you can change the above remapping configuration by setting the multiplexed remapping and debugging I/O configuration registers (GPIOx_AFL or GPIOx_AFH).
Page 123: Table 5-5 Adc External Trigger Regular Conversion Alternate Function Remapping
Table 5-5 ADC External Trigger Regular Conversion Alternate Function Remapping Alternate Function ADC_ETRR = 0 ADC_ETRR = 1 ADC external trigger ADC external trigger regular conversion is connected to ADC external trigger regular conversion and rule conversion EXTI (0 - 15). TIM8_TRGO connection.
Page 124: Table 5-8 Tim3 Alternate Function Remapping
5.2.5.6.3 TIM3 Alternate Function Remapping Table 5-8 TIM3 Alternate Function Remapping Alternate Function Remap TIM3_ETR TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 5.2.5.6.4 TIM4 Alternate Function Remapping Table 5-9 TIM4 Alternate Function Remapping Alternate Function Remap TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_CH4 5.2.5.6.5 TIM5 alternate function remapping Table 5-10 TIM5 alternate function remapping Alternate function Remap...
Page 125: Table 5-12 Tim9 Alternate Function Remapping
Alternate Function Remap TIM8_CH2N TIM8_CH3N 5.2.5.6.7 TIM9 Alternate Function Remapping Table 5-12 TIM9 Alternate Function Remapping Alternate Function Remap TIM9_ETR TIM9_CH1 PB12 TIM9_CH2 PB13 TIM9_CH3 PB14 TIM9_CH4 PB15 LPTIM Alternate Function Remapping Table 5-13 LPTIM Alternate Function Remapping Alternate Function Remap LPTIM_IN1 LPTIM_IN2...
Page 126: Table 5-16 Usart2 Alternate Function Remapping
Alternate Function Remap USART1_CTS PA11 USART1_RTS PA12 USART1_RX PA10 USART1_CK 5.2.5.9.2 USART2 Alternate Function Remapping Table 5-16 USART2 Alternate Function Remapping Alternate Function Remap USART2_CTS PA15 USART2_RTS USART2_TX PD14 USART2_RX PD15 USART2_CK PA14 5.2.5.9.3 USART3 Alternate Function Remapping Table 5-17 USART3 Alternate Function Remapping Alternate Function Remap USART3_CTS...
Page 127: Table 5-18 Uart4 Alternate Function Remapping
UARTx Alternate Function Remapping 5.2.5.10.1 UART4 Alternate Function Remapping Table 5-18 UART4 Alternate Function Remapping Alternate Function Remap PB14 UART4_TX PC10 PD13 PB15 UART4_RX PC11 PD12 5.2.5.10.2 UART5 alternate function remapping Table 5-19 UART5 alternate function remapping Alternate function Remap UART5_TX PC12 UART5_RX...
Page 128: Table 5-21 I2C1 Alternate Function Remapping
Alternate Function Remap LPUART_CTS PB13 PB12 LPUART_RTS PB14 PB11 PC11 I2C Alternate Function Remapping 5.2.5.12.1 I2C1 Alternate Function Remapping Table 5-21 I2C1 Alternate Function Remapping Alternate Function Remap PA15 I2C1_SCL PD13 PA14 I2C1_SDA PD12 I2C1_SMBA 103 / 652...
Page 129: Table 5-22 I2C2 Alternate Function Remapping
5.2.5.12.2 I2C2 Alternate Function Remapping Table 5-22 I2C2 Alternate Function Remapping Alternate Function Remap I2C2_SCL PB10 PB13 PD15 PA10 I2C2_SDA PB11 PB14 PD14 I2C2_SMBA PB12 SPI/I2S Alternate Function Remapping 5.2.5.13.1 SPI1 Alternate Function Remapping Table 5-23 SPI1 Alternate Function Remapping Alternate Function Remap SPI1_I2S1_NSS_WS...
Page 130: Table 5-24 Spi2/I2S2 Alternate Function Remapping
5.2.5.13.2 SPI2/I2S2 Alternate Function Remapping Table 5-24 SPI2/I2S2 Alternate Function Remapping Alternate Function Remap PA13 PA15 SPI2_I2S2_NSS_WS PB12 PA10 SPI2_I2S2_SCLK_CK PB13 PD12 PA11 SPI2_I2S2_MISO_MCK PB14 PA12 SPI2_I2S2_MOSI_SD PB15 COMP Alternate Function Remapping 5.2.5.14.1 COMP1 Alternate FunctionRemapping Table 5-25 COMP1 Alternate Function Remapping Alternate Function Remap PA11...
Page 131: Table 5-27 Eventout Alternate Function Remapping
EVENTOUT Alternate Function Remapping Table 5-27 EVENTOUT Alternate Function Remapping Alternate Function Remap PA0~PA13 PA15 PB0~PB15 EVENTOUT PC0~PC7 PC9~PC13 PD12~PD13 RTC Alternate Function Remapping Table 5-28 RTC Alternate Function Remapping Alternate Function Remap RTC_REFIN PB15 LCD Alternate Function Remapping Table 5-29 LCD Alternate Function Remapping Alternate Function Remap COM0...
Page 132: I/O Configuration Of Peripherals
Alternate Function Remap PD4~PD6 AF10 AF10 SEG31 AF10 SEG32~SEG33 PD0~PD1 AF10 SEG34 AF10 SEG35 PC13 AF10 SEG36~SEG39 PD8~PD11 AF10 PD4~PD6 AF10 SEG40~SEG42 PC10~PC12 AF10 AF10 SEG43 AF10 1. Due to the difference of the chip version, the corresponding pins of COM4~COM7, SEG28~SEG31, SEG40~SEG43 are different.
Page 133: Table 5-33 Tim2/3/4/5/9
TIM1/TIM8 Pin Configuration PAD Configuration Mode TIM1/8_CHxN Complementary output channel x Push-pull alternate output TIM1/8_BKIN Brake input Input floating TIM1/8_ETR External trigger clock input Input floating Table 5-33 TIM2/3/4/5/9 TIM2/3/4/5/9 Pin Configuration PAD Configuration Mode Input capture channel x Input floating TIM2/3/4/5/9_CHx Output channel x Push-pull alternate output...
Page 134: Table 5-39 I2C
LPUSART Pin Configuration GPIO Configuration LPUART _CTS Hardware flow control Input floating or input pull-up LPUART _RTS Hardware flow control Push-pull alternate output Table 5-39 I2C I2C Pin Configuration GPIO Configuration I2Cx_SCL I2C clock Open-drain alternate output I2Cx_SDA I2C data Open-drain alternate output I2Cx_SMBA SMBA data...
Page 135: Gpio Locking Mechanism
Alternate Function GPIO Configuration Input floating or input pull-up or input EXTI Input Line External interrupt input pull-down GPIO Locking Mechanism The locking mechanism is used to freeze the I/O configuration to prevent accidental changes. When a lock (LOCK) procedure is performed on a port bit, the configuration of the port cannot be changed until the next reset, refer to the port configuration lock register GPIOx_PLOCK.
Page 136 Offset Register GPIOx_POTYPE 004h Reserved Reset Value GPIOx_SR 008h Reserved Reset Value GPIOx_PUPD 00Ch Reset Value GPIOx_PID 010h Reserved Reset Value GPIOx_POD 014h Reserved Reset Value GPIOx_PBSC 018h Reset Value GPIOx_PLOCK 01Ch Reserved Reset Value GPIOx_AFL AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0]...
Page 137: Gpio Mode Description Register (Gpiox_Pmode)
GPIO Mode Description Register (GPIOx_PMODE) Address: 0x00 Reset value: 0xABFF FFFF（x=A）；0xFFFF FEBF（x=B）；0xFFFF FFFF（x=C）；0xFFFF FFFC（x=D） Bit Field Name Description 31:30 PMODEy[1:0] Mode bits for port x (y = 0…15) 29:28 00: Input mode 27:26 01: General output mode 25:24 10: Alternate function mode 23:22...
Page 138: Gpio Port Slew Rate Configuration Register (Gpiox_Sr)
Bit Field Name Description 15:0 POTy Output mode bits for port x (y = 0…15) 0: Output push-pull mode (state after reset) 1: Output open-drain mode GPIO Port Slew Rate Configuration Register (GPIOx_SR) Address: 0x08 Reset value: 0x0000 FFFF（x= A,B,C,D） Bit Field Name Description...
Page 139: Gpio Input Data Register (Gpiox_Pid)
Bit Field Name Description 15:14 13:12 11:10 GPIO Input Data Register (GPIOx_PID) Address: 0x10 Reset value: 0x0000 0000（x=A,B,C,D） Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 PIDy Port input data (y = 0…15) These bits are read-only and can only be read in the form of 16-bit words, and the read value is the state of the corresponding I/O port.
Page 140: Gpio Bit Set/Clear Register (Gpiox_Pbsc)
GPIO Bit Set/Clear Register (GPIOx_PBSC) Address: 0x18 Reset value: 0x0000 0000（x=A,B,C,D） Bit Field Name Description 31:16 PBCy Clear bit y of port GPIOx (y = 0…15) These bits can only be written and operated as words (16 bits). 0: Does not affect the corresponding PODy bit 1: Clear the corresponding PODy bit to 0 Note: if the corresponding bits of PBSy and PBCy are set at the same time, the PBSy bit works.
Page 141: Gpio Alternate Function Low Register (Gpiox_Afl)
Bit Field Name Description The last reading can be omitted, but it can be used to confirm that the lock key has been activated. Note: the value of PLOCK[15:0] cannot be changed when the writing sequence of lock key is operated. Any error in the operation key writing sequence will not activate the key.
Page 142: Gpio Alternate Function High Register (Gpiox_Afh)
GPIO Alternate Function High Register (GPIOx_AFH) Address: 0x24 Reset value: 0x000F FFFF（x=A）；0xFFFF FFFF（x=B,C,D） Bit Field Name Description 31:28 AFSELy[3:0] Alternate function configuration bits y for port GPIOx（y = 8…15） 27:24 0000：AF0 23:20 0001：AF1 19:16 0010：AF2 15:12 0011：AF3 11:8 0100：AF4 0101：AF5 0110：AF6 0111：AF7...
Page 143: Gpio Driver Strength Configuration Register (Gpiox_Ds)
Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 PBCy Clear bit y of port GPIOx (y = 0...15) These bits can only be written and operated as words (16 bits). 0: Does not affect the corresponding PODy bit 1: Clear the corresponding PODy bit to 0 GPIO Driver Strength Configuration Register (GPIOx_DS) Address: 0x2C...
Page 144: Afio Mapping Configuration Control Register (Afio_Rmp_Cfg)
Table 5-45 AFIO Register Overview Offset Register AFIO_RMP_CFG 000h Reserved Reset Value AFIO_EXTI_CFG1 004h Reserved Reset Value AFIO_EXTI_CFG2 008h Reserved Reset Value AFIO_EXTI_CFG3 00Ch Reserved Reset Value AFIO_EXTI_CFG4 010h Reserved Reset Value AFIO Mapping Configuration Control Register (AFIO_RMP_CFG) Address: 0x00 Reset value: 0x0000 0000 Bit Field Name...
Page 145: Afio External Interrupt Configuration Register 1(Afio_Exti_Cfg1)
Bit Field Name Description 1: NSS is high when idle ADC_ETRI ADC injection conversion external trigger remapping This bit can be set to '1' or '0' by software. It controls the trigger input connected to the external trigger for ADC injection conversion. 0: ADC injection conversion external trigger is connected to EXTI (0-15) 1: ADC injection conversion external trigger is connected to TIM8_CH4.
Page 146: Afio External Interrupt Configuration Register 2(Afio_Exti_Cfg2)
Bit Field Name Description EXTI0[1:0] 00：PA0 pin 01：PB0 pin 10：PC0 pin 11：PD0 pin AFIO External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2) Address: 0x08 Reset value: 0x0000 0000 Bit Field Name Description 31:14 Reserved Reserved, the reset value must be maintained 13:12 EXTI7[1:0] 00：PA7 pin 01：PB7 pin...
Page 147: Afio External Interrupt Configuration Register 4(Afio_Exti_Cfg4)
Bit field Name Description 31:14 Reserved Reserved, the reset value must be maintained 13:12 EXTI11[1:0] 00：PA11 pin 01：PB11 pin 10：PC11 pin 11：PD11 pin 11:10 Reserved Reserved, the reset value must be maintained EXTI10[1:0] 00：PA10 pin 01：PB10 pin 10：PC10 pin 11：PD10 pin Reserved Reserved, the reset value must be maintained EXTI9[1:0]...
Page 148 Bit Field Name Description 01：PB15 pin 10：PC15 pin 11：PD15 pin 11:10 Reserved Reserved, the reset value must be maintained EXTI14[1:0] 00：PA14 pin 01：PB14 pin 10：PC14 pin 11：PD14 pin Reserved Reserved, the reset value must be maintained EXTI13[1:0] 00：PA13 pin 01：PB13 pin 10：PC13 pin 11：PD13 pin Reserved...
Page 149: Interrupts And Events
6 Interrupts And Events Nested Vector Interrupt Register Features • 66 maskable interrupt channels (excluding 16 Cortex ® -M4F interrupt lines). • 16 programmable priority levels (using 4-bit interrupt priority); • Low-latency exception and interrupt handling; • Power management control; •...
Page 150 Priority Position Priority Name Description Address type System services that can be Settable PendSV 0x0000_0038 suspended Settable SysTick System tick timer 0x0000_003C Settable WWDG Window timer interrupt 0x0000_0040 Power supply voltage detection Settable (PVD) interrupt connected to EXTI 0x0000_0044 line 16 RTC timestamp interrupt connected Settable RTC_TAMPER_STAMP...
Page 151 Priority Position Priority Name Description Address type Settable TIM4 TIM4 global interrupt 0x0000_00B8 Settable I2C1_EV I2C1 event interrupt 0x0000_00BC Settable I2C1_ER I2C1 error interrupt 0x0000_00C0 Settable I2C2_EV I2C2 event interrupt 0x0000_00C4 Settable I2C2_ER I2C2 error interrupt 0x0000_00C8 Settable SPI1 SPI1 global interrupt 0x0000_00CC Settable SPI2...
Page 152: Extended Interrupt/Event Controller (Exti)
Priority Position Priority Name Description Address type Settable RAMC_PERR RAM verification error interrupt 0x0000_0148 Settable TIM9 TIM9 global interrupt 0x0000_014C Settable UCDR UCDR error interrupt 0x0000_0150 Extended Interrupt/Event Controller (EXTI) Introduction The extended interrupt/event controller contains 27 edge detection circuits that generate interrupt/event triggers. Each input line can be independently configured with pulse or pending input types, and 3 trigger event types including rising edge, falling edge or double edge, which can also be independently shielded.
Page 153: Functional Description
Figure 6-1 External Interrupt/Event Controller Block Diagram AMBA APB BUS peripheral interface PCLK2 Software Interrupt Falling edge Rising edge Request to interrupt triggers triggers the masking suspend configuration configuration event register register register register register Connect the NVIC interrupt controller Pulse Input Edge detection circuit...
Page 154: Exti Line Image
• Hardware interrupt configuration, select and configure 27 lines as interrupt sources as required: • Configure the mask bit (EXTI_IMASK) for 27 interrupt lines. • Configure the Trigger Selection bits of the selected interrupt line (EXTI_RT_CFG and EXTI_FT_CFG); • Configure the enable and mask bits of the NVIC interrupt channel corresponding to the external interrupt controller so that the requests in the 27 interrupt lines can be correctly responded to.
Page 155: Exti Registers
• EXTI line 18 is connected to the RTC alarm • EXTI line 19 is connected to the RTC timestamp event • EXTI line 20 is connected to the RTC Wake up event • EXTI line 21 is connected to the COMP1 output •...
Page 156: Exti Registers Overview
EXTI Registers Overview Table 6-2 EXTI Register Overview Offset Register EXTI_IMASK IMASK[24:0] 000h Reserved Reset Value EXTI_EMASK EMASK[24:0] 004h Reserved Reset Value EXTI_RT_CFG RT_CFG[24:0] 008h Reserved Reset Value EXTI_FT_CFG FT_CFG[24:0] 00Ch Reserved Reset Value EXTI_SWIE SWIE[24:0] 010h Reserved Reset Value EXTI_PEND 014h Reserved...
Page 157: Exti Event Mask Register (Exti_Emask)
Bit Field Name Description IMASK26 Interrupt mask on line 26 0: Masking the interrupt requests from line 26. 1: Not masking the interrupt requests from line 26. Reserved Reserved,the reset value must be maintained. 24:0 IMASKx Interrupt mask on line x(x is 0,1,2,3…23,24) 0: Masking the interrupt requests from line x.
Page 158: Exti Falling Edge Trigger Configuration Register (Exti_Ft_Cfg)
Bit Field Name Description 0: Disable rising edge triggering (interrupts and events) on input line 26. 1: Enable rising edge triggering (interrupts and events) on input line 26. Reserved Reserved,the reset value must be maintained. 24:0 RT_CFGx The rising edge on line x triggers the configuration bit.(x is 0,1,2,3…23,24) 0: Disable rising edge triggering (interrupts and events) on input line x 1: Enable rising edge triggering (interrupts and events) on input line x EXTI Falling Edge Trigger Configuration Register (EXTI_FT_CFG)
Page 159: Exti Pending Register (Exti_Pend)
Bit Field Name Description this interrupt is allowed in EXTI_IMASK and EXTI_EMASK, an interrupt will be generated. Note: This bit can be cleared to '0' by writing '1' to clear the corresponding bit of EXTI_PEND. Reserved Reserved,the reset value must be maintained. 24:0 SWIEx Software interrupt on line x.
Page 160 Reset value: 0x0000 0000 Bit Field Name Description 31:4 Reserved Reserved,The reset value must be maintained. TSSEL[3:0] Select the external interrupt input as the trigger source for the timestamp event 0000: Select EXTI0 as the trigger source of the timestamp event; 0001: Select EXTI1 as the trigger source of the timestamp event.
Page 161: Dma Controller
7 DMA Controller Introduction The DMA controller can access totally 5 AHB slaves: Flash, SRAM, ADC, ABP1 and APB2. DMA Controller is controlled by CPU to perform fast data transfer from source to destination. After configuration, data can be transferred without CPU intervention.
Page 162: Block Diagram
Block Diagram Figure 7-1 DMA Block Diagram Flash Flash Interface controller Cortex-M4F SRAM Bridge 1 Bridge 2 USART1 I2C1 UART4 I2C2 UART5 USART2 SPI1 USART3 SPI2 Arbiter LPUART DMA requests TIM1 AHB slave TIM2 TIM8 DMA requests device TIM3 TIM4 TIM5 TIM6 TIM7...
Page 163: Channel Priority And Arbitration
Each DMA data transfer consists of three operations: • Data access: determine the source address (DMA_PADDRx or DMA_MADDRx) according to the transfer direction and read data from the source address. • Data storage: determine the destination address (DMA_PADDRx or DMA_MADDRx) according to the transfer direction and store the read data into the destination address space.
Page 164: Table 7-1 Programmable Data Width And Endian Operation (When Pinc = Minc = 1)
Table 7-1 Programmable Data Width and Endian Operation (when PINC = MINC = 1) Destina- Number Source tion Source: Transfer operations Destination: width width transfer Address / data (R: Read, W: Write) Address / data (bit) (bit) (bit) 0x0 / B0 1: R B0 [7:0] @0x0, W B0 [7:0] @0x0 0x0 / B0 0x1 / B1...
Page 165: Peripheral/Memory Address Incrementation
DMA always provide full 32-bits data to HWDATA[31:0] no matter what destination size it is (HSIZE still follows destination size setting for device supports byte/half-word operation). The HWDATA[31:0] follows the following rules : • When source size is smaller than destination size, DMA pads the MSB with 0 until their sizes match and duplicates it to be 32 bits.
Page 166: Flow Control
If necessary, configure circular mode. If it is memory to memory, configure MEM2MEM mode (Note: to configure DMA to work in M2M mode, user needs to set corresponding channel select value to reserved value, e.g., 63). Repeat step 1~8 on channel 1~8 and finally. Enable corresponding channel.
Page 167: Circular Mode
Circular Mode The circular mode is used to process circular buffers and continuous data transmission (such as ADC scan mode). The DMA_CHCFGx.CIRC is used to enable this function. When the circular mode is activated, if the number of data to be transferred becomes 0, it will automatically be restored to the initial value when configuring the channel, and the DMA operation will continue.
Page 168: Table 7-4 Dma Request Mapping
can be used to select which DMA request is mapped to which DMA channel. The table blow show the mapping scheme of peripherals’ DMA request to DMA controller’s DMA channels. Table 7-4 DMA Request Mapping DMA Channel Select Peripheral DMA Request Sel = 0 ADC_DMA Sel = 1...
Page 169: Dma Registers
DMA Channel Select Peripheral DMA Request Sel = 36 TIM3_CH4 Sel = 37 TIM3_UP Sel = 38 TIM3_TRIG Sel = 39 TIM4_CH1 Sel = 40 TIM4_CH2 Sel = 41 TIM4_CH3 Sel = 42 TIM4_UP Sel = 43 TIM5_CH1 Sel = 44 TIM5_CH2 Sel = 45 TIM5_CH3...
Page 170 Offset Register Reset Value DMA_TXNUM1 NDTX[15:0] 00Ch Reserved Reset Value DMA_PADDR1 ADDR[31:0] 010h Reset Value DMA_MADDR1 ADDR[31:0] 014h Reset Value DMA_CHSEL1 CH_SEL[5:0] 018h Reserved Reset Value DMA_CHCFG2 01Ch Reserved Reset Value DMA_TXNUM2 NDTX[15:0] 020h Reserved Reset Value DMA_PADDR2 ADDR[31:0] 024h Reset Value DMA_MADDR2 ADDR[31:0]...
Page 171: Dma Interrupt Status Register (Dma_Intsts)
Offset Register Reset Value DMA_TXNUM7 NDTX[15:0] 084h Reserved Reset Value DMA_PADDR7 ADDR[31:0] 088h Reset Value DMA_MADDR7 ADDR[31:0] 08Ch Reset Value DMA_CHSEL7 CH_SEL[5:0] 090h Reserved Reset Value DMA_CHCFG8 094h Reserved Reset Value DMA_TXNUM8 NDTX[15:0] 098h Reserved Reset Value DMA_PADDR8 ADDR[31:0] 09Ch Reset Value DMA_MADDR8 ADDR[31:0]...
Page 172: Dma Interrupt Flag Clear Register (Dma_Intclr)
Bit Field Name Description cleared by software by writing ‘1’ to DMA_INTCLR.CGLBFx bit. 0: No transfer error, half transfer or transfer done event happen on channel x. 1: One of transfer error, half transfer or transfer done event happen on channel x. DMA Interrupt Flag Clear Register (DMA_INTCLR) Address offset: 0x04 Reset value: 0x0000 0000...
Page 173 Bit Field Name Description 31:15 Reserved Reserved, the reset value must be maintained. MEM2MEM Memory to memory mode. Software can configure this channel to memory to memory transfer when it is not yet enabled. 0: Channel transfer between memory and peripheral. 1: Channel set to memory to memory transfer.
Page 174: Dma Channel X Transfer Number Register (Dma_Txnumx)
Bit Field Name Description 1: Channel configure as circular mode. Data transfer direction Software can set/clear this bit. 0: Data transfer from Peripheral to Memory 1: Data transfer from Memory to Peripheral. ERRIE Transfer error interrupt enable. Software can enable/disable transfer error interrupt. 0: Disable transfer error interrupt of channel x.
Page 175: Dma Channel X Peripheral Address Register (Dma_Paddrx)
Bit Field Name Description Otherwise it will keep at zero and reset channel enable. DMA Channel x Peripheral Address Register (DMA_PADDRx) Note：The x is channel number, x = 1…8 Address offset: 0x10+20 * (x–1) Reset value: 0x0000 0000 This register can only be written if the channel is disabled (DMA_CHCFGx.CHEN = 0). Bit Field Name Description...
Page 176: Dma Channel X Channel Request Select Register (Dma_Chselx)
Bit Field Name Description DMA_CHCFGx.MSIZE equal to 10 DMA will ignore bit [1:0] of MADDR. DMA Channel x Channel Request Select Register (DMA_CHSELx) Note：The x is channel number, x = 1…8 Address offset: 0x18+20 * (x–1) Reset value: 0x0000 0000 Bit Field Name Description...
Page 177 Bit Field Name Description 0x18：TIM1_CH3 0x19：TIM1_CH4 0x1A：TIM1_COM 0x1B：TIM1_UP 0x1C：TIM1_TRIG 0x1D：TIM2_CH1 0x1E：TIM2_CH2 0x1F：TIM2_CH3 0x20：TIM2_CH4 0x21：TIM2_UP 0x22：TIM3_CH1 0x23：TIM3_CH3 0x24：TIM3_CH4 0x25：TIM3_UP 0x26：TIM3_TRIG 0x27：TIM4_CH1 0x28：TIM4_CH2 0x29：TIM4_CH3 0x2A：TIM4_UP 0x2B：TIM5_CH1 0x2C：TIM5_CH2 0x2D：TIM5_CH3 0x2E：TIM5_CH4 0x2F：TIM5_UP 0x30：TIM5_TRIG 0x31：TIM6 0x32：TIM7 0x33：TIM8_CH1 0x34：TIM8_CH2 0x35：TIM8_CH3 0x36：TIM8_CH4 0x37：TIM8_COM 0x38：TIM8_UP 0x39：TIM8_TRIG 0x3A：TIM9_CH1 0x3B：TIM9_TRIG 0x3C：TIM9_CH3 0x3D：TIM9_CH4 0x3E：TIM9_UP...
Page 178: Crc Calculation Unit
8 CRC Calculation Unit CRC Introduction This module integrates the functions of CRC32 and CRC16, and the cyclic redundancy check (CRC) calculation unit obtains any CRC calculation result according to a fixed generator polynomial. In other applications, CRC technology is mainly used to verify the correctness and integrity of data transmission or data storage. EN/IEC 60335-1 provides a method to verify the integrity of flash memory.
Page 179: Crc Function Description
Figure 8-1 CRC Calculation Unit Block Diagram CRC32 CRC16 Ctrl&Data Regs AHBInf CRC Function Description CRC32 CRC unit contains one 32-bit data register: • Writing this register to input CRC data. • Reading this register to get the calculated CRC result. Every writing operation to this data register triggers the calculation of this new data with the previous calculation result (CRC calculation is performed on the whole 32-bit word rather than byte by byte).
Page 180: Crc Registers
CRC Registers CRC Register Overview The following table lists the registers and reset values of CRC. Table 8-1 CRC Register Overview Offset Register CRC32DAT CRC32DAT[31:0] 000h Reset Value CRC32IDAT CRC32IDAT[7:0] 004h Reserved Reset Value CRC32CTRL 008h Reserved Reset Value CRC16CTRL 00Ch Reserved Reset Value...
Page 181: Crc32 Control Register (Crc_Crc32Ctrl)
Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. CRC32IDAT[7:0] Independent 8-bit data register. General 8 bits data register. It is for temporary stored 1-byte data. CRC_ CRC32CTRL.RESET reset signal will not impact this register. Note: This register is not a part of CRC calculation and can be used to store any data. CRC32 Control Register (CRC_CRC32CTRL) Address offset: 0x08 Reset value: 0x0000 0000...
Page 182: Crc16 Input Data Register (Crc_Crc16Dat)
Bit Field Name Description 31:3 Reserved Reserved, the reset value must be maintained. Clear CRC16 results. 0: Not clear. 1: Clear to default value 0x0000. Set this bit to 1 will only maintain 1 clock cycle, hardware will clear automatically. (Software read always 0). ENDHL Data to be verified start to calculate from MSB or LSB(configured endian).
Page 183: Lrc Result Register (Crc_Lrc)
Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 CRC16D[15:0] 16-bit value of cyclic redundancy result data. Every time the software writes the CRC16DAT register, the 16-bit calculated data from CRC16 is updated in this register. Note: 8-bits, 16-bits and 32-bits operations are supported (8-bit operations must be performed twice in a row to ensure that 16-bit initial values are configured properly) LRC Result Register (CRC_LRC)
Page 184: Cryptographic Algorithm Hardware Acceleration Engine (Sac)
Support 128bit/192bit/ 256bit key length − Support CBC, ECB, CTR mode • Support SHA hash algorithm − Support SHA1/SHA224/SHA256 • Support MD5 digest algorithm Note: For the performance and use of the cryptographic algorithm, please contact Nsing Technologies sales Representatives 159 / 652...
Page 185: Advanced-Control Timers (Tim1 And Tim8)
10 Advanced-control Timers (TIM1 and TIM8) TIM1 and TIM8 Introduction The advanced control timers (TIM1 and TIM8) are mainly used in the following scenarios: counting the input signal, measuring the pulse width of the input signals and generating the output waveforms, etc. Advanced control timers have complementary output functions dead-time insertion and break functions.
Page 186: Tim1 And Tim8 Function Description
Figure 10-1 Block Diagram Of TIM1 And TIM8 Polarity TIMx_BKIN selection Clock failure event From clock controller CSS(Clock Security System) PVD abnormal (Power supply voltage detection) LOOKUP(Core Hardfault) Comparator polarity CK_TIM18 from RCC Internal clock(CK_INT) To another timer, ADC, Polarity selection ETRF TRGO Edge detector...
Page 187: Prescaler Description
counting one clock cycle after the TIMx_CTRL1.CNTEN bit is set. Prescaler description The TIMx_PSC register consists of a 16-bit counter that can be used to divide the counter clock frequency by any factor between 1 and 65536. It can be changed on the fly as this register is buffered. The new prescaler value is only taken into account at the next update event.
Page 188: Figure 10-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
• The prescaler shadow register is reloaded with the preload value(TIMx_PSC). To avoid updating the shadow registers when new values are written to the preload registers, you can disable the update event by setting TIMx_CTRL1.UPDIS=1. When an update event is generated, the counter will still be cleared and the prescaler counter will also be set to 0 (but the prescaler value will remain unchanged).
Page 189: Figure 10-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 10-4 Timing Diagram Of The Up-Counting, Update Event When ARPEN=0/1 ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 190: Down-Counting Mode
Down-counting mode In down-counting mode, the counter will decrement from the value of the register TIMx_AR to 0, then restart from the auto-reload value and generate a counter underflow event. The process of configuring update events and updating registers in down-counting mode is the same as in up-counting mode, see Section 10.3.2.1.
Page 191: Figure 10-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N
Alternatively, an update event can also be generated by setting the TIMx_EVTGEN. UDGN bit (either by software or using a slave mode controller). In this case, the counter restarts from 0, and the prescaler counter also restarts from Note: if an update is generated due to a counter overflow, the auto-reload update before reloading the counter. Figure 10-6 Timing Diagram of Center-aligned with Internal Clock Divided Factor 2/N Internal clock CK_PSC...
Page 192: Figure 10-7 A Center-Aligned Sequence Diagram That Includes Counter Overflows And Underflows (Arpen = 1)
Figure 10-7 A Center-Aligned Sequence Diagram That Includes Counter Overflows And Underflows (ARPEN = 1) Counter underflow CNTEN CK_PSC Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Write a new value in TIMx_AR...
Page 193: Figure 10-8 Repeat Count Sequence Diagram In Down-Counting Mode
underflow, where N is the value in the TIMx_REPCNT. The repetition counter is decremented: • In the up-counting mode, each time the counter reaches the maximum value, an overflow occurs. • In down-counting mode, each time the counter decrements to the minimum value, an underflow occurs. •...
Page 194: Figure 10-9 Repeat Count Sequence Diagram In Up-Counting Mode
Figure 10-9 Repeat Count Sequence Diagram in Up-Counting Mode CK_PSC CNTEN Timer clock = CK_CNT 01 ... 35 00 01 ... 35 36 00 01 ... 35 00 01 ... 35 36 00 01 ... 35 36 CNT_REG 36 00 00 01 Underflow Overflow...
Page 195: Clock Selection
Clock Selection • The internal clock of Advanced-control timers ：CK_INT • Two kinds of external clock mode : − external input pin − external trigger input ETR • Internal trigger input (ITRx): one timer is used as a prescaler for another timer. Internal clock source (CK_INT) When the TIMx_SMCTRL.SMSEL is equal to “000”, the slave mode controller is disabled.
Page 196: Figure 10-12 Ti2 External Clock Connection Example
External clock source mode 1 Figure 10-12 TI2 External Clock Connection Example Filter (TIMx_CCMOD1.ICF[3:0]) Edge Detector TIMx_SMCTRL. CK_INT rising TSEL[2:0] Internal clock mode Polarity Selection （ TIMx_CCEN.CC2P ） ITRx TRGI rising TI1_ED External clock mode 1 TI1FP1 TI2FP2 CK_PSC ETRF ETRF rising External clock mode 2 TI2F rising or falling...
Page 197: Figure 10-13 Control Circuit In External Clock Mode 1
Figure 10-13 Control Circuit in External Clock Mode 1 CNTEN Timer clock = CK_CNT=CK_PSC Counter register TITF Write TITF=0 External clock source mode 2 This mode is selected by TIMx_SMCTRL .EXCEN equal to 1. The counter can count on every rising or falling edge of the external trigger input ETR.
Page 198: Capture/Compare Channels
• External clock mode 2 is selected by setting TIMx_SMCTRL .EXCEN equal to ‘1’ • Turn on the counter by setting TIMx_CTRL1. CNTEN equal to ‘1’ The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to the counter is due to a resynchronization circuit on the ETRP signal.
Page 199: Figure 10-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
Figure 10-16 Capture/Compare Channel (example: channel 1 input stage) From slave mode controller TI2FP1 Divider /1,/2,/4,/8 TI2F_Rising From channel 2 IC1PSC TI1FP1 TI2F_Falling TIMx_CCMOD1. Polarity Selection IC1PSC[1:0] TIMx_CCMOD1.CC1SEL[3:0] TIMx_CCEN.CC2P TIMx_CCEN.CC1EN Filter Down counter TIMx_CCMOD1.IC1F[ Edge Detector 3:0] TI1F_Rising TI1F To the slave TI1F_Falling mode controller Polarity Selection...
Page 200: Figure 10-17 Capture/Compare Channel 1 Main Circuit
Figure 10-17 Capture/Compare Channel 1 Main Circuit CC1SEL[1] CC1SEL[0] Input IC1PSC CC1EN mode Read CCDAT1H TIM1_EVTGEN.CC1GN Read CCDAT1L Read in APB Bus progress MCU Peripheral interface 16 bit High 8-bits Capture/ Capture/ transfer compare compare Counter preload register shadow register Low 8-bits Output Comparator...
Page 201: Input Capture Mode
Figure 10-18 Output Part Of Channelx (x= 1,2,3, take channel 1 as example) To the master mode controller Output enable Output enable circuit circuit Polarity Seletion TIM1_CCEN.CC1NEN ETRF Ocref_clr_int TIM1_CCEN. TIM1_CCEN.CC1EN TIM1_CCEN.CC1NEN CC1P TIM1_CCEN.CC1EN TIM1_BKDT.MOEN TIM1_BKDT.MOEN CNT=CCR1 TIM1_BKDT.OSSI TIM1_BKDT.OSSI OC1REFC CNT>CCR1 TIM1_BKDT.OSSR TIM1_BKDT.OSSR...
Page 202: Pwm Input Mode
The TIMx_STS. CCxITF bit is set by hardware when a capture event occurs and is cleared by software or by reading the TIMx_CCDATx register. The overcapture flag TIMx_STS.CCxOCF is set equal to 1 when the counter value is captured in the TIMx_CCDATx register and TIMx_STS.CC1ITF is already pulled high.
Page 203: Forced Output Mode
• Configure TIMx_CCEN.CC2P equal to 1 to select the valid polarity of filtered timer input 2(TI1FP2), active on the falling edge. • Configure TIMx_SMCTRL.TSEL=101 to select filtered timer input 1 (TI1FP1) as valid trigger input. • Configure TIMx_SMCTRL.SMSEL=100 to configure the slave mode controller to reset mode. •...
Page 204: Output Compare Mode
Output Compare Mode User can use this mode to control the output waveform, or to indicate that a period of time has elapsed. When the capture/compare register and the counter have the same value, the output compare function’s operations are as follow: •...
Page 205: Pwm Mode
Figure 10-21 Output Compare Mode, Toggle on OC1 TIM1_CNT 0069 006A 006B 8800 8801 TIM1_CCDAT1 006A 8801 Write 8801h in CCDAT1 register OC1REF=OC1 Match detected on CCDAT1 Interrupt generated if enabled PWM Mode Pulse width modulation mode is used to generate a signal with a frequency determined by the value of the TIMx_AR register and a duty cycle determined by the value of the TIMx_CCDATx register.
Page 206: Figure 10-22 Center-Aligned Pwm Waveform (Ar=8)
Examples of center-aligned PWM waveforms is as follow, and the setting of the waveform are: TIMx_AR=8, PWM mode 1, the compare flag is set when the counter counts down corresponding to TIMx_CTRL1. CAMSEL=01. Figure 10-22 Center-aligned PWM Waveform (AR=8) Counter register OCXREF CCDATx=0 CAMSEL=01...
Page 207: Figure 10-23 Edge-Aligned Pwm Waveform (Apr=8)
not writing the counter while it is running. PWM edge-aligned mode There are two kinds of configuration in edge-aligned mode, up-counting and down-counting. • Up-counting User can set TIMx_CTRL1.DIR=0 to make counter counts up. Example for PWM mode1. When TIMx_CNT < TIMx_CCDATx, the reference PWM signal OCxREF is high. Otherwise it will be low. If the compare value in TIMx_CCDATx is greater than the auto-reload value, the OCxREF will remains 1.
Page 208: One-Pulse Mode
(n+1)th PWM cycle is 0. At the moment when the counter is 0 in the (n+1)th PWM cycle, although the value of the counter = CCDATx shadow register = 0 and OCxREF = '0', no compare event will be generated. One-pulse Mode In the one-pulse mode (ONEPM), a trigger signal is received, and a pulse t with a controllable pulse width is...
Page 209: Clearing The Ocxref Signal On An External Event
5. Configure TIMx_CTRL1.ONEPM=1 to enable single pulse mode, configure TIMx_CCMOD1.OC1MD = ‘111’to select PWM2 mode; 6. Wait for an external trigger event on TI2, and a one pulse waveform will be output on OC1; Special case: OCx fast enable: In one-pulse mode, an edge is detected through the TIx input, and triggers the start of the counter to count to the comparison value and then output a pulse.
Page 210: Complementary Outputs With Dead-Time Insertion
Figure 10-24 Clearing The Ocxref of Timx ETRF (CCDATx) Counter(CNT) OCxREF (OCxCEN=＇0＇) OCxREF (OCxCEN=＇１＇) still ETRF ETRF becomes high high Complementary Outputs with Dead-Time Insertion Advanced-control timer can output two complementary signals with dead time in between. User should adjust dead- time depending on the devices connected to the outputs and their characteristics.
Page 211: Redirecting Ocxref To Ocx Or Ocxn
Figure 10-25 Complementary Output with Dead-Time Insertion OCxREF Complementary output with dead-time insertion Delay OCxN Delay Dead-time waveform with delay greater OCxREF than the negative pulse Delay OCxN Dead-time waveform OCxREF with delay larger than the positive pulse OCxN Delay User can set TIMx_BKDT.DTGN to programme the dead-time delay for each of the channels.
Page 212: Break Function
Break Function The output enable signals and inactive levels will be modified when setting the corresponding control bits when using the break function. However, the output of OCx and OCxN cannot at the active level at the same time no matter when, that is, (CCxP^OIx) ^(CCxNP^OIxN)!=0.
Page 213: Figure 10-26 Output Behavior In Response To A Break
– Timer will release the output control if TIMx_BKDT.OSSI=0. Otherwise, if the enable output was high, it will remain high. If it was low, it will become high when TIMx_CCEN.CCxEN or TIMx_CCEN.CCxNEN is high. • If TIMx_DINTEN.BIEN=1, when TIMx_STS.BITF=1, an interrupt will be generated. •...
Page 214: Debug Mode
Debug Mode ® When the microcontroller is in debug mode (the Cortex -M4F core halted), depending on the DBG_CTRL.TIMx_STOP configuration in the DBG module, the TIMx counter can either continue to work normally or stop. For more details, see 28.4.3. TIMx And External Trigger Synchronization TIMx timers can be synchronized by a trigger in slave modes (reset, trigger and gated).
Page 215: Figure 10-28 Control Circuit In Trigger Mode
Slave mode: Trigger mode In trigger mode, the trigger event (rising edge/falling edge) of the input port can trigger the counter to start counting. The following is an example of a trigger pattern: 1. Channel 2 is configured as input to detect the rising edge of TI2 (TIMx_CCMOD1.CC2SEL=01, TIMx_CCEN.CC2P=0);...
Page 216: Figure 10-29 Control Circuit In Gated Mode
TI1 input. Figure 10-29 Control Circuit in Gated Mode Counter clock=CK_CNT=CK_PSC Counter register 30 31 32 33 36 37 38 CNTEN TITF Clear TITF Slave mode: Trigger Mode + External Clock Mode 2 In reset mode, trigger mode and gate control mode, the counter clock can be selected as external clock mode 2, and the ETR signal is used as the external clock source input.
Page 217: Timer Synchronization
Figure 10-30 Control Circuit in Trigger Mode + External Clock Mode2 Counter clock=CK_CNT=CK_PSC Counter register CNTEN TITF Timer Synchronization All TIM timers are internally interconnected for timer synchronization or chaining. For more details, see 11.3.14. Generating Six-Step PWM Output In order to modify the configuration of all channels at the same time, the configuration of the next step can be set in advance (the preloaded bits are OCxMD, CCxEN and CCxNEN).
Page 218: Encoder Interface Mode
Figure 10-31 6-Step PWM Generation, COM Example (OSSR=1) (CCRx) Counter (CNT) OCxREF write COM=1 COM event CCxEN=1 write OCxMD=100 CCxEN=1 CCxNEN=0 CCxNEN=0 OCxMD=100(forced inactive) OCxMD=100 OCxN write CCxNEN=0 CCxEN=1 和OCxMD=100 CCxNEN=0 CCxEN=1 OCxMD=100(forced inactive) CCxNEN=0 OCxMD=100 OCxN write CCxNEN=1 CCxEN=1 和OCxMD=101 CCxEN=0 CCxNEN=0...
Page 219: Table 10-1 Counting Direction Versus Encoder Signals
Table 10-1 Counting Direction Versus Encoder Signals Level on opposite signals TI1FP1 signal TI2FP2 signal Active edge (TI1FP1 forTI2, Rising Falling Rising Falling TI2FP2 for TI1) High Counting down Counting up Don't count Don't count Counting only at TI1 Counting up Counting down Don't count Don't count...
Page 220: Interfacing With Hall Sensor
Figure 10-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted forward jitter backward jitter Counter down Interfacing with Hall Sensor Connect the Hall sensor to the three input pins (CC1, CC2 and CC3) of the timer, and then select the XOR function to pass the inputs of TIMx_CH1, TIMx_CH2 and TIMx_CH3 through the XOR gate as the output of TI1 to channel 1 for capture signal.
Page 221: Figure 10-34 Example Of Hall Sensor Interface
Figure 10-34 Example of Hall Sensor Interface Interfacing timer Counter(CNT) (CCDAT2) CCDAT1 TRGO=OC2REF Advanced-control timers(TIM1&TIM8) OC1N OC2N OC3N Write CCxEN、CCxNEN and OCxMD for next step 196 / 652...
Page 222: Timx Register Description(X=1, 8)
TIMx Register (x=1, 8) For abbreviations used in registers, see section 1.1. These peripheral registers can be operated as half word (16-bits) or one word (32-bits). TIMx Register Overview Table 10-2 TIMx Register Overview Offset Register TIMx_CTRL1 000h Reset Value TIMx_CTRL2 004h Reset Value...
Page 223: Control Register 1 (Timx_Ctrl1)
Offset Register Reset Value TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC PSC[15:0] 028h Reserved Reset Value TIMx_AR AR[15:0] 02Ch Reserved Reset Value TIMx_REPCNT REPCNT[7:0] 030h Reserved Reset Value TIMx_CCDAT1 CCDAT1[15:0] 034h Reserved Reset Value TIMx_CCDAT2 CCDAT2[15:0] 038h Reserved Reset Value TIMx_CCDAT3 CCDAT3[15:0] 03Ch...
Page 224 Bit Field Name Description 31:18 Reserved Reserved, the reset value must be maintained PBKPEN PVD as BKP enable 0: Disable 1: Enable LBKPEN LockUp as BKP enable 0: Disable 1: Enable CLRSEL OCxREF clear selection 0: Select the external OCxREF clear from ETR 1: Select the internal OCxREF clear from comparator 14:12 Reserved...
Page 225: Control Register 2 (Timx_Ctrl2)
Bit Field Name Description ONEPM One-pulse mode 0: Disable one-pulse mode, the counter counts are not affected when an update event occurs. 1: Enable one-pulse mode, the counter stops counting when the next update event occurs (clearing TIMx_CTRL1.CNTEN bit) UPRS Update request source This bit is used to select the UEV event sources by software.
Page 226 Bit Field Name Description 31:19 Reserved Reserved, the reset value must be maintained Output idle state 6 (OC6 output). See TIMx_CTRL2.OI1 bit. Reserved Reserved, the reset value must be maintained Output idle state 5 (OC5 output). See TIMx_CTRL2.OI1 bit. Reserved Reserved, the reset value must be maintained Output idle state 4 (OC4 output).
Page 227: Slave Mode Control Register (Timx_Smctrl)
Bit Field Name Description CCDSEL Capture/compare DMA selection 0: When a CCx event occurs, a DMA request for CCx is sent. 1: When an update event occurs, a DMA request for CCx is sent. CCUSEL Capture/compare control update selection 0: If TIMx_CTRL2.CCPCTL = 1, they can only be updated by setting CCUDGN bits 1: If TIMx_CTRL2.CCPCTL = 1, they can be updated by setting CCUDGN bits or a rising edge on TRGI.
Page 228 Name Description Field Note 3: Setting the TIMx_SMCTRL.EXCEN bit has the same effect as selecting external clock mode 1 and connecting TRGI to ETRF (TIMx_SMCTRL.SMSEL = 111 and TIMx_SMCTRL.TSEL = 111). 13:12 EXTPS[1:0] External trigger prescaler The frequency of the external trigger signal ETRP must be at most 1/4 of TIMxCLK frequency. When a faster external clock is input, a prescaler can be used to reduce the frequency of ETRP.
Page 229: Dma/Interrupt Enable Registers (Timx_Dinten)
Name Description Field For more details on ITRx, see Table 10-3 below. Note: These bits must be changed only when not in use (e. g. TIMx_SMCTRL.SMSEL=000) to avoid false edge detection at the transition. Reserved Reserved, the reset value must be maintained SMSEL[2:0] Slave mode selection When an external signal is selected, the active edge of the trigger signal (TRGI) is linked to the...
Page 230 Bit Field Name Description Reserved Reserved, the reset value must be maintained TDEN Trigger DMA request enable 0: Disable trigger DMA request 1: Enable trigger DMA request COMDEN COM DMA request enable 0: Disable COM DMA request 1: Enable COM DMA request CC4DEN Capture/Compare 4 DMA request enable 0: Disable capture/compare 4 DMA request...
Page 231: Status Registers (Timx_Sts)
Bit Field Name Description 0: Disable capture/compare 1 interrupt 1: Enables capture/comparing 1 interrupt UIEN Update interrupt enable 0: Disable update interrupt 1: Enables update interrupt Status Registers (TIMx_STS) Offset address: 0x10 Reset value: 0x0000 0000 Bit Field Name Description 31：18 Reserved Reserved, the reset value must be maintained...
Page 232 Bit Field Name Description TITF Trigger interrupt flag This bit is set by hardware when an active edge is detected on the TRGI input when the slave mode controller is in a mode other than gated. This bit is set by hardware when any edge in gated mode is detected.
Page 233: Event Generation Registers (Timx_Evtgen)
Bit Field Name Description This bit is cleared by software. 0: No update event occurred 1: Update interrupt occurred Event Generation Registers (TIMx_EVTGEN) Offset address: 0x14 Reset values: 0x0000 Bit Field Name Description 15：8 Reserved Reserved, the reset value must be maintained Break generation This bit can generate a brake event when set by software.
Page 234: Capture/Compare Mode Register 1 (Timx_Ccmod1)
Bit Field Name Description cleared by hardware. When the corresponding channel of CC1 is in output mode: The TIMx_STS.CC1ITF flag will be pulled high, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be generated. When the corresponding channel of CC1 is in input mode: TIMx_CCDAT1 will capture the current counter value, and the TIMx_STS.CC1ITF flag will be pulled high, if the corresponding interrupt and DMA are enabled, the corresponding interrupt...
Page 235 Bit Field Name Description 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is only active when the internal trigger input is selected by TIMx_SMCTRL.TSEL. Note: CC2SEL is writable only when the channel is off (TIMx_CCEN.CC2EN = 0).
Page 236 Bit Field Name Description 1: An active edge of the trigger input acts like a comparison match on CC1 output. Therefore, OC is set to the comparison level regardless of the comparison result. The delay time for sampling the trigger input and activating the CC1 output is reduced to 3 clock cycles. OCxFEN only works if the channel is configured in PWM1 or PWM2 mode.
Page 237: Capture/Compare Mode Register 2 (Timx_Ccmod2)
Bit Field Name Description 1010: f /16, N = 5 SAMPLING 1011: f /16, N = 6 SAMPLING 1100: f /16, N = 8 SAMPLING 1101: f /32, N = 5 SAMPLING 1110: f /32, N = 6 SAMPLING 1111: f /32, N = 8 SAMPLING IC1PSC[1:0]...
Page 238 Bit Field Name Description 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is only active when the internal trigger input is selected by TIMx_SMCTRL.TSEL. Note: CC4SEL is writable only when the channel is off (TIMx_CCEN.CC4EN = 0).
Page 239: Capture/Compare Enable Registers (Timx_Ccen)
Name Description Field the internal trigger input is selected by TIMx_SMCTRL.TSEL. Note: CC3SEL is writable only when the channel is off (TIMx_CCEN.CC3EN = 0). Capture/Compare Enable Registers (TIMx_CCEN) Offset address: 0x20 Reset value: 0x0000 0000 Bit Field Name Description 31:22 Reserved Reserved, the reset value must be maintained CC6P...
Page 240 Bit Field Name Description CC2NEN Capture/Compare 2 complementary output enable See TIMx_CCEN.CC1NEN description. CC2P Capture/Compare 2 output polarity See TIMx_CCEN.CC1P description. CC2EN Capture/Compare 2 output enable See TIMx_CCEN.CC1EN description. CC1NP Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low CC1NEN Capture/Compare 1 complementary output enable 0: Disable - Disable output OC1N signal.
Page 241: Counters (Timx_Cnt)
Table 10-4 Output Control Bits Of Complementary Ocx And Ocxn Channels With Break Function Control Bits Output State MOEN OSSI OSSR CCxEN CCxNEN OCx Output state OCxN Output state Output disabled（not driven by timer） Output disabled（not driven by timer） OCx=0，OCx_EN=0 OCxN=0，OCxN_EN=0 Output disabled（not driven by timer）...
Page 242: Prescaler (Timx_Psc)
Bit Field Name Description 15:0 CNT[15:0] Counter value Prescaler (TIMx_PSC) Offset address: 0x28 Reset value: 0x0000 Bit Field Name Description 15:0 PSC[15:0] Prescaler value Counter clock f / (PSC [15:0] +1). CK_CNT CK_PSC Each time an update event occurs, the PSC value is loaded into the active prescaler register. Auto-reload Register (TIMx_AR) Offset address: 0x2C Reset values: 0xFFFF...
Page 243: Capture/Compare Register 1 (Timx_Ccdat1)
Bit Field Name Description The repetition counter is decremented at each counter overflow in up-counting mode, at each counter underflow in down-counting mode or at each counter overflow and at each counter underflow in center-aligned mode. Setting the TIMx_EVTGEN.UDGN bit will reload the content of TIMx_REPCNT.REPCNT and generate an update event.
Page 244: Capture/Compare Register 3 (Timx_Ccdat3)
Name Description Field If the preload feature is not selected in TIMx_CCMOD1.OC2PEN bit, the written value is immediately transferred to the active register. Otherwise, this preloaded value is transferred to the active register only when an update event occurs. • CC2 channel is configured as input: CCDAT2 contains the counter value transferred by the last input capture 2 event (IC2).
Page 245: Break And Dead-Time Registers (Timx_Bkdt)
15:0 CCDAT4[15:0] Capture/Compare 4 value • CC4 channel is configured as output: CCDAT4 contains the value to be compared to the counter TIMx_CNT, signaling on the OC4 output. If the preload feature is not selected in TIMx_CCMOD2.OC4PEN bit, the written value is immediately transferred to the active register.
Page 246 Bit Field Name Description OSSR Off-state Selection for Run Mode This bit is used when TIMx_BKDT.MOEN=1 and the channel is a complementary output. The OSSR bit does not exist in timer without complementary outputs. 0: When inactive, OCx/OCxN outputs are disabled (OCx/OCxN enable output signal=0). 1: When inactive, OCx/OCxN outputs are enabled with their inactive level as soon as CCxEN=1 or CCxNEN=1.
Page 247: Dma Control Register (Timx_Dctrl)
Bit Field Name Description DTGN [then] = 111: dead time = (32 + DTGN [4:0]) × (16 × t value see TIMx_CTRL1.CLKD [1:0]. DMA Control Register (TIMx_DCTRL) Offset address: 0x48 Reset value: 0x0000 Bit Field Name Description 15:9 Reserved Reserved, the reset value must be maintained, kept at 0. 12:8 DBLEN[4:0] DMA Burst Length...
Page 248: Capture/Compare Mode Registers 3(Timx_Ccmod3)
Bit Field Name Description 15:0 BURST[15:0] DMA access buffer. When a read or write operation is assigned to this register, the register located at the address range (DMA base address + DMA burst length × 4) will be accessed. DMA base address = The address of TIM_CTRL1 + TIMx_DCTRL. DBADDR * 4； DMA burst len = TIMx_DCTRL.DBLEN + 1.
Page 249: Capture/Compare Register 6 (Timx_Ccdat6)
Reset value: 0x0000 CCDAT5[15:0] Name Description Field 15:0 CCDAT5[15:0] Capture/Compare 5 value • CC5 channel can only configured as output: CCDAT5 contains the value to be compared to the counter TIMx_CNT, signaling on the OC5 output. If the preload feature is not selected in TIMx_CCMOD3.OC5PEN bit, the written value is immediately transferred to the active register.
Page 250: General-Purpose Timers (Tim2, Tim3, Tim4, Tim5 And Tim9)
11 General-purpose Timers (TIM2, TIM3, TIM4, TIM5 and TIM9) General-purpose Timers Introduction The general-purpose timers (TIM2, TIM3, TIM4, TIM5 and TIM9) is mainly used in the following scenarios: counting the input signal, measuring the pulse width of the input signal and generating the output waveform, etc. Main Features of General-purpose Timers •...
Page 251: General-Purpose Timers Description
Figure 11-1 Block Diagram of Timx（x=2, 3 ,4 ,5 and 9） TIMxCLK from RCC Internal clock(CK_INT) To another timer, ADC, Polarity selection ETRF TRGO Edge detector Trigger controller TIMx_ETR pin Prescaler Input filter Reset, enable, COMP_TIM_ up/down, count OCREFCLR Slave mode controller TI1F_ED TRGI...
Page 252: Counter Mode
when the counter reaches the overflow/underflow condition and it can be generated by software when TIMx_CTRL1.UPDIS=0. The counter CK_CNT is valid only when the TIMx_CTRL1.CNTEN bit is set. The counter starts counting one clock cycle after the TIMx_CTRL1.CNTEN bit is set. Prescaler description The TIMx_PSC register consists of a 16-bit counter that can be used to divide the counter clock frequency by any factor between 1 and 65536.
Page 253: Figure 11-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
• Update auto-reload shadow registers with preload value(TIMx_AR), when TIMx_CTRL1.ARPEN = 1. • The prescaler shadow register is reloaded with the preload value(TIMx_PSC). To avoid updating the shadow registers when new values are written to the preload registers, you can disable the update by setting TIMx_CTRL1.UPDIS=1.
Page 254: Figure 11-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 11-4 Timing Diagram Of The Up-counting, Update Event When ARPEN=0/1 ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT Counter register 33 34 35 36 00 01 02 03 04 05 06 07 Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 255: Figure 11-5 Timing Diagram Of The Down-Counting, Internal Clock Divided Factor = 2/N
Down-counting mode In down-counting mode, the counter will decrement from the value of the register TIMx_AR to 0, then restart from the auto-reload value and generate a counter underflow event. The process of configuring update events and updating registers in down-counting mode is the same as in up-counting mode, see 11.3.2.1.
Page 256: Figure 11-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N
Alternatively, an update event can also be generated by setting the TIMx_EVTGEN. UDGN bit (either by software or using a slave mode controller). In this case, the counter restarts from 0, as does the prescaler's counter. Please note: if the update source is a counter overflow, auto-reload update before reloading the counter. Figure 11-6 Timing Diagram of The Center-aligned, Internal Clock Divided Factor =2/N Internal clock CK_PSC...
Page 257: Clock Selection
Figure 11-7 A Center-aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1) Counter underflow CNTEN CK_PSC Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Write a new value in TIMx_AR...
Page 258: Figure 11-8 Control Circuit In Normal Mode, Internal Clock Divided By 1
– external input pin external trigger input ETR – • Internal trigger input (ITRx): one timer is used as a prescaler for another timer. Internal clock source (CK_INT) When the TIMx_SMCTRL.SMSEL is equal to “000”, the slave mode controller is disabled. The three control bits (TIMx_CTRL1.CNTEN、TIMx_CTRL1.
Page 259: Figure 11-9 Ti2 External Clock Connection Example
External clock source mode 1 Figure 11-9 TI2 External Clock Connection Example Filter (TIMx_CCMOD1.ICF[3:0]) Edge Detector TIMx_SMCTRL. CK_INT rising TSEL[2:0] Internal clock mode Polarity Selection （ TIMx_CCEN.CC2P ） ITRx TRGI rising TI1_ED External clock mode 1 TI1FP1 TI2FP2 CK_PSC ETRF ETRF rising External clock mode 2 TI2F rising or falling...
Page 260: Figure 11-10 Control Circuit In External Clock Mode 1
Figure 11-10 Control Circuit in External Clock Mode 1 CNTEN Timer clock = CK_CNT=CK_PSC Counter register TITF Write TITF=0 External clock source mode 2 This mode is selected by TIMx_SMCTRL .EXCEN equal to 1. The counter can count on every rising or falling edge of the external trigger input ETR.
Page 261: Capture/Compare Channels
• Turn on the counter by setting TIMx_CTRL1. CNTEN equal to ‘1’ The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to the counter is due to a resynchronization circuit on the ETRP signal. Figure 11-12 Control Circuit in External Clock Mode 2 CNTEN CK _INT...
Page 262: Figure 11-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
Figure 11-13 Capture/Compare Channel (example: channel 1 input stage) From slave mode controller TI2FP1 Divider /1,/2,/4,/8 TI2F_Rising From channel 2 IC1PSC TI1FP1 TI2F_Falling TIMx_CCMOD1. Polarity Selection IC1PSC[1:0] TIMx_CCMOD1.CC1SEL[3:0] TIMx_CCEN.CC2P TIMx_CCEN.CC1EN Filter Down counter TIMx_CCMOD1.IC1F[ Edge Detector 3:0] TI1F_Rising TI1F To the slave TI1F_Falling mode controller Polarity Selection...
Page 263: Figure 11-14 Capture/Compare Channel 1 Main Circuit
Figure 11-14 Capture/Compare Channel 1 Main Circuit CC1SEL[1] CC1SEL[0] Input IC1PSC CC1EN mode Read CCDAT1H TIM1_EVTGEN.CC1GN Read CCDAT1L Read in APB Bus progress MCU Peripheral interface 16 bit High 8-bits Capture/ Capture/ transfer compare compare Counter preload register shadow register Low 8-bits Output Comparator...
Page 264: Input Capture Mode
Figure 11-15 Output Part of Channelx （x = 1,2,3,4;take channel 4 as an example） To the master mode controller Output enable Output enable Polarity circuit circuit selection TIM1_CCEN. CC4P Ocref_clr ETRF TIM1_CCEN.CC4EN OC4 REF CNT=CCDAT4 CNT>CCDAT4 Output mode controller TIM1_CCMOD2.OC2M D[2:0] Reads and writes always access preloaded registers when capturing/comparing.
Page 265: Pwm Input Mode
TIMx_CCMODx.ICxF bits. Example: If the input signal jitters up to 5 internal clock cycles, we must choose a filter duration longer than these 5 clock cycles. When 8 consecutive samples (sampled at f frequency) with the new level are detected, we can validate the transition on TI1. Then configure TIMx_CCMOD1. IC1F to ‘0011’.
Page 266: Forced Output Mode
Figure 11-16 PWM Input Mode Timing TIMx_CNT 0004 0000 0001 0002 0003 0004 0000 TIMx_CCDAT1 0004 0002 TIMx_CCDAT2 IC1 capture IC2 capture IC1 capture IC2 capture Pulse width Period Reset counter measurement measurement Because of only filter timer input 1 (TI1FP1) and filter timer input 2 (TI2FP2) are connected to the slave mode controller, the PWM input mode can only be used with the TIMx_CH1/TIMx_CH2 signals.
Page 267 the compare matches, if set TIMx_CCMODx.OCxMD=000, the output pin will keep its level;if set TIMx_CCMODx.OCxMD=001, the output pin will be set active;if set TIMx_CCMODx.OCxMD=010, the output pin will be set inactive;if set TIMx_CCMODx.OCxMD=011, the output pin will be set to toggle. •...
Page 268: Pwm Mode
Figure 11-17 Output Compare Mode, Toggle on OC1 TIM1_CNT 0069 006A 006B 8800 8801 TIM1_CCDAT1 006A 8801 Write 8801h in CCDAT1 register OC1REF=OC1 Match detected on CCDAT1 Interrupt generated if enabled PWM Mode User can use PWM mode to generate a signal whose duty cycle is determined by the value of the TIMx_CCDATx register and whose frequency is determined by the value of the TIMx_AR register.
Page 269: Figure 11-18 Center-Aligned Pwm Waveform (Ar=8)
Examples of center-aligned PWM waveforms is as follow, and the setting of the waveform are: TIMx_AR=8, PWM mode 1, the compare flag is set when the counter counts down corresponding to TIMx_CTRL1. CAMSEL=01. Figure 11-18 Center-aligned PWM Waveform (AR=8) Counter register OCXREF CCDATx=0 CAMSEL=01...
Page 270: Figure 11-19 Edge-Aligned Pwm Waveform (Apr=8)
before starting the counter, and not writing the counter while it is running. PWM edge-aligned mode There are two kinds of configuration in edge-aligned mode, up-counting and down-counting. • Up-counting User can set TIMx_CTRL1.DIR=0 to make counter counts up. Example for PWM mode1. When TIMx_CNT <...
Page 271: One-Pulse Mode
Note: If the nth PWM cycle CCDATx shadow register >= AR value, the shadow register value of CCDATx in the (n+1)th PWM cycle is 0. At the moment when the counter is 0 in the (n+1)th PWM cycle, although the value of the counter = CCDATx shadow register = 0 and OCxREF = '0', no compare event will be generated.
Page 272: Clearing The Ocxref Signal On An External Event
the pulse width t PULSE 5. Configure TIMx_CTRL1.ONEPM=1 to enable single pulse mode, configure TIMx_CCMOD1.OC1MD = ‘111’ to select PWM2 mode; 6. Wait for an external trigger event on TI2, and a one pulse waveform will be output on OC1; Special case: OCx fast enable: In one-pulse mode, an edge is detected through the TIx input, and triggers the start of the counter to count to the comparison value and then output a pulse.
Page 273: Debug Mode
Figure 11-21 Control Circuit in Reset Mode ETRF (CCDATx) Counter(CNT) OCxREF (OCxCEN=＇0＇) OCxREF (OCxCEN=＇１＇) still ETRF ETRF becomes high high Debug Mode When the microcontroller is in debug mode (the Cortex ® -M4F core halted), depending on the DBG_CTRL.TIMx_STOP configuration in the DBG module, the TIMx counter can either continue to work normally or stop.
Page 274: Figure 11-22 Block Diagram Of Timer Interconnection
Figure 11-22 Block Diagram of Timer Interconnection TIMx （Slave TIM） Clock Prescaler Trigger Counter selection ITRx Slave mode control TRGO TIMx_SMCTRL.SMSEL Master mode control TIMx_CTRL2.MMSEL TIMx_SMCTRL. CK_PSC TSEL Prescaler TIMx（Master TIM） Counter Master timer as a prescaler for another timer TIM1 as a prescaler for TIM2.
Page 275: Figure 11-23 Tim2 Gated By Oc1Ref Of Tim1
• Set TIM2_SMCTRL.SMSEL= ‘101’ to set TIM2 to gated mode. • Set TIM2_CTRL1.CNTEN= ‘1’ to start TIM2. • Set TIM1_CTRL1.CNTEN= ‘1’ to start TIM1. Note: The TIM2 clock is not synchronized with the TIM1 clock, this mode only affects the TIM2 counter enable signal. Figure 11-23 TIM2 Gated by OC1REF of TIM1 TIM1 CK_INT...
Page 276: Figure 11-24 Tim2 Gated By Enable Signal Of Tim1
Figure 11-24 TIM2 Gated by Enable Signal of TIM1 TIM1 CK_INT CNTEN TIM2 TITF Clear TITF Master timer to start another timer In this example, we can use update event as trigger source.TIM1 is master, TIM2 is slave. The configuration steps are shown as below: •...
Page 277: Figure 11-25 Trigger Tim2 With An Update Of Tim1
Figure 11-25 Trigger TIM2 with an Update of TIM1 TIM1 CK_INT TIM2 CNTEN TITF Clear TITF Start 2 timers synchronously using an external trigger In this example, TIM1 is enabled when TIM1's TI1 input rises, and TIM2 is enabled when TIM1 is enabled. To ensure the alignment of counters, TIM1 must be configured in master/slave mode.
Page 278: Encoder Interface Mode
Figure 11-26 Triggers Timers 1 and 2 Using the TI1 Input of TIM1 TIM1 CK_INT CNTEN CK_PSC 02 03 04 05 06 07 08 09 TITF TIM2 CNTEN CK_PSC 01 02 03 04 05 06 07 08 09 TITF Encoder Interface Mode The encoder uses two inputs TI1 and TI2 as an interface and the counter counts on every edge change on TI1FP1 or TI2FP2.
Page 279: Figure 11-27 Example Of Counter Operation In Encoder Interface Mode
(TI1FP1 forTI2, Rising Falling Rising Falling TI2FP2 for TI1) High Counting down Counting up Don't count Don't count Counting only at TI1 Counting up Counting down Don't count Don't count High Don't count Don't count Counting up Counting down Counting only at TI2 Don't count Don't count Counting down...
Page 280: Interfacing With Hall Sensor
Figure 11-28 Encoder Interface Mode Example with IC1FP1 Polarity Inverted forward jitter backward jitter Counter down Interfacing With Hall Sensor Please refer to 10.3.20 TIMx Registers (x=2, 3 ,4 ,5 and 9) For abbreviations used in registers, see section 1.1. These peripheral registers can be operated as half word (16-bits) or one word (32-bits).
Page 281 Offset Register TIMx_DINTEN 00Ch Reset Value TIMx_STS 010h Reset Value TIMx_EVTGEN 014h Reset Value TIMx_CCMOD1 Reset Value 018h TIMx_CCMOD1 Reset Value TIMx_CCMOD2 01Ch Reset Value TIMx_CCMOD2 01Ch Reset Value TIMx_CCEN 020h Reset Value TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC PSC[15:0] 028h Reserved...
Page 282: Control Register 1 (Timx_Ctrl1)
Control Register 1 (TIMx_CTRL1) Offset address: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained CLRSEL OCxREF clear selection 0: Select the external OCxREF clear from ETR 1: Select the internal OCxREF clear from comparator Note: For TIM5, setting to 1 is invalid C4SEL Channel 4 Selection...
Page 283 Bit Field Name Description 1: Shadow register enable for TIMx_AR register CAMSEL[1:0] Center-aligned mode selection 00: Edge-aligned mode. TIMx_CTRL1.DIR specifies up-counting or down-counting. 01: Center-aligned mode 1. The counter counts in center-aligned mode, and the output compare interrupt flag bit is set to 1 when down-counting. 10: Center-aligned mode 2.
Page 284: Control Register 2 (Timx_Ctrl2)
Bit Field Name Description Note: external clock, gating mode and encoder mode can only work after TIMx_CTRL1.CNTEN bit is set in the software. Trigger mode can automatically set TIMx_CTRL1.CNTEN bit by hardware. Control Register 2 (TIMx_CTRL2) Offset address: 0x04 Reset value: 0x0000 Bit Field Name Description...
Page 285: Slave Mode Control Register (Timx_Smctrl)
Bit Field Name Description 111: Compare - OC4REF signal is used as the trigger output (TRGO). CCDSEL Capture/compare DMA selection 0: When a CCx event occurs, a DMA request for CCx is sent. 1: When an update event occurs, a DMA request for CCx is sent. Reserved Reserved, the reset value must be maintained Slave Mode Control Register (TIMx_SMCTRL)
Page 286 Name Description Field These bits are used to define the frequency at which the ETRP signal is sampled and the bandwidth of the ETRP digital filtering. In effect, the digital filter is an event counter that generates a validate output after consecutive N events are recorded. 0000: No filter, sampling at f 0001: f , N = 2...
Page 287: Dma/Interrupt Enable Registers (Timx_Dinten)
Name Description Field 010: Encoder mode 2. According to the level of TI1FP1, the counter up-counting or down- counting on the edge of TI2FP2. 011: Encoder mode 3. According to the input level of another signal, the counter up-counting or down-counting on the edges of TI2FP1 and TI2FP2.
Page 288: Status Registers (Timx_Sts)
Bit Field Name Description 1: Enable capture/compare 4 DMA request CC3DEN Capture/Compare 3 DMA request enable 0: Disable capture/compare 3 DMA request 1: Enable capture/compare 3 DMA request CC2DEN Capture/Compare 2 DMA request enable 0: Disable capture/compare 2 DMA request 1: Enable capture/compare 2 DMA request CC1DEN Capture/Compare 1 DMA request enable...
Page 289 Bit Field Name Description 15:13 Reserved Reserved, the reset value must be maintained CC4OCF Capture/Compare 4 overcapture flag See TIMx_STS.CC1OCF description. CC3OCF Capture/Compare 3 overcapture flag See TIMx_STS.CC1OCF description. CC2OCF Capture/Compare 2 overcapture flags See TIMx_STS.CC1OCF description. CC1OCF Capture/Compare 1 overcapture flag This bit is set by hardware only when the corresponding channel is configured in input capture mode.
Page 290: Event Generation Registers (Timx_Evtgen)
Bit Field Name Description 1: Input capture occurred. Counter value has captured in the TIMx_CCDAT1. An edge with the same polarity as selected has been detected on IC1. UDITF Update interrupt flag This bit is set by hardware when an update event occurs under the following conditions: –...
Page 291: Capture/Compare Mode Register 1 (Timx_Ccmod1)
Bit Field Name Description When the corresponding channel of CC1 is in input mode: TIMx_CCDAT1 will capture the current counter value, and the TIMx_STS.CC1ITF flag will be pulled high, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be generated.
Page 292 Bit Field Name Description OC1CEN Output Compare 1 clear enable 0: OC1REF is not affected by ETRF input level 1: OC1REF is cleared immediately when the ETRF input level is detected as high OC1MD[2:0] Output Compare 1 mode These bits are used to manage the output reference signal OC1REF, which determines the values of OC1 and OC1N, and is valid at high levels, while the active levels of OC1 and OC1N depend on the TIMx_CCEN.CC1P and TIMx_CCEN.CC1NP bits.
Page 293 Bit Field Name Description 1：0 CC1SEL[1:0] Capture/compare 1 selection These bits are used to select the input/output and input mapping of the channel 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channels are configured as inputs and IC1 is mapped to TRC.
Page 294: Capture/Compare Mode Register 2 (Timx_Ccmod2)
Bit Field Name Description 1110: f /32, N = 6 SAMPLING 1111: f /32, N = 8 SAMPLING IC1PSC[1:0] Input Capture 1 prescaler These bits are used to select the ratio of the prescaler for IC1 (CC1 input). When TIMx_CCEN.CC1EN = 0, the prescaler will be reset. 00: No prescaler, capture is done each time an edge is detected on the capture input 01: Capture is done once every 2 events 10: Capture is done once every 4 events...
Page 295: Capture/Compare Enable Registers (Timx_Ccen)
Bit Field Name Description OC3CEN Output compare 3 clear enable OC3MD[2:0] Output compare 3 mode OC3PEN Output compare 3 preload enable OC3FEN Output compare 3 fast enable CC3SEL[1:0] Capture/Compare 3 selection These bits are used to select the input/output and input mapping of the channel 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped to TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4...
Page 296 Reset value: 0x0000 Bit Field Name Description 15:14 Reserved Reserved, the reset value must be maintained. CC4P Capture/Compare 4 output polarity See TIMx_CCEN.CC1P description. CC4EN Capture/Compare 4 output enable See TIMx_CCEN.CC1EN description. 11:10 Reserved Reserved, the reset value must be maintained CC3P Capture/Compare 3 output polarity See TIMx_CCEN.CC1P description.
Page 297: Counters (Timx_Cnt)
Table 11-4 Output Control Bits Of Standard Ocx Channel CCxEN OCx output status Disable output (OCx=0) OCx = OCxREF + polarity Note: The state of external I/O pins connected to standard OCx channels depends on the OCx channel state and GPIO and AFIO registers.
Page 298: Capture/Compare Register 1 (Timx_Ccdat1)
Bit Field Name Description See Section 11.3.1 for more details. When the TIMx_AR.AR [15:0] value is null, the counter does not work. Capture/Compare Register 1 (TIMx_CCDAT1) Offset address: 0x34 Reset value: 0x0000 Name Description Field 15:0 CCDAT1[15:0] Capture/Compare 1 value •...
Page 299: Capture/Compare Register 3 (Timx_Ccdat3)
Name Description Field • CC2 channel is configured as input: CCDAT2 contains the counter value transferred by the last input capture 2 event (IC2). When configured as input mode, register CCDAT2 is only readable. When configured as output mode, register CCDAT2 is readable and writable. Capture/Compare Register 3 (TIMx_CCDAT3) Offset address: 0x3C Reset value: 0x0000...
Page 300: Dma Control Register (Timx_Dctrl)
If the preload feature is not selected in TIMx_CCMOD2.OC4PEN bit, the written value is immediately transferred to the active register. Otherwise, this preloaded value is transferred to the active register only when an update event occurs. • CC4 channel is configured as input: CCDAT4 contains the counter value transferred by the last input capture 4 event (IC4).
Page 301: Dma Transfer Buffer Register (Timx_Daddr)
DMA Transfer Buffer Register (TIMx_DADDR) Offset address: 0x4C Reset value: 0x0000 Bit Field Name Description 15:0 BURST[15:0] DMA access buffer. When a read or write operation is assigned to this register, the register located at the address range (DMA base address + DMA burst length × 4) will be accessed. DMA base address = The address of TIM_CTRL1 + TIMx_DCTRL.
Page 302: Basic Timers (Tim6 And Tim7)
12 Basic Timers (TIM6 and TIM7) Basic Timers Introduction Basic timers TIM6 and TIM7 each contain a 16-bit auto-reload counter. These two timers are independent of each other and do not share any resources. The basic timer can provide a time reference for general purpose timers, and in particular can provide a clock for a digital-to-analog converter (DAC).
Page 303: Counter Mode
the software can read and write the corresponding registers (TIMx_PSC, TIMx_CNT and TIMx_AR) at any time. Depending on the setting of the auto-reload preload enable bit (TIMx_CTRL1.ARPEN), the value of the preload register is transferred to the shadow register immediately or at each update event UEV. When TIMx_CTRL1.UPDIS=0, an update event is generated when the counter reaches the overflow condition, or when the TIMx_EVTGEN.UDGN bit is set by software.
Page 304 to generate an update interrupt. Depending on the update request source is configured in TIMx_CTRL1.UPRS, when an update event occurs, TIMx_STS.UDITF is set, and all registers are updated: • Update auto-reload shadow registers with preload value(TIMx_AR), when TIMx_CTRL1.ARPEN = 1. •...
Page 305: Figure 12-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
Figure 12-3 Timing Diagram of Up-counting. The Internal Clock Divider Factor = 2/N Internal clock divided by 2 CNTEN CK_PSC Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update interrupt flag(UDITF) Update event(UEV) Internal clock divided by N CK_PSC...
Page 306: Figure 12-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 12-4 Timing Diagram of The , Update Event when ARPEN=0/1 Up-counting ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 307: Clock Selection
Clock Selection • The internal clock of timers : CK_INT Internal clock source (CK_INT) It is provided that the TIMx_CTRL1.CNTEN bit is written as' 1 ' by software, the clock source of the prescaler is provided by the internal clock CK_INT. Figure 12-5 Control Circuit in Normal Mode, Internal Clock Divided by 1 CEN=CNTEN Internal clock...
Page 308: Register Overview
TIMx Register Overview Table 12-1 TIMx Register Overview Offset Register TIMx_CTRL1 000h Reset Value TIMx_CTRL2 004h Reset Value 008h Reserved TIMx_DINTEN 00Ch Reset Value TIMx_STS 010h Reset Value TIMx_EVTGEN 014h Reset Value 018h Reserved 01Ch Reserved 020h Reserved TIMx_CNT CNT[15:0] 024h Reserved Reset Value...
Page 309: Control Register 2 (Timx_Ctrl2)
Bit Field Name Description 1: Shadow register enable for TIMx_AR register Reserved Reserved, the reset value must be maintained ONEPM One-pulse mode 0: Disable one-pulse mode, the counter counts are not affected when an update event occurs. 1: Enable one-pulse mode, the counter stops counting when the next update event occurs (clearing TIMx_CTRL1.CNTEN bit) UPRS Update request source...
Page 310: Dma/Interrupt Enable Registers (Timx_Dinten)
Bit Field Name Description 001: Enable - The TIMx_CTRL1.CNTEN bit is used as the trigger output (TRGO). Sometimes you need to start multiple timers at the same time or enable slave timer for a period of time. The counter enable signal is set when TIMx_CTRL1.CNTEN bit is set or the trigger input in gated mode is high.
Page 311: Event Generation Registers (Timx_Evtgen)
Bit Field Name Description – When TIMx_CTRL1.UPDIS = 0, and counter value overflow. – When TIMx_CTRL1.UPRS = 0, TIMx_CTRL1.UPDIS = 0, and set the TIMx_EVTGEN.UDGN bit by software to reinitialize the CNT. This bit is cleared by software. 0: No update event occurred 1: Update interrupt occurred Event Generation registers (TIMx_EVTGEN) Offset address: 0x14...
Page 312: Automatic Reload Register (Timx_Ar)
Bit Field Name Description 15:0 PSC[15:0] Prescaler value PSC register value will be updated to prescaler register at update event. Counter clock frequency is input clock frequency divide PSC + 1. Automatic reload register (TIMx_AR) Offset address: 0x2C Reset values: 0xFFFF Bit Field Name Description...
Page 313: Low Power Timer (Lptim)
13 Low Power Timer (LPTIM) Introduction The LPTIM is a 16-bit timer with multiple clock sources, it can keep running in all power modes except for Standby mode. LPTIM can run without internal clock source, it can be used as a “Pulse Counter”. Also, the LPTIM can wake up the system from low-power modes, to realize “Timeout functions”...
Page 314: Block Diagram
Block Diagram Figure 13-1 LPTIM Diagram APB Interface LPTIM Up to 8 exti trigger Glitch Software filter trigger 16bit ARR Mux trigger CLK MUX APB clock prescaler COMP 16bit counter Count mode 16bit compare Up/down Glitch Encoder Input2 filter Non- Glitch encoder Input1...
Page 315: Prescaler
• The LPTIM uses both external clock and internal clock. • The LPTIM only use external clock from comparator or external Input1. This configuration is suitable for low power application. LPTIM_CFG.CLKSEL and LPTIM_CFG.CNTMEN bits are used for the clock source configuration. The active clock edge is configured through LPTIM_CFG.CLKPOL[1:0] bits.
Page 316: Timer Enable
Figure 13-2 Glitch Filter Timing Diagram 2 consecutive samples 2 consecutive samples Filtered Filter out Input CLKMUX Note: If no internal clock is used, the glitch filter needs to be turned off by clearing LPTIM_CFG.CLKFLT[1:0] and LPTIM_CFG.TRIGFLT[1:0] bits. If glitch filter is not used, the user can use a digital filter in the comparator or an external analog filter to remove the glitch.
Page 317: Operating Mode
RTC alarm B RTC_TAMP1 RTC_TAMP2 RTC_TAMP3 COMP1_OUT COMP2_OUT Operating Mode The LPTIM has two operating modes: • Continuous mode: A trigger event will start the LPTIM and it will continue running until the user switched off the LPTIM. • One-shot mode: A trigger event will start the LPTIM and it will stop when the counter value reaches LPTIM_ARR.ARRVAL[15:0].
Page 318: Figure 13-4 Ptim Output Waveform, Single Counting Mode Configuration
LPTIM_CTRL.TSTCM bit to 1 will switch the LPTIM to continuous counting mode. Counter will restart as soon as LPTIM_ARR register value is reached. One-shot mode: LPTIM_CTRL.SNGMST bit must be set to enable the one-shot mode. A trigger event will re-start the LPTIM. Hardware will abandon all the trigger events after the internal counter starts and before the counter value equal to LPTIM_ARR.ARRVAL[15:0] value.
Page 319: Waveform Generation
Figure 13-5 LPTIM Output Waveform, Single Counting Mode Configuration and One-Time Mode Activated LPTIM_ARR Compare Discarded trigger External trigger event In case of software start (LPTIM_CFG.TRGEN[1:0] = ‘00’), the LPTIM_CTRL.SNGMST setting will start the counter for one-shot counting. Waveform Generation The LPTIM auto-reload register(LPTIM_ARR) and compare register(LPTIM_COMP) are used for generating LPTIM output waveforms.
Page 320: Register Update
• LPTIM_CTRL.WAVE bit equals to ‘1’ forces the LPTIM to generate a Set-once mode waveform. The LPTIM_CFG.WAVEPOL bit controls LPTIM output polarity. The outputdefault valuewill change immediately after the user configured the polarity, even when the timer is disabled. Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. Only when LPTIM counter counting external clock active edge can achieve clock frequency divided by 2.
Page 321: Counter Mode
software write through APB bus and the moment when these values are available to the kernel logic. During this latency period, any additional write into these registers must be avoided. The update method of LPTIM_ARR and LPTIM_COMP registers is determined by the LPTIM_CFG.RELOAD bit: •...
Page 322: Encoder Mode
first five active edges on the LPTIM external Input1 (after LPTIM is enable) are lost. Encoder Mode The Encoder mode can handle signals from quadrature encoders which used to detect angular position of rotary elements. The encoder mode allows the counter counts the events within 0 and LPTIM_ARR.ARRVAL[15:0] value. (0 up to LPTIM_ARR.ARRVAL[15:0] or LPTIM_ARR.ARRVAL[15:0] to 0).
Page 323: Non-Orthogonal Encoder Mode
Figure 13-7 Encoder Mode Counting Sequence Coutnter Down Non-Quadrature Encoder Mode This mode allows handling signals from non-quadrature encoders, which is used to detect sub-sequent positive pulses from external interface. Non-Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to 0 depending on the direction).
Page 324: Timeout Function
direction of the incremental encoder. Therefore, its content always represents the encoder’s position. The count direction, signaled by the Up and Down flags, correspond to the rotation direction of the encoder rotor. The following two waveforms, the decoder module can work properly, when there is no case that both Input1 and Input2 are high.
Page 325: Lptim Interrupts
LPTIM Interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_INTEN register: • Compare match • Auto-reload match (whatever the direction if encoder mode) • External trigger event • Autoreload register write completed • Compare register write completed •...
Page 326: Lptim Interrupt And Status Register (Lptim_Intsts)
Offset Register LPTIM_INTEN 008h Reserved Reset Value LPTIM_CFG 00Ch Reserved Reset Value LPTIM_CTRL 010h Reserved Reset Value LPTIM_COMP CMPVAL[15:0] 014h Reserved Reset Value LPTIM_ARR ARRVAL[15:0] 018h Reserved Reset Value LPTIM_CNT CNTVAL[15:0] 01Ch Reserved Reset Value LPTIM Interrupt And Status Register (LPTIM_INTSTS) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field...
Page 327: Lptim Interrupt Clear Register (Lptim_Intclr)
Bit Field Name Description In Encoder mode, hardware will set UP bit to inform the application the counter direction. ARRUPD Auto-reload value updated to register. Hardware sets ARRUPD to inform application that LPTIM_ARR register has been written by the APB1 bus successfully. For more details, see 13.4.8.
Page 328: Lptim Interrupt Enable Register (Lptim_Inten)
Bit Field Name Description Writing 1 to this bit clears the EXTRIG flag in the LPTIM_INTSTS register ARRMCF Autoreload match Clear Flag Writing 1 to this bit clears the ARRM flag in the LPTIM_INTSTS register CMPMCF compare match Clear Flag Writing 1 to this bit clears the CMPM flag in the LPTIM_INTSTS register LPTIM Interrupt Enable Register (LPTIM_INTEN) Address offset: 0x08...
Page 329: Lptim Configuration Register (Lptim_Cfg)
LPTIM Configuration Register (LPTIM_CFG) Address offset: 0x0C Reset value: 0x0000 0000 Note: The LPTIM_CFG register must only be modified when the LPTIM is disabled (LPTIM_CTRL.LPTIMEN bit reset to ‘0’) TIMOUT Reserved NENC CNTMEN RELOAD WAVEPOL WAVE TRGEN[1:0] Reserved TRGSEL[2:0] Reserved CLKPRE[2:0] Reserved TRIGFLT[1:0]...
Page 330 Bit Field Name Description 0: Deactivate Set-once mode, PWM / One Pulse waveform (depending on LPTIM_CTRL.TSTCM or LPTIM_CTRL.SNGMST bit) 1: Activate the Set-once mode TIMOUTEN Timeout enable 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the counter 18:17...
Page 331 Bit Field Name Description 00: Any trigger active level change is considered as a valid trigger. 01: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
Page 332: Lptim Control Register (Lptim_Ctrl)
LPTIM Control Register (LPTIM_CTRL) Address offset: 0x10 Reset value: 0x0000 0000 Bit Field Name Description 31:3 Reserved Reserved, the reset value must be maintained. TSTCM Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (LPTIM_CFG.TRGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode.
Page 333: Lptim Auto-Reload Register (Lptim_Arr)
Note: The LPTIM_COMP register must only be modified when the LPTIM is enabled (LPTIM_CTRL.LPTIMEN bit reset to ‘1’) Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 CMPVAL[15:0] Compare value CMPVAL is the compare value used by the LPTIM. LPTIM Auto-Reload Register (LPTIM_ARR) Address offset: 0x18 Reset value: 0x0000 0001...
Page 334 Reserved CNTVAL[15:0] Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 CNTVAL[15:0] Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Page 335: Real Time Clock (Rtc)
14 Real Time Clock (RTC) Introduction • The real-time clock (RTC) is an independent BCD timer/counter • The software supports daylight saving time compensation • Programmable periodic automatic wake-up timer • Two programmable alarm clocks • Two 32-bit registers contain programming alarm clock, hour, minute, second, year, month, day (day), week (day of the week) •...
Page 336 Main Function Describe • RTC_TSH • RTC_DATA • RTC_INITSTS (some bits) RTC core can be reset by backup domain reset Resets the RTC and preserves the contents of some registers in low power modes, including: • RTC_CTRL • RTC_PRE • RTC_CALIB •...
Page 337: Main Function
Main Function Describe Alarm A/Alarm B interrupt/event Wakeup interrupt/event Interrupts/events Timestamp interrupt/event Tamper interrupt/event Backup registers 20 independent backup registers Function Description RTC Block Diagram Figure 14-1 RTC Block Diagram EXTI0 EXTI1 Shadow register EXTI15 HSE/32 RTCCLK ck_spre ck_apre Asynchronous Default value Default value Timestamp...
Page 338: Gpio Controlled By Rtc
• 20 32-bit backup registers • RTC output function: − 256 Hz or 1Hz clock output (LSE frequency is 32.768 kHz). − Alarm clock output (polarity configurable), Alarm A and Alarm B are optional. − Auto wakeup output (polarity configurable). •...
Page 339: Rtc Calendar
• LSE clock • LSI clock • HSE/32 clock For the purpose of reduction of power consumption, the prescaler is divided into 2 programmable prescalers, they are asynchronous prescaler and synchronous prescaler. If both prescaler are used, it is recommended that the value of the asynchronous divider be as large as possible.
Page 340: Calendar Reading
• Enter initialization mode by setting “1” to RTC_INITSTS.INITM bit, then wait for RTC_INITSTS.INITF flag to be set 1. • Set RTC_PRE.DIVS[14:0] and RTC_PRE.DIVA[6:0] value. • Write the initial calendar values include time and date into the shadow registers (RTC_TSH and RTC_DATE) and configure the time format (12 or 24 hours) by the RTC_CTRL.HFMT bit.
Page 341: Calibration Clock Output
To ensure the correctness of read calendar value, it is necessary to read RTC_SUBS, RTC_TSH and RTC_DATE twice, then compare the data read twice, if they are equal, the read data can be considered correct. Calibration Clock Output When RTC_CTRL.COEN set to 1, PC13 pin will output calibration clock. If RTC_CTRL.CALOSEL=0 and RTC_PRE.DIVA[6:0] = 0x7F, the RTC_CALIB frequency is f /RTC_PRE.DIVA[6:0].
Page 342: Periodic Automatic Wakeup
RTC_OPT.TYPE bit control the RTC_ALARM pin to output open drain or output pull-up. When RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin (PC13) is automatically configured as output. The duty cycle is about 4%*10 Periodic Automatic Wakeup A 16-bit programmable auto-load down counter can generate periodic wakeup flag. Periodic automatic wakeup can be enabled by setting RTC_CTRL.WTEN.
Page 343: Tamper Detection
RTC_INITSTS.TISOVF flag to 1, and the timestamp registers (RTC_TST and RTC_TSD) will continue to hold the value of the previous event, which means timestamp registers(RTC_TST and RTC_TSD) data will not change when RTC_INITSTS.TISF=1. After the timestamp event caused by the synchronization process occurs again, RTC_INITSTS.TISF is set to 1 in 2 RTC_CLK cycles.
Page 344: Daylight Saving Time Configuration
The internal pull-up resistance of tamper pin can be precharged before each sampling, and the precharge time is controlled by RTC_TMPCFG.TPPRCH[1:0] bits. Precharge will be disabled when RTC_TMPCFG.TPPUDIS set 1. Using RTC_TMPCFG.TPFREQ[2:0] to determine the sampling frequency of level detection can optimize the best balance between tamper detection delay and pull-up power consumption.
Page 345 seconds. The precision calibration register (RTC_CALIB) indicates that there has RTC_CALIB.CM[8:0] RTCCLK clock cycles will be reduced during the specified period. The value of RTC_CALIB.CM[8:0] represents the number of RTCCLK pulses to be reduced during specified period. While RTC_CALIB.CP can be used to increase 488.5 PPM, every 2 RTCCLK cycles will inserts a RTCCLK pulse.
Page 346: Rtc Low Power Mode
Using an accurate 8-second period to measure the 1Hz calibration output can ensure that the measurement error is within 1.907ppm (0.5 RTCCLK cycles within 8 seconds). Dynamic recalibration When RTC_INITSTS.INITF=0, RTC_CALIB register can update by using following steps: • Wait RTC_INITSTS.RECPF=0. •...
Page 347: Rtc Calendar Time Register (Rtc_Tsh)
Offset Register RTC_WKUPT WKUPT[15:0] 014h Reserved Reset Value RTC_ALARMA DTT[1:0] DTU[3:0] HOT[1:0] HOU[3:0] MIT[2:0] MIU[3:0] SET[2:0] SEU[3:0] 01Ch Reset Value RTC_ALARMB DTT[1:0] DTU[3:0] HOT[1:0] HOU[3:0] MIT[2:0] MIU[3:0] SET[2:0] SEU[3:0] 020h Reset Value RTC_WRP PKEY[7:0] 024h Reserved Reset Value RTC_SUBS SS[15:0] 028h Reserved Reset Value...
Page 348: Rtc Calendar Date Register (Rtc_Date)
Bit Field Name Description 31:23 Reserved Reserved, the reset value must be maintained AM/PM format. 0:AM format or 24-hour format 1:PM format 21:20 HOT[1:0] Describes the hour tens value in BCD format 19:16 HOU[3:0] Describes the hour units value in BCD format Reserved Reserved, the reset value must be maintained 14:12...
Page 349: Rtc Control Register (Rtc_Ctrl)
Bit Field Name Description Reserved Reserved, the reset value must be maintained DAT[1:0] Describes the date tens value in BCD format DAU[3:0] Describes the date units value in BCD format RTC Control Register (RTC_CTRL) Address offset: 0x08 Reset value: 0x0000 0000 Bit Field Name Description...
Page 350 Bit Field Name Description bit is always read as 0. 0: No effect. 1: Subtracts 1 hour to the current time. AD1H Add 1 hour (summer time change) When this bit is set, 1 hour can be added to the calendar time. This bit is always read as. 0: No effect.
Page 351: Rtc Initial Status Register (Rtc_Initsts)
Bit Field Name Description REFCLKEN RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: Disable RTC_REFIN detection 1: Enable RTC_REFIN detection Note: RTC_PRE.DIVS must be 0x00FF TEDGE Time-stamp event active edge 0: Input rising edge creates a timestamp event 1: Input falling edge creates a timestamp event TSE need to be reset when TEDGE is changed to avoid unwanted RTC_INITSTS.TISF setting.
Page 352 Bit Field Name Description This flag is set to ‘1’ by hardware when a tamper event is detected on the RTC_TAMP1 input pin. This flag can be cleared by software writing 0 TISOVF The time-stamp overflow flag This flag is set to ‘1’by hardware when a time-stamp event happens when TISF bit is set.
Page 353: Rtc Prescaler Register (Rtc_Pre)
Bit Field Name Description INITSF Initialization status flag This flag is set to ‘1’ by hardware when the calendar year field is different from 0 (which is the RTC domain reset state). 0: Calendar has not been initialized 1: Calendar has been initialized SHOPF Shift operation pending flag This flag is set to ‘1’...
Page 354: Rtc Wakeup Timer Register (Rtc_Wkupt)
Bit Field Name Description /(DIVS[14:0]+1) ck_spre ck_apre RTC Wakeup Timer Register (RTC_WKUPT) Address offset: 0x14 Reset value: 0x0000 FFFF Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 WKUPT[15:0] Wake up auto-reload value bits The RTC_INITSTS.WTF flag is set every (WKUPT[15:0] + 1) ck_wut cycles when the RTC_CTRL.WTEN=1.
Page 355: Rtc Alarm B Register (Rtc_Alarmb)
Bit Field Name Description 0: DTU[3:0] represents the date units 1: DTU[3:0] represents week day only. DTT[1:0] is not considered 29:28 DTT[1:0] Describes the date tens value in BCD format 27:24 DTU[3:0] Describes the date units value in BCD format MASK3 Alarm hours mask 0: Hours match...
Page 356: Rtc Write Protection Register (Rtc_Wrp)
Bit Field Name Description 29:28 DTT[1:0] Describes the date tens value in BCD format 27:24 DTU[3:0] Describes the date units value in BCD format MASK3 Alarm hours mask 0: Hours match 1: Hours not match AM/PM notation 0: AM or 24 hours format 1: PM format 21:20 HOT[1:0]...
Page 357: Rtc Shift Control Register (Rtc_Sctrl)
Reset value: 0x0000 0000 Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 SS[15:0] Sub-second value. The value is the counter value of synchronous prescaler. This sub-second value is calculated by the below formula: Sub-second value = (RTC_PRE.DIVS[14:0]-SS)/( RTC_PRE.DIVS[14:0]+1) Note: SS[15:0] can be larger than RTC_PRE.DIVS[14:0] only after the shift operation is finished.
Page 358: Rtc Timestamp Time Register (Rtc_Tst)
Bit Field Name Description Note: RTC_INITSTS.RSYF bit will be cleared when write SUBF[14:0]. When RTC_INITSTS.RSYF=1, the shadow registers have been updated with the shifted time. RTC Timestamp Time Register (RTC_TST) Address offset: 0x30 Reset value: 0x0000 0000 Bit Field Name Description 31:23 Reserved...
Page 359: Rtc Timestamp Sub-Second Register (Rtc_Tsss)
Bit Field Name Description 23:20 YRT[3:0] Describes the year tens value in BCD format 19:16 YRU[3:0] Describes the year units value in BCD format 15:13 WDU[2:0] Describes which Week day 000: Forbidden 001: Monday 111: Sunday Describes the month tens value in BCD format 11:8 MOU[3:0] Describes the month units value in BCD format...
Page 360: Rtc Tamper Configuration Register（Rtc_Tmpcfg
Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained Increase frequency of RTC by 488.5 ppm This feature is intended to be used along with CM[8:0]. When RTCCLK frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is ((512 * CP) –...
Page 361 Bit Field Name Description 0: Not mask tamper 3 event. 1: Mask tamper 3 event. Note: The Tamper 3 interrupt must not be enabled when TP3MF is set. TP3NOE Tamper 3 no erase 0: Backup registers values are erased by Tamper 3 event. 1: Backup registers values are not erased by Tamper 3 event.
Page 362 Bit Field Name Description 0x1: Triggers a tamper event after 2 consecutive samples at the active level. 0x2: Triggers a tamper event after 4 consecutive samples at the active level. 0x3: Triggers a tamper event after 8 consecutive samples at the active level. 10:8 TPFREQ[2:0] Tamper sampling frequency...
Page 363: Rtc Alarm A Sub-Second Register (Rtc_Alrmass)
Bit Field Name Description enabled by setting TPxINTEN. TP1TRG Tamper 1 event trigger edge if TPFLT[1:0] != 00, tamper detection is in level mode: 0: low level trigger a tamper detection event. 1: high level trigger a tamper detection event. if TPFLT = 00, tamper detection is in edge mode: 0: Rising edge trigger a tamper detection event.
Page 364: Rtc Alarm B Sub-Second Register (Rtc_Alrmbss)
RTC Alarm B Sub-second Register (RTC_ALRMBSS) Address offset: 0x48 Reset value: 0x0000 0000 Bit Field Name Description 31:28 Reserved Reserved, the reset value must be maintained 27:24 MASKSSB[3:0] Mask the most significant bit from this bits. 0x0: No comparison on sub seconds for Alarm. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
Page 365: Rtc Backup Registers (Rtc_Bkp(1~20))
Bit Field Name Description 31:1 Reserved Reserved, the reset value must be maintained TYPE RTC_ALARM output type on PC13 0: Open-drain output 1: Push-pull output RTC Backup Registers (RTC_BKP(1~20)) Address offset: 0x50 to 0x9C Reset value: 0x0000 0000 Bit field Name Description 31:0...
Page 366: Independent Watchdog (Iwdg)
15 Independent Watchdog (IWDG) Introduction The N32L40x has built-in independent watchdog (IWDG) and window watchdog (WWDG) timers to solve the problems caused by software errors. The watchdog timer is very flexible to use, which improves the security of the system and the accuracy of timing control. The independent Watchdog (IWDG) is driving by Low-speed internal clock (LSI clock) running at 40 KHz, which will still running event dead loop or MCU stuck is happening.
Page 367: Function Description
Function Description Figure 15-1 Functional Block Diagram Of The Independent Watchdog Module User Program 40KHz IWDG_KEY.KEYV == 0x5555 IWDG_PREDIV.PD IWDG_STS.PVU 4/8/16/32/64/128/256 Counter == 0 IWDG_RELV.REL 12 Bit IWDG Reset 12-bit reload value Down Counter IWDG_STS.CRVU Reload Enable IWDG_KEY.KEYV Note: Watchdog function is in V power supply area, and it can still work normally in RUN, SLEEP, LOW POWER RUN, LOW POWER SLEEP, STOP2and STANDBY modes.
Page 368: Debugging Mode
Debugging Mode ® In debug mode ( Cortex -M4F core stops), IWDG counter will either continue to work normally or stop, depending on DBG_CTRL.IWDG_STOP bit in debug module. If this bit is set to ‘1’, the counter stops. The counter works normally when the bit is ‘0’.
Page 369: Iwdg Configuration Flow
3276.8 6553.6 /128 13107.2 /256 26214.4 IWDG Configuration Flow Software flow: Write 0x5555 to IWDG_KEY.KEYV[15:0] bits to enable write access of IWDG_PREDIV and IWDG_RELV registers. Check IWDG_STS.PVU bit or IWDG_STS.CRVU bit, if they are 0, continue next step. Configure IWDG_PREDIV.PD[2:0] bits to select pre-scale value. Configure IWDG_RELV.REL[11:0] bits reload value.
Page 370: Iwdg Key Register (Iwdg_Key)
IWDG Key Register (IWDG_KEY) Address offset: 0x00 Reset value: 0x00000000 Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 KEYV[15:0] Key value register: only certain value will serve particular function 0xCCCC: Start watch dog counter, does not have any effect if hardware watchdog is enable, (if hardware watchdog is selected, it is not limited by this command word) 0xAAAA: Reload counter with REL value in IWDG_RELV register to prevent reset.
Page 371: Iwdg Reload Register (Iwdg_Relv)
Bit Field Name Description PD[2:0] Pre-frequency division factor Pre-scaler divider: with write access protection when IWDG_KEY.KEYV[15:0] is not 0x5555. The IWDG_STS.PVU bit must be 0 otherwise PD [2:0] value cannot be changed. Divide number is as follow: 000: divider /4 001: divider /8 010: divider /16 011: divider /32...
Page 372 Bit Field Name Description 31:2 Reserved Reserved, the reset value must be maintained. CRVU Watchdog reload value update Reload Value Update: this bit indicates an update of reload value is ongoing. Set by hardware and clear by hardware. Software can only try to change IWDG_RELV.REL[11:0] value when IWDG_KEY.KEYV[15:0] bits’...
Page 373: Window Watchdog (Wwdg)
16 Window Watchdog (WWDG) Introduction The clock of the window watchdog (WWDG) is obtained by dividing the APB1 clock frequency by 4096, and whether the program operation is abnormal is detected through the configuration of the time window. Therefore, WWDG is suitable for precise timing, and is often used to monitor software failures caused by external disturbances or unforeseen logic conditions that cause an application to deviate from its normal operating sequence.
Page 374: Timing For Refresh Watchdog And Interrupt Generation
immediately after enable. The pre-scaler value set by the clock APB1 and WWDG_CFG.TIMERB[1:0] bits determine the decrement speed of the counter. WWDG_CFG.W[6:0] bits set the upper limit of the window. When the down-counter is refreshed before reaching the window register value or after WWDG_CTRL.T6 bit becomes 0, a system reset will be generated.
Page 375: Debug Mode
clock, the maximum counting time and minimum counting time is shown in Table 16-1 (assuming APB1 clock 16 MHz) with calculate equation: �� = �� × 4096 × 2 × (��[6: 0] + 1) �� 1 In which: : WWDG timeout WWDG :APB1 clock interval in ms PCLK1...
Page 376: Wwdg Registers
WWDG Registers WWDG Register Overview Table 16-2 WWDG Register Overview Offset Register WWDG_CTRL T[6:0] 000h Reserved Reset Value TIMERB WWDG_CFG W[6:0] [1:0] 004h Reserved Reset Value WWDG_STS 008h Reserved Reset Value WWDG Control Register (WWDG_CTRL) Address offset : 0x00 Reset value : 0x0000007F Bit Field Name Description...
Page 377: Wwdg Status Register (Wwdg_Sts)
Bit Field Name Description Reserved Reserved, the reset value must be maintained. 31:10 EWINT Early wake-up interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. TIMERB[1:0] Timer base.
Page 378: Analog To Digital Conversion (Adc)
17 Analog To Digital Conversion (ADC) Introduction The 12-bit ADC is a high-speed analog-to-digital converter using successive approximation. It has multiple channels, 19 channels, measuring 16 external and 3 internal signal sources. The A/D conversion of each channel has four execution modes: single, continuous, scan or discontinuous.
Page 379: Function Description
• Interrupt generation − At the end of conversion − At the end of injection conversion − Analog watchdog event • Data alignment with embedded data consistency • Both regular conversions and injection conversions have external triggering options • ADC power requirements: 1.8V to 3. 6V •...
Page 380: Adc Clock
Figure 17-1 Block Diagram of A Single ADC Analog watchdog event Analog Data bus watchdog ADC Interrupt to NVIC Interrupt End of injected conversion generate Data register Injected data registers Regular data register (4 x 16 bits) (16 bits) End of conversion Injected Regular channels...
Page 381: Adc Switch Control
PLL). The HCLK divided clock and system clock are synchronous clock, while the PLL divided clock and system clock are asynchronous clock. The advantage of using a synchronous clock is that there is no uncertainty when triggering the ADC to respond to the trigger.The advantage of using PLL's divider clock is that the ADC's working clock can be handled independently without affecting other modules attached to the HCLK •...
Page 382: Channel Selection
The conversion can be stopped by clearing the ADC_CTRL2.ONbit and placing the ADC in power-off mode. In this mode, the ADC consumes almost no power consumption (just a few μA). Power-down can be checked by polling the ADC_CTRL3.PDRDY bit. When the ADC is disabled, the default mode is power-down. In this mode, as long as the power is on, there is no need to re-calibrate, and the calibration value is automatically maintained in the ADC.
Page 383: Figure 17-3 Adc Channels And Pin Connections
Figure 17-3 ADC Channels and Pin Connections VREFINT: Internal reference voltage , 1.2V(BG) VREFBUFF: Internal reference voltage , 2.048V Internal temperature sensor OPAMP1_OUT is connected to ADC_IN3 OPAMP2_OUT is connected to ADC_IN7 Channel Selection Fast Channel REFINT VREF- Fast Channel ADC_IN1 Fast Channel ADC_IN2...
Page 384: Internal Channel
OP2OUT Internal channels can be converted by injection or regular channels. Note: For the use of V ,please contact Nsing to obtain relevant information. REFBUFF Single Conversion Mode The ADC can enter the single conversion mode by configuring ADC_CTRL2.CTU to 0. In this mode, external triggering(for regular channels or injected channels) or setting ADC_CTRL2.ON=1(for regular channels only) can...
Page 385: Analog Watchdog
Figure 17-4 Timing Diagram ADC_CLK Set ON to 1 ADC power on conversion Start first Start next conversion Next ADC Conversion ADC Conversion Conversion Time （total conv time） ENDC STAB ENDC is set to 0 by software Analog Watchdog The analog watchdog can be enabled on the regular channel by setting ADC_CTRL1.AWDGERCH to 1, or the analog watchdog on the injection channel can be enabled by setting ADC_CTRL1.AWDGEJCH to 1.
Page 386: Scanning Mode
ADC_CTRL1 register control bit Channel AWDGSGLEN AWDGERCH AWDGSGLEN A single Injection or regular channels Scan Mode By configuring ADC_CTRL1.SCAMD to 1, the scan conversion mode can be turned on, and by configuring the four registers ADC_RSEQ1, ADC_RSEQ2, ADC_RSEQ3, ADC_JSEQ, the conversion sequence can be selected, and the ADC will scan and convert all the regular or injected channels.
Page 387: Discontinuous Mode
Figure 17-5 Injection Conversion Delay ADC clock Injected event Latency Note:For the maximum delay value, please refer to the electrical characteristics section in the data manual. Discontinuous Mode Regular channels Configure ADC_CTRL1.DREGCH to 1 to enable the discontinuous mode on the regular channel, obtain the regular sequence by configuring ADC_RSEQ1, ADC_RSEQ2, ADC_RSEQ3, and configure ADC_CTRL1.DCTU[2:0] to control the conversion of n channels each time a trigger signal is generated.
Page 388: Calibration
Only one of injection conversion and regular conversion can be set to discontinuous mode at the same time, and the automatic injection function and discontinuous mode cannot be set at the same time. Calibration To reduce errors, the ADC will have a built-in self-calibration mechanism. Before the A/D conversion, this self- calibration mechanism is used to calculate a calibration factor on each capacitor.
Page 389: Programmable Channel Sampling Time
Table 17-3 Right-align Data The Injection sequence (12bit resolution) SYM SYM SYM The regular sequence (12bit resolution) Table 17-4 Left-aligne Data Injection sequence (12bit resolution) The regular sequence (12bit resolution) Note: When the conversion digits are 10, 8, and 6, refer to the alignment with 12 conversion digits Programmable Channel Sampling Time Specify the number of sampling cycles of ADC in ADC_SAMPTx.SAMPx[2:0], and then the ADC samples the input voltage in the specified sampling cycle.
Page 390: Dma Requests
Table 17-5 ADC Is Used for External Triggering of Regular Channels EXTRSEL[2:0] Trigger source Type TIM1_CC1 event TIM1_CC2 event TIM1_CC3 event Internal signal from the on-chip timer TIM2_CC2 event TIM3_TRGO event TIM4_CC4 event EXTI line 0~15/TIM8_TRGO event External pin/internal signal from on-chip timer SWSTRRCH Software control bit For the injected sequence , the software sets the ADC_CTRL2.EXTJTRIG bit to 1, then the injected channel can use...
Page 391: Temperature Sensor Using Flow
sampling time is 17.1us; when the temperature sensor is not working, the ADC_CTR2.TEMPEN bit can be cleared by software to reduce power consumption. Figure 17-7 is a block diagram of a temperature sensor. The output voltage of the temperature sensor changes linearly with temperature. Different chips will have different offsets in the temperature curve due to different production processes.
Page 392: Adc Interrupt
= empirical value for temperature error compensation (°C) offset Refer to the values of V and Avg_Slope in the electrical characteristics chapter of the datasheet. Note: There is a setting time before the sensor wakes up from the power-off mode to the correct output of VSENSE; there is also a setting time after the ADC is powered on, so in order to shorten the delay, the ADC_CTRL2.TEMPEN and ADC_CTRL2.ON bits should be set at the same time.
Page 393: Adc Status Register (Adc_Sts)
Offset Register Reset Value ADC_JOFFSET1 OFFSETJCH1[11:0] 014h Reserved Reset Value ADC_JOFFSET2 OFFSETJCH2[11:0] 018h Reserved Reset Value ADC_JOFFSET3 OFFSETJCH3[11:0] 01Ch Reserved Reset Value ADC_JOFFSET4 OFFSETJCH4[11:0] 020h Reserved Reset Value ADC_WDGHIGH HTH[11:0] 024h Reserved Reset Value ADC_WDGLOW LTH[11:0] 028h Reserved Reset Value 02Ch ADC_RSEQ1 LEN[3:0]...
Page 394: Adc Control Register 1 (Adc_Ctrl1)
Bit Field Name Description 31:15 Reserved Reserved, the reset value must be maintained JENDCA Any injected channel end of conversion flag This bit is set by hardware at the end of any injection channel conversion and cleared by software. 0: Conversion is not complete; 1: Conversion is complete.
Page 395 AWDG AWDG Reserved Reserved ERCH EJCH AWDG JENDC DCTU[2:0] DJCH DREGCH AUTOJC SCANMD ENDCIEN AWDGCH[4:0] SGLEN GIEN Bit Field Name Description 31:24 Reserved Reserved, the reset value must be maintained AWDGERCH Analog watchdog enable on regular channels This bit is set and cleared by the software. 0: Disables analog watchdog on regular channel.
Page 396: Adc Control Register 2 (Adc_Ctrl2)
Bit Field Name Description 0: Use watchdog on all channels. 1: Use watchdog on single channel. SCANMD Scan mode This bit is set and cleared by the software to enable or disable scan mode. In scan mode, the conversion is made by ADC_RSEQx or the selected channel of the ADC_JSEQ register. 0: Disable scan mode.
Page 397 Bit Field Name Description 31:24 Reserved Reserved, the reset value must be maintained TEMPEN Temperature sensor and V Enable REFINT This bit is set and cleared by the software to enable or disable the temperature sensor and Channel. REFINT 0: Disables the temperature sensor and V REFINT 1: Enable the temperature sensor and V REFINT...
Page 398: Adc Sampling Time Register 1 (Adc_Sampt1)
Bit Field Name Description 0: Start conversion without external events. 1: Use an external event to start the conversion. 14:12 EXTJSEL[2:0] External event select for injected sequence These bits select the External event used to trigger the injected sequence conversion. The triggering configuration of ADC is as follows 000: indicates the TRGO event of timer 1 100: indicates the CC4 event of timer 3...
Page 399: Adc Sampling Time Register 2 (Adc_ Sampt2)
Reset value: 0x0000 0000 Bit Field Name Description 31:24 Reserved Reserved, the reset value must be maintained 23:0 SAMPx[2:0] Channel x sample time selection These bits are used to independently select the sampling time for each channel. The channel selection bit must remain constant during the sampling period.
Page 400: Adc Injected Channel Data Offset Register X (Adc_Joffsetx)(X=1
Bit Field Name Description ADC_SAMPT3.SAMPSEL = 1, the sampling time is set as follows: 000: 1.5 cycles 100: 19.5 cycles 001: 2.5 cycles 101: 61.5 cycles 010: 4.5 cycles 110: 181.5 cycles 011: 7.5 cycles 111: 601.5 cycles ADC Injected Channel Data Offset Register x (ADC_JOFFSETx)(x=1…4) Address offset: 0x14-0x20 Reset value: 0x0000 0000...
Page 401: Adc Watchdog Low Threshold Register (Adc_Wdglow)
ADC Watchdog Low Threshold Register (ADC_WDGLOW) Address offset: 0x28 Reset value: 0x0000 0000 Bit Field Name Description 31:12 Reserved Reserved, the reset value must be maintained 11:0 LTH[11:0] Analog watchdog low threshold These bits define the low thresholds for analog watchdog. ADC Regular Sequence Register 1 (ADC_RSEQ1) Address offset: 0x2C Reset value: 0x0000 0000...
Page 402: Adc Regular Sequence Register 2 (Adc_Rseq2)
ADC Regular Sequence Register 2 (ADC_RSEQ2) Address offset: 0x30 Reset value: 0x0000 0000 Bit Field Name Description 31:30 Reserved Reserved, the reset value must be maintained 29:25 SEQ12[4:0] 12th conversion in regular sequence These bits are software-defined as the number (0 to 18) of the 12th conversion channel in the conversion sequence.
Page 403: Adc Injection Sequence Register (Adc_Jseq)
ADC Injection Sequence Register (ADC_JSEQ) Address offset: 0x38 Reset value: 0x0000 0000 Bit Field Name Description 31:22 Reserved Reserved, the reset value must be maintained 21:20 JLEN[1:0] Injected sequence length These bits are software-defined as the number of channels in the injected channel conversion sequence.
Page 404: Adc Regulars Data Register (Adc_Dat)
Bit Field Name Description 15:0 JDAT[15:0] Injected data for conversions These bits are read-only and contain the conversion results of the injected channel. The data is left- aligned or right-aligned ADC Regulars Data Register (ADC_DAT) Address offset: 0x4C Reset value: 0x0000 0000 Reserved DAT[15:0] Name...
Page 405: Adc Calibration Factor (Adc_Calfact)
ADC Calibration Factor (ADC_CALFACT) Address offset: 0x54 Reset value: 0x0000 0000 Bit Field Name Description 31:23 Reserved Reserved, the reset value must be maintained 22:16 CALFACTD[6:0] Calibration factors in differential mode This bit can be written by hardware or software After the differential input calibration is complete, the hardware will update it according to the calibration coefficient.
Page 406 Bit Field Name Description 31:12 Reserved Reserved, the reset value must be maintained VBATMEN Vbat monitor enable 0: Disable 1: Enable DPWMOD Deep power mode 0: When the ADC is disabled, the ADC enters low power mode 1: When the ADC is disabled, the ADC enters deep sleep mode JENDCAIEN Interrupt enable for any injected channels This bit is set and cleared by the software to enable/disable the injection channel conversion end...
Page 407: Adc Sampling Time Register 3 (Adc_Sampt3)
Bit Field Name Description 11: 12-bits ADC Sampling Time Register 3 (ADC_SAMPT3) Address offset: 0x5C Reset value: 0x0000 0000 Bit Field Name Description 31:4 Reserved Reserved, the reset value must be maintained SAMPSEL Sample Time Selection When SAMPSEL = 0, the value of SAMPx[2:0] is set as follows: 000: 1.5 cycles 100: 41.5 cycles 001: 7.5 cycles...
Page 408: Digital To Analog Conversion (Dac)
18 Digital To Analog Conversion (DAC) Introduction DAC is a digital/analog converter, mainly digital input, voltage output.DAC data can be 8-bit or 12-bit and supports DMA functionality.When the DAC is configured in 12-bit mode, the DAC data can be right-aligned or left- aligned.When the DAC is configured in 8-bit mode, the DAC data can be right-aligned.The DAC output channel has 1, with independent converter.VREF+ is used as the DAC reference voltage through the pin input to make the DAC conversion data more accurate.
Page 409: Table 18-1 Dac Pins
Figure 18-1 Block Diagram Of A DAC Channel EXTI_9 DAC CTRL register Trigger source Control logic DMA request DAC alignment data holding DATO register register VDDA VSSA VREF+ Table 18-1 DAC Pins Name Description Type The positive reference voltage used by the DAC, Input, analog reference voltage REF+ 2.4V ≤...
Page 410: Dac Function Description And Operation Description
to the output of the DAC. DAC Function Description And Operation Description DAC Enable Powering on the DAC can be done by configuring DAC_CTRL. CHEN = 1. It takes some time for t to open WAKEUP the DAC. DAC Output Buffer. By configuring DAC_CTRL.BEN to disable or enable the output buffer of DAC, if the output buffer is enable, the output impedance is reduced, the driving ability is enhanced, and the external load can be driven without the external operational amplifier.
Page 411: Dac Trigger
Figure 18-2 Data Register of Single DAC Channel Mode 8-bit right aligned 12-bit left aligned 12-bit right aligned DAC Trigger Configure DAC_CTRL. TEN = 1 can enable external trigger of DAC, and DAC_CTRL.TSEL[2:0] is configured to select an external triggering event as the external triggering source for the DAC. Table 18-2 DAC External Trigger Trigger source Type...
Page 412: Dac Conversion
DAC Conversion If DAC trigger is enable, the data in the DAC alignment data hold register will be transferred to the DAC_DATO register after three APB1 cycles according to the selected trigger event when the hardware trigger occurs. When the software trigger occurs, the data in the DAC alignment data hold register is transferred to the DAC_DATO register after one APB1 cycle.If trigger is not enabled, data in the DAC alignment data hold register is automatically transferred to the DAC_DATO register after one APB1 cycle.
Page 413: Noise Generation
Noise Generation DAC can generate noise, by configuring DAC_CTRL.WEN[1:0] to "01" to turn on the noise function, by configuring DAC_CTRL.MASEL[3:0] to select which bits of the linear feedback shift register (LFSR) are masked, the value of LFSR is added to the value of the DAC alignment data holding register and written to the DAC_DATO register (overflow bits are discarded).
Page 414: Triangular Wave Generation
Figure 18-5 DAC Conversion with LFSR Waveform Generation (enable software trigger) APB1_CLK SWTRIG 0x00 DACCHxD DATOx 0xD55 0xAAA Note: The DAC is configured to trigger to generate noise. Triangular Wave Generation The DAC can generate a triangle wave. The triangle wave function can be turned on by configuring DAC_CTRL.WEN[1:0] as "10", and the amplitude of the triangle wave can be selected by configuring DAC_CTRL.MASEL[3:0].
Page 415: Dac Register
Figure 18-6 Triangle Wave Generation of DAC ADC_CTRL.MAS EL[3:0]+DAC aligned data holding register reference increase decrease DAC aligned data holding register reference Figure 18-7 DAC Conversion With Trigonometry Generation (Enable Software Trigger) APB1_CLK 0xABE DACCHD DATO 0xABE 0xABF 0xAC0 SWTRIG Note: 1.
Page 416: Dac Control Register (Dac_Ctrl)
Offset Register Reset Value DAC_12DRCH DACCHD[11:0] 008h Reserved Reset Value DAC_12DLCH DACCHD[11:0] 00Ch Reserved Reserved Reset Value DAC_8DRCH DACCHD[7:0] 010h Reserved Reset Value 02Ch DAC_DATO DACCHDO[11:0] Reserved Reset Value DAC Control Register (DAC_CTRL) Offset address: 0x00 Reset value: 0x0000 0000 Bit Field Name Description...
Page 417: Dac Software Trigger Register (Dac_Sottr)
Bit Field Name Description 00: Disable noise and triangle wave 01: Enable the noise function 1x: Enables the triangle wave function TSEL[2:0] DAC triggers selection. This bit is used for selection of DAC external triggers. 000: TIM6 TRGO event 001: TIM8 TRGO event 010: TIM7 TRGO event 011: TIM5 TRGO event 100: TIM2 TRGO event...
Page 418: Bit Right Aligned Data Hold Register For Dac (Dac_Dr12Ch)
Bit Field Name Description 0: disables the DAC software trigger. 1: enable the DAC software trigger. Note: After the alignment data hold register transfers data to the DAC_DATO register, this bit will be cleared by the hardware after an APB1 clock. 12 Bit Right Aligned Data Hold Register For DAC (DAC_DR12CH) Offset address: 0x08 Reset value: 0x0000 0000...
Page 419: Dac Data Output Register (Dac_Dato)
Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. DACCHD[7:0] DAC 8 bits right aligned data The bits are configured by the software and the DAC converts the data. DAC Data Output Register (DAC_DATO) Offset address: 0x2C Reset value: 0x0000 0000 Reserved Reserved...
Page 420: Comparator (Comp)
19 Comparator (COMP) The COMP module is used to compare the analog voltages of two inputs and output high/low levels based on the comparison result. When "INP" input voltage is higher than "INM" input voltage, the comparator output are high level, when "INP"...
Page 421: Comp Features
The second character in the 8-bit code of the last line of the chip printed in the factory settings is not “B”The second character in the 8-bit code of the last line of the chip printed in the factory setting is “B” COMP Features •...
Page 422: Comp Working Mode
• Configure the filter sampling frequency (for timer applications, sampling frequency should be greater than 5MHz) • Enable COMPx_FILC.FILEN filter • Enable COMPx_CTRL.EN on the comparator Note: For the above steps, the filter should be enabled first and then the comparator should be enabled. The comparator should be enabled after the filtering (if enabled) is configured and enabled.
Page 423: Interrupt
(2): The selection of the comparator's PA1/DAC1 is done by configuring COMP1_CTRL.INPDAC The comparator INM pins have the following configuration. INMSEL COMP1 COMP2 Float Float DAC1/PA4 VREF_VC1 DAC1/PA4 VREF_VC2 VREF_VC2 Note: DAC1/PA4, indicating that the output pin of DAC1 is PA4 Comparator output TRIG signal has the following interconnection.
Page 424: Comp Register
comparator interrupt is generated when COMPx_CTRL.OUT is set to 1 by hardware. COMP Register COMP Register Overview Table 19-1 COMP Register Overview Offset Register COMP_INTEN 000h Reserved Reset Value COMP_LPCKSEL 004h Reserved Reset Value COMP_WINMODE 008h Reserved Reset Value COMP_LOCK 00Ch Reserved Reset Value...
Page 425: Comp Interrupt Enable Register (Comp_Inten)
Offset Register Reset Value COMP2_OSEL 02Ch Reserved Reset Value COMP_VREFSCL 030h Reserved Reset Value COMP_TEST 034h Reserved Reset Value COMP_INTSTS 038h Reserved Reset Value COMP Interrupt Enable Register (COMP_INTEN) Address offset : 0x00 Reset value : 0x0000 0000 Bit Field Name Description 31:2...
Page 426: Comp Window Mode Register (Comp_Winmode)
Reset value : 0x0000 0000 Bit Field Name Description 31:1 Reserved Reserved, the reset value must be maintained LPCKSEL Comparator clock select 0: Configure this bit to 0 in normal mode, use PCLK1 clock; 1: Configure this bit to 1 during STOP2 or low power operation, using a 32 KHz clock. COMP Window Mode Register (COMP_WINMODE) Address offset : 0x08 Reset value : 0x0000 0000...
Page 427: Comp Control Register (Comp1_Ctrl)
Bit Field Name Description 31:3 Reserved Reserved, the reset value must be maintained CMP2LK This bit is write-once. It is set by software. It can only be cleared by a system reset. If set it causes COMP2_ CTRL register to be read-only. 0: COMP2_ CTRL is read-write.
Page 428 Bit Field Name Description 10: Medium hysteresis 11: High hysteresis This bit is used to invert the comparator 1 output. 0: Output is not inverted 1: Output is inverted 12:9 OUTTRG[3:0] These bits select which Timer input must be connected with the comparator1 output. 0000：Reserved；...
Page 429: Comp Filter Register (Comp1_Filc)
Bit Field Name Description 100：PB5； 101：PD4； 110：VREF_VC1； 111：VREF_VC2。 This bit switches COMP1 ON/OFF. 0: Comparator disabled 1: Comparator enabled COMP Filter Register (COMP1_FILC) Address offset : 0x14 Reset value : 0x0000 0000 Bit Field Name Description 31:11 Reserved Reserved, the reset value must be maintained 10:6 SAMPW[4:0] Filter sampling window size, sampling window = SAMPW + 1.
Page 430: Comp Control Register (Comp2_Ctrl)
Bit Field Name Description System clock divider = CLK_PRE_CYCLE + 1, e.g. 0: Every cycle 1: Every 2 cycle 2: Every 3 cycle … COMP Control Register (COMP2_CTRL) Address offset : 0x20 Reset value : 0x0000 0000 Bit Field Name Description 31:22 Reserved...
Page 431: Comp Filter Register (Comp2_Filc)
Bit Field Name Description 0110：TIM4_IC1； 0111：TIM4_OCrefclear； 1000：TIM5_IC1； 1001：TIM8_IC1； 1010：TIM8_OCrefclear； 1011：TIM9_IC1； 1100：TIM9_OCrefclear； 1101：TIM8_BKIN； 1110：TIM1_BKIN + TIM8_BKIN； 1111：LPTIM_ETR。 INPSEL[3:0] Comparator 2 non-inverting input selection. 0000 to 0111：floating； 1000：PA1(window mode)/DAC1/PA4(window mode && COMP1_CTRL1.INPDAC=1); 1001：PA3； 1010：PA6； 1011：PA7； 1100：PA11； 1101：PA15； 1110：PB7； 1111：PD7。 Reserved Reserved, the reset value must be maintained INMSEL[2:0] These bits allows to select the source connected to the inverting input of the comparator 2.
Page 432: Comp Filter Frequency Division Register (Comp2_Filp)
Bit Field Name Description 31:11 Reserved Reserved, the reset value must be maintained 10:6 SAMPW[4:0] Filter sampling window size, sampling window = SAMPW + 1. THRESH[4:0] The filter threshold is set. At least the sampling threshold of the opposite state in the sample window can change the output state.
Page 433: Comp Reference Voltage Register (Comp_Vrefscl)
Bit Field Name Description 31:1 Reserved Reserved, the reset value must be maintained CMP2XO Bit select to choose COPM2 output or the XOR output(comparison of COMP1&2) outputs 0: COMP2 Output 1: XOR(comparison) output between results of COMP1 and COMP2 COMP Reference Voltage Register (COMP_VREFSCL) Address offset : 0x30 Reset value : 0x0000 0000 Bit Field...
Page 434: Comp Interrupt Status Register (Comp_Intsts)
Bit Field Name Description 31:1 Reserved Reserved, the reset value must be maintained Comparator test enable: 0: disable 1: enable COMP Interrupt Status Register (COMP_INTSTS) Address offset : 0x38 Reset value : 0x0000 0000 Bit Field Name Description 31:2 Reserved Reserved, the reset value must be maintained COMP2IS This bit indicate the interrupt status of COMP2,write 0 to clear.
Page 435: Operational Amplifier (Opamp)
20 Operational Amplifier (OPAMP) The OPAMP module can be flexibly configured, suitable for applications such as independent operational amplifier(PGA) mode and follower mode.OPAMP has an input range of 0V to VDDA and an output range of 0.15V to VDDA-0.15V. Main Features •...
Page 436: Opamp Working Mode
Figure 20-1 Block Diagram of OPAMP1 and OPAMP2 Connection Diagram DAC1/PA4 ADC1 Channel3 OPAMP1 PB14 PD13 OPAMP2 ADC1 Channel7 OPAMP OperatingMode External Amplification Mode of OPAMP The external amplification refers to the amplification factor mode is determined by the connected resistance and capacitance.
Page 437: Opamp Follow Mode
Figure 20-2 OPAMP External Amplification Mode OPAMP Follow Mode In follow mode, the voltage is directly follow input, the VMSEL terminal must be directly connected to the OPAMP output port. Opamp_cs. MOD = 2b’11 is the internal follower function, OPAMPx_CS. VPSSEL or OPAMPx_CS. VPSEL selects the positive end input, OPAMPx_CS.
Page 438: Opamp Internal Gain (Pga) Mode
Figure 20-3 Follow Mode OPAMP Internal Gain (PGA) Mode The programming gain amplifier (PGA)mode amplifies the input voltage through a built-in resistor feedback network. OPAMPx_CS. MOD = 2b’10 is a PGA function that supports gain of 2/4/8/16/32. OPAMPx_CS. VMSSEL or OPAMPx_CS.
Page 439: Opamp With Filtered Internal Gain Mode
Figure 20-4 Internal Gain Mode Programming Gain Amplifier (PGA) Mode with Filtering In this mode, the amplification voltage is adjustable, supporting gains of 2/4/8/16/32, and the OPAMPx_CS.VPSSEL or OPAMAPx_CS.VPSEL is set to be connected to the external pin, and the negative terminal of OPAMP can be connected to components such as capacitors.
Page 440: Opamp Calibration
OPAMP Calibration The chip has been calibrated before delivery. Users can calibrate the chip again according to the actual environment. OPAMP Independent Write Protection By configuring the OPAMP_LOCK register, the write protection of OPAMP can be set independently. Once the write protection is set, the software cannot write to the corresponding OPAMP register.
Page 441: Opamp Control Status Register (Opamp1_Cs)
Offset Register OPAMP_LOCK 020h Reserved Reset Value OPAMP Control Status Register (OPAMP1_CS) Offset address: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:22 Reserved Reserved, the reset value must be maintained. 21:19 VPSSEL[2:0] OPAMP non-inverted input secondary selection 000: VP0 (PA1); 001: VP1 (PA5);...
Page 442: Opamp Control Status Register (Opamp2_Cs)
Bit Field Name Description Reserved Reserved, the reset value must be maintained. CALON Calibration mode enabled 0: Normal mode; 1: Calibration mode. 10:8 VPSEL[2:0] OPAMP non-inverted input selection 000: VP0 (PA1); 001: VP1 (PA5); 010: VP2 good-sized dining room (PA4); 011: VP3 (PA7);...
Page 443 Bit Field Name Description 31:25 Reserved Reserved, the reset value must be maintained. TIMSRCSEL Primary/secondary input port switch clock source selection Zero: TIM1_CC6; 1: TIM8_CC6. 23:22 Reserved Reserved, the reset value must be maintained 21:19 VPSSEL[2:0] OPAMP non-inverted input secondary selection 000: VP0 (PA7);...
Page 444: Opamp Lock Register (Opamp_Lock)
Bit Field Name Description 10: VM2 (PA5); 11: VM float (for internal PGA(no filter ) mode and follow mode). PGAGAN[2:0] Operational Amplifier Programmable amplifier Gain Value 000: internal PGA gain 2; 001: Internal PGA gain 4; 010: Internal PGA gain 8; 011: Internal PGA gain 16;...
Page 445: Liquid Crystal Display Controller (Lcd)
21 Liquid Crystal Display Controller (LCD) Introduction The LCD controller is suitable for monochrome passive Segment LCD, with a maximum of 8 common terminals (COM) and 44 Segment terminals (SEG), the specific number of terminals depends on the package of pin, refer to the data manual for details.The Segment LCD consists of a number of segments that can be turned on or off.
Page 446: Functional Block Diagram
Functional Block Diagram Figure 21-1 LCD Controller Block Diagram Frequency generator RTCSEL[1:0] LCDCLK PRES[3:0] ck_pres DIV[3:0] ck_div SEG[43:0] VSEL LCDEN COM[7:4] Interrupt HDEN CONTRAST[2:0] SEG[43:40] BIAS[1:0] SEG[31:28] SEG[43:40] COM[3:0] SEG[39:0] Analog Switch Array 421 / 652...
Page 447: Functional Description
Functional Description The LCD controller provides a fully configurable interface to support various monochrome passive LCD displays, with flexible configuration of frame frequency. Each COM has same waveforms, but different phases. The number of COM ports depends on the duty cycle configuration, with the same waveform in a frame, but only one COM is active in each phase.
Page 448: Common End Driver
32.768kHz 31.03Hz 32.768kHz 30.12Hz 32.768kHz 1088 static 30.12Hz 32.768kHz 102.4Hz 32.768kHz 102.4Hz 32.768kHz 101.14Hz 32.768kHz 102.4Hz 32.768kHz static 102.4Hz 1.00MHz 1216 102.8Hz 1.00MHz 2432 102.8Hz 1.00MHz 3328 100.16Hz 1.00MHz 4864 102.8Hz 1.00MHz 9728 static 102.8Hz Note: in order to achieve low power consumption and high refresh rate, the frame frequency range must be within 40Hz to 100Hz.
Page 449: Figure 21-2 Odd-Even Frames Example(1/4 Duty Cycle, 1/3 Bias)
Figure 21-2 Odd-even Frames Example(1/4 duty cycle, 1/3 bias) odd frame even frame Phase Phase Phase Phase Phase Phase Phase Phase VLCD 2/3VLCD 1/3VLCD Active Active Inactive Inactive Active Active Inactive Inactive VLCD 2/3VLCD 1/3VLCD Active Inactive Inactive Inactive Active Inactive Inactive Inactive...
Page 450: Segment Driver
Figure 21-3 Static Duty Cycle Example 1 frame 1/1VLCD PIN COM0 0/1VLCD Line connection 1/1VLCD SEG7 PIN SEG0 0/1VLCD SEG0 SEG6 SEG5 1/1VLCD PIN SEG1 SEG1 SEG3 0/1VLCD COM0 SEG2 SEG4 1/1VLCD COM0-SEG0 Activated pixel 0/1VLCD -1/1VLCD COM0-SEG1 Inactivated pixel 0/1VLCD Eight to One Multiplexer Selector When COM[0] is activated, the COM driver module drives an eight-to-one multiplexer (refer to the LCD controller...
Page 451: Figure 21-4 1/2 Duty Cycle, 1/2 Bias
Figure 21-4 1/2 Duty Cycle, 1/2 Bias 1 frame 2/2VLCD PIN COM0 1/2VLCD 0/2VLCD Line connection 2/2VLCD 1/2VLCD PIN COM1 0/2VLCD SEG0 COM1 2/2VLCD SEG0 PIN SEG0 SEG3 0/2VLCD SEG1 SEG2 2/2VLCD SEG1 PIN SEG1 0/2VLCD COM0 SEG2 SEG3 2/2VLCD 1/2VLCD COM0-SEG0 Activated pixel...
Page 452: Figure 21-5 1/3 Duty Cycle, 1/3 Bias
Figure 21-5 1/3 Duty Cycle, 1/3 Bias 1 frame 3/3VLCD 2/3VLCD PIN COM0 1/3VLCD 0/3VLCD 3/3VLCD 2/3VLCD PIN COM1 1/3VLCD 0/3VLCD 3/3VLCD 2/3VLCD Line connection PIN COM2 1/3VLCD 0/3VLCD SEG1 COM2 3/3VLCD 2/3VLCD SEG0 SEG2 PIN SEG0 1/3VLCD SEG1 0/3VLCD SEG2 SEG0 COM1...
Page 453: Figure 21-6 1/4 Duty Cycle, 1/3 Bias
Figure 21-6 1/4 Duty Cycle, 1/3 Bias 1 frame 3/3VLCD 2/3VLCD PIN COM0 1/3VLCD 0/3VLCD 3/3VLCD 2/3VLCD PIN COM1 1/3VLCD 0/3VLCD Line connection 3/3VLCD 2/3VLCD PIN COM2 1/3VLCD SEG1 COM3 0/3VLCD 3/3VLCD SEG0 SEG1 2/3VLCD COM2 PIN SEG0 1/3VLCD SEG0 0/3VLCD SEG0 SEG1...
Page 454: Blink Function
Figure 21-7 1/8 Duty Cycle, 1/4 Bias 1 frame 4/4VLCD 3/4VLCD PIN COM0 2/4VLCD 1/4VLCD 0/4VLCD 4/4VLCD 3/4VLCD PIN COM1 2/4VLCD 1/4VLCD 0/4VLCD Line connection 4/4VLCD 3/4VLCD COM7 PIN COM2 2/4VLCD SEG0 1/4VLCD COM6 0/4VLCD SEG0 SEG0 SEG0 COM5 4/4VLCD COM4 3/4VLCD COM3...
Page 455: Voltage Generator And Contrast Control
Table 21-2 Blink Frequency Configure Example ck_div(LCDCLK = 32.768kHz) BLINKF[2:0] 32Hz 64Hz 128Hz 256Hz 4.0Hz 4.0Hz 4.0Hz 0.5Hz 4.0Hz 0.25Hz 0.5Hz 0.25Hz 0.5Hz 0.25Hz 0.5Hz 0.25Hz Voltage Generator and Contrast Control Power supply selection Configure LCD power from internal step-up converter or external voltage through LCD_CTRL.VSEL. When internal step-up converter is selected, the contrast ratio can be controlled in the range of V to V through...
Page 456: Figure 21-8 Lcd Drive Voltage Control
levels change. The shorter the driving time, the lower the power consumption, but the display with high internal resistance needs a longer driving time to obtain a good contrast ratio. For LCD_FCTRL.HDEN bit: If the LCD_FCTRL.HDEN bit and the LCD_FCTRL.PULSEON[2:0] bit are cleared, the HDEN switch is opened; if the LCD_FCTRL.HDEN bit is cleared and the LCD_FCTRL.PULSEON[2:0] bit is not 0, the HDEN switch closed during the number of pulses defined in the LCD_FCTRL.PULSEON[2:0] bits;...
Page 457: Double Buffer Display
Voltage buffer mode When the LCD_CTRL.BUFEN bit is configured (configured when LCD_CTRL.LCDEN is disabled) to enable the voltage output buffer, the high-value resistor network R generates an intermediate voltage to reduce power consumption, and the low-value resistor network R is automatically disabled(ignore LCD_FCTRL.HDEN bit or LCD_FCTRL.PULSEON bit configuration).
Page 458: Table 21-3 Com And Seg Pins Mapping Table
If the duty cycle mode is not 1/8 and the device has few external pins, you can set the LCD_CTRL.MUXSEG bit to remap 4 SEG pins. When LCD_CTRL.MUXSEG=1, the output pin SEG[43:40] has the same function as SEG[31:28], while the original SEG[31:28] pin is unavailable. The relationship between COM and SEG functions and duty cycle and pin remapping configuration is shown in Table 21-3.
Page 459 Configure bits SEG × COM LCD module function MCU output pins DUTY MUXSEG 48 PIN 64PIN 80 PIN SEG[27:0] SEG[27:0] SEG[43:40]/ COM[7:4] Not available COM[3:0] COM[3:0] 20×4 —— —— SEG[32], SEG[35] SEG[32], SEG[35] SEG[31:28] Not available SEG[17:0] SEG[17:0] SEG[43:40]/ COM[7:4] SEG[43:40] COM[3] Not used...
Page 460 Configure bits SEG × COM LCD module function MCU output pins DUTY MUXSEG 48 PIN 64PIN 80 PIN SEG[43:40]/ COM[7:4] SEG[43:40] COM[3:2] Not used COM[1:0] COM[1:0] —— —— 44×2 SEG[39:32] SEG[39:32] SEG[31:28] SEG[31:28] SEG[27:0] SEG[27:0] SEG[43:40]/ COM[7:4] SEG[31:28] COM[3:2] Not used COM[1:0] COM[1:0] ——...
Page 461: Working Process
Configure bits SEG × COM LCD module function MCU output pins DUTY MUXSEG 48 PIN 64PIN 80 PIN SEG[43:40]/ COM[7:4] SEG[31:28] COM[3:1] Not used COM[0] COM[0] —— —— 40×1 SEG[39:32] SEG[39:32] SEG[31:28] Not used SEG[27:0] SEG[27:0] Not available SEG[43:40]/ COM[7:4] SEG[43:40] COM[3:1] Not used...
Page 462: Low Power Mode
Write the default data to LCD_RAM, and set LCD_STS.UDR by software; After configuring the frame frequency and contrast, set LCD_CTRL.LCDEN to enable the LCD module; If you need to adjust the contrast, you can modify LCD_FCTRL.PRES[3:0], LCD_FCTRL.DIV[3:0], LCD_FCTRL.CONTRAST[2:0], LCD_FCTRL.PULSEON[2:0], LCD_FCTRL.DEAD[2:0] LCD_FCTRL.HDEN bit;...
Page 463 Offset Register LCD_FCTRL 004h Reserved Reset Value LCD_STS 008h Reserved Reset Value LCD_CLR 00Ch Reserved Reset Value LCD_RAM1_COM0 014h Reset Value LCD_RAM2_COM0 018h Reserved Reset Value LCD_RAM1_COM1 01Ch Reset Value LCD_RAM2_COM1 020h Reserved Reset Value LCD_RAM1_COM2 024h Reset Value LCD_RAM2_COM2 028h Reserved Reset Value...
Page 464: Lcd Control Register (Lcd_Ctrl)
Offset Register Reset Value LCD Control Register (LCD_CTRL) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:9 Reserved Reserved, the reset value must be maintained. BUFEN Voltage output buffer enable This bit is used to enable or disable high drive capability voltage output. 0: Disable.
Page 465: Lcd Frame Control Register (Lcd_Fctrl)
Bit Field Name Description be pulled down to VSS after disable. 0: Disable. 1: Enable. Note: LCD_CTRL.VSEL, LCD_CTRL.DUTY, LCD_CTRL.BIAS, LCD_CTRL.MUXSEG and LCD_CTRL.BUFEN are write protected after LCD_CTRL.LCDEN is enabled. If you want to modify these bits, you must disable the LCD controller first.
Page 466 Bit Field Name Description 010: ck_div / 32; 011: ck_div / 64; 100: ck_div / 128; 101: ck_div / 256; 110: ck_div / 512; 111: ck_div / 1024. 12:10 CONTRAST[2:0] Contrast control These bits specify the maximum V voltage (independent of the VDD), which ranges from 2.60V to 3.58V.
Page 467: Lcd Status Register (Lcd_Sts)
Bit Field Name Description 0: Disable. 1: Enable. Reserved Reserved, the reset value must be maintained. SOFIE Start of frame interrupt enable This bit is set and cleared by the software. 0: Disable. 1: Enable. HDEN High Drive Enable (High drive enable) This bit enables low resistance voltage divider.
Page 468: Lcd Clear Register (Lcd_Clr)
Bit Field Name Description The bit is set to 1 by hardware.If LCD_FCTR.UDDIE set to 1, a UDD interrupt is generated. The bit is cleared when LCD_CLR.UDDCLR bit is written to 1.Setting has a higher priority than clearing. 0: No event. 1: Update display request is complete.
Page 469: Lcd Display Memory Register (Lcd_Ram1_Comx X = 0
LCD Display Memory Register (LCD_RAM1_COMx x = 0...7) Address offset: 0x14 + x*8 Reset value: 0x0000 0000 Bit Field Name Description 31:0 Display memory LCD_RAM1_COMx (x = 0...7) Pixel bits (y = 0...31), each bit corresponds to a pixel. The pixel value 1 represents activity, and 0 represents inactivity.
Page 470 Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. Display memory LCD_RAM2_COMx (x = 4...7) Pixel bits (y = 0...7), each bit corresponds to a pixel. The pixel value 1 represents activity, and 0 represents inactivity. 445 / 652...
Page 471: C Interface
22 I C Interface Introduction The I C (Inter-Integrated Circuit) bus is a widely used bus structure, it has only two bidirectional lines: thedata bus SDA and clock bus SCL. All devices compatible with I C bus can communicate directly with each other through I bus with these two lines.
Page 472: Function Description
− Acknowledge (ACK) fail after address/data transfer − Error start or stop condition detected − Overrun or underrun when clock extending is disable • Two interrupt vectors: − 1 interrupt for address/data communication success − 1 interrupt for an error •...
Page 473: Software Communication Process
If the clock stretching is allowed, the SCL line is pulled down which can be avoided the overload error during receiving and the under load error during transmission. For example, when in the transmission mode, if the transmit data register is empty and the byte transmit end bit is set (I2C_STS1.TXDATE = 1, I2C_STS1.BSF = 1), the I C interface keeps the clock line low before transmission to wait for the software to read STS1 and write the data into the data register (both buffer and shift register are empty);...
Page 474: Figure 22-1 I 2 C Functional Block Diagram
Figure 22-1 I C Functional Block Diagram Data Data register Shift register GPIO control Own address register Comparator calculation Dual address register PEC register Clock Clock Control Register GPIO control Control Register Control SMBALERT logic Status Register Interrupts DMA requests Note: in SMBus mode, SMBALERT is an optional signal.
Page 475: Clock Synchronization
concurrently when the bus is inactive. So some mechanisms are needed to grant a master the access to the bus. This process is generally named Clock Synchronization and Arbitration. C module has two key features: • SDA and SCL are drain open-drain configurations, and the signal "wire-and" logic is realized through an external pull-up resistor.
Page 476 or a receiver. The I C host is responsible for generating the start bit and the end bit in order to start and end a transmission. And is responsible for generating the SCL clock. The I C module supports 7-bit and 10-bit addresses, and the user can configure the address of the I C slave through software.
Page 477: Figure 22-3 Slave Transmitter Transfer Sequence Diagram
6. During the sending of the second last byte, the software writes the last data to the I2C_DAT register to clear the I2C_STS1.TXDATE flag bit, and then the I2C_STS1.TXDATE status is no longer concerned. I2C_STS1.TXDATE bit is set after the second last byte is sent until the stop end bit is detected. 7.
Page 478: Figure 22-4 Slave Receiver Transfer Sequence Diagram
reading I2C_STS1 register first and then I2C_STS2 register. Once the I2C_STS1.ADDRF bit is cleared,The I slave starts to receive data from the I2C bus. 3. When the first byte is received, the I2C_STS1.RXDATNE bit (the received data is not empty) is set to 1 by hardware.
Page 479 bus through the start bit, the device enters the master mode. When sending data to I C bus in master mode, the software should operate as follows: First, enable the I C peripheral clock, and configure the clock-related registers in I2C_CTRL1 to ensure the correct I C timing.
Page 480: Figure 22-5 Master Transmitter Transfer Sequence Diagram
I2C_STS1.TXDATE bit is set to 1, the software can write a byte to the I2C_DAT register. In the process of sending the penultimate byte, the software writes the last byte of data to I2C_DAT to clear the I2C_STS1.TXDATE flag bit. After that, there is no need to care about the status of the I2C_STS1.TXDATE bit. The I2C_STS1.TXDATE bit will be set after the penultimate byte is sent, and will be cleared when the stop bit (STOP) is sent.
Page 481 (1) EV5, EV6, EV9, EV8_1 and EV8_2 event prolonged the low SCL time until the end of the corresponding software sequence. (2) The software sequence of EV8 must be completed before the end of the current byte transfer. (3) When I2C_STS1.TXDATE or I2C_STS1.BSF bit is set, stop condition should be arranged when EV8_2 occurs. C master receiving mode In master mode, software receiving data from I C bus should follow the following steps:...
Page 482: Figure 22-6 Master Receiver Transfer Sequence Diagram
the I2C_STS1.ADDRF bit again by reading I2C_STS1 and I2C_STS2 in sequence. After sending the address and clearing the I2C_STS1.ADDRF bit, the I C interface enters the host receiving mode. In this mode, the I C interface receives data bytes from the SDA line and sends them to the DAT register through the internal shift register.
Page 483: Error Conditions Description
5. EV7_1: I2C_STS1.RXDATNE =1, read the DAT register to clear this event. Set I2C_CTRL1.ACKEN=0 and I2C_CTRL1.STOPGEN=1. 6. EV9: I2C_STS1.ADDR10F=1, reading STS1 and then writing to the DAT register will clear this event. Notes: (1) If a single byte is received, it is NA. (2) EV5, EV6, and EV9 events extend the low level of SCL until the corresponding software sequence ends.
Page 484: Dma Application
When I C interface is receiving data (I2C_STS1.RXDATNE=1, data have received in register), and I2C_DAT register still have previous byte has not been read, it will occurs an overrun error. In this situation, the last received data is discarded. And software should clear I2C_STS1.RXDATNE bit, transmitter retransmit last byte. When I C interface is sending data (I2C_STS1.TXDATE=1, new data have not sending to register), and I2C_DAT register still empty, it will occurs an underrun error.
Page 485: Receive Process
Note: if DMA is used for transmission, do not set I2C_CTRL2.BUFINTEN bit. Receive process DMA mode can be enabled by setting I2C_CTRL2.DMAEN bit. When data byte is received,DMA will send I C data to storage area, set DMA channel for I C reception, the following steps must be opreate: In DMA_PADDRx register set the address of the I2C_DAT register.
Page 486: Smbus
SMBus Introduction The System Management Bus(SMBus or SMB) is a simple single-ended two-wire bus structure. Using SMBus can communicate with other device or other parts of the system, it able to commnicate with multiple devices without other independent control wire. SMBus is a derivate of the I C bus and provides a control bus for system and power management related tasks.
Page 487: Bus Protocol
Bus protocol SMBus specification includes eight bus protocols. If user wants browse the details on protocols or SMBus address types,it can refer to the SMBus specification v2.0(http://smbus.org/specs/). User’s software can device what protocols are implemented. Every packet through the SMBus complies with the SMBus protocol predefined format. SMBus is a subset of the data transfer format of I C specification.
Page 488: Debug Mode
is low,it means host will read ARA again. The host can periodically access the ARA when the SMBALERT signal is not used. SMBus communication process The communication process on SMBus is similar to that on I C.To use the SMBus mode, you need to configure SMBus specific registers in the program, respond and process SMBus specific flag, and implement the upper-layer protocols described in the SMBus manual.
Page 489: I2C Register Description
Interrupt Function Interrupt Event Event Flag Set Control Bit SMBus Alert SMBALERT Note: 1. STARTBF, ADDRF, ADDR10F, STOPF, BSF, RXDATNE and TXDATE are merged into the event interrupt channel through logical OR. 2. BUSERR, ARLOST, ACKFAIL, OVERRUN, PECERR, TIMEOUT and SMBALERT are merged into the error interrupt channel through logical OR.
Page 490: I2C Control Register 1 (I2C_Ctrl1)
Control Register 1 (I2C_CTRL1) Address offset: 0x00 Reset value: 0x0000 Bit Field Name Description SWRESET Software reset Make sure the I2C bus is idle before resetting this bit. 0:I2C not reset; 1:I2C reset. Note: This bit can be used when the I2C_STS2.BUSY bit is set to 1 and no stop condition is detected on the bus.
Page 491 Bit Field Name Description 0：No acknowledge send; 1：Send an acknowledge after receiving a byte STOPGEN Stop generation It can be set or cleared by software. Or it will be cleared by hardware when a stop condition is detected. Or it will be set by hardware when SMBus timeout error is detected,. In the master mode: 0：No stop condition generates;...
Page 492: I2C Control Register 2 (I2C_Ctrl2)
Bit Field Name Description I2C Peripheral enable 0：Disable I2C module; 1：Enable I2C module Note: If this bit is cleared when the communication is in progress, the I2C module is disabled and returns to the idle state after the current communication ends,all bits will be cleared. In master mode,this bit must never be cleared until the communication has ended.
Page 493: I2C Own Address Register 1 (I2C_Oaddr1)
Bit Field Name Description 1：Enable error interrupt. This interrupt is generated when: I2C_STS1.BUSERR = 1； I2C_STS1.ARLOST = 1； I2C_STS1.ACKFAIL = 1； I2C_STS1.OVERRUN = 1； I2C_STS1.PECERR = 1； I2C_STS1.TIMOUT = 1； I2C_STS1.SMBALERT = 1. Reserved Reserved, the reset value must be maintained. CLKFREQ[5:0] I2C Peripheral clock frequency CLKFREQ[5:0] should be the APB clock frequency to generate the correct timming.
Page 494: I2C Own Address Register 2 (I2C_Oaddr2)
Own Address Register 2 (I2C_OADDR2) Address offset: 0x0C Reset value: 0x0000 Bit Field Name Description 15:8 Reserved Reserved, the reset value must be maintained. ADDR2[7:1] Interface address 7~1 bits of address in dual address mode. DUALEN Dual addressing mode enable 0: Disable dual address mode, only OADDR1 is recognized;...
Page 495 Bit Field Name Description SMBALERT SMBus alert Writing ‘0’ to this bit by software can clear it, or it is cleared by hardware when I2C_CTRL1.EN=0. 0: No SMBus alert(host mode) or no SMB alert response address header sequence(slave mode); 1: SMBus alert event is generated on the pin(host mode) or receive SMBAlert response address(slave mode) TIMOUT Timeout or Tlow error...
Page 496 Bit Field Name Description 1: Arbitration lost. When the interface loses control of the bus to another host, the hardware will set this bit to '1', and the I2C interface will automatically switch back to slave mode (I2C_STS2.MSMODE=0). Note: In SMBUS mode, the arbitration of data in slave mode only occurs in the data stage or the acknowledge transfer interval (excluding the address acknowledge).
Page 497 Bit Field Name Description After the software reads the STS1 register, the operation of writing to the CTRL1 register will clear this bit, or when I2C_CTRL1.EN=0, the hardware will clear this bit. 0: No ADD10F event; 1: Master has sent the first address byte. In 10-bit address mode, when the master device has sent the first byte, the hardware sets this bit to' Note: After receiving a NACK, the I2C_STS1.ADDR10F bit is not set.
Page 498: I2C Status Register 2 (I2C_Sts2)
I2C Status Register 2 (I2C_STS2) Address offset: 0x18 Reset value: 0x0002 Bit Field Name Description 15:8 PECVAL[7:0] Packet error checking register Stores the internal PEC value When I2C_CTRL1.PECEN =1. DUALFLAG Dual flag(Slave mode) Hardware clears this bit when a stop condition or a repeated start condition is generated, or when I2C_CTRL1.EN=0.
Page 499: I2C Clock Control Register (I2C_Clkctrl)
Bit Field Name Description 0: No data communication on the bus; 1: Data communication on the bus. When detecting that SDA or SCL is low level, the hardware sets this bit to' 1'; Note:This bit indicates the bus communication currently in progress, and this information is still updated when the interface is disabled (I2C_CTRL1.EN=0).
Page 500: I2C Rise Time Register (I2C_Tmrise)
Bit Field Name Description • If duty cycle = Tlow/Thigh = 16/9: CLKCTRL = f (Hz)/100000/25 PCLK1 Tlow = 16 × CLKCTRL× T PCLK1 Thigh = 9 × CLKCTRL× T PCLK1 For example, if f (Hz) = 8MHz, duty cycle = 1/1, CLKCTRL = 8000000/100000/2 = 0x28. PCLK1 Note: 1.
Page 501: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
23 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction USART is a full-duplex universal synchronous/asynchronous serial transceiver module. This interface is a highly flexible serial communication device that can perform full-duplex data exchange with external devices. The USART has programmable transmit and receive baud rates and can communicate continuously using DMA. It also supports multiprocessor communication, LIN mode, synchronous mode, single-wire half-duplex communication, smart card asynchronous protocol, IrDA SIR ENDEC function, and hardware flow control function.
Page 502 • Parity control: • Send parity bit • Check the received data • Four error detection flags: • Overflow error • Noise error • Frame error • Parity error • 10 USART interrupt sources with flags: • CTS change • LIN break detection •...
Page 503: Functional Block Diagram
Functional Block Diagram Figure 23-1 USART Block Diagram CPU/DMA Transmit Data Receive Register(TDR) Data(RDR) IrDA ENDEC Transmit Shift Receive Shift BLOCK SW_RX Register Register Hardware nRTS flow TX control RX control controller nCTS Tx clock Rx clock Buadrate CTRL register PCLK generate BRCF...
Page 504: Usart Frame Format
receiving device through its own TX interface, and the bus is in an idle state before sending or receiving. Frame format is: 1 start bit + 8 or 9 data bits (least significant bit first) + 1 parity bit (optional) + 0.5,1,1.5 or 2 stop bit. Use the fractional baud rate generator to configure transmit and receive baud rates.
Page 505: Transmitter
Figure 23-3 Word Length = 9 Setting 9-bit word length , 1 stop bit Clock Data frame bit8 can be the parity bit Data frame Start Stat Stop bit2 bit6 bit7 bit8 bit0 bit1 bit3 bit4 bit5 Start Idle frame Start Stop Break frame...
Page 506: Figure 23-4 Configuration Stop Bit
Figure 23-4 Configuration Stop Bit 8-bit Word length (WL bit is reset) CLOCK bit7 can be the parity bit Data frame Start Stat bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Data frame 0.5 Stop bit 0.5Stop bit Data frame bit7 can be the parity bit Data frame Start...
Page 507: Single Byte Communication
the end of the transmission of the last data frame. Single byte communication A write to the USART_DAT register clears the USART_STS.TXDE bit. The USART_STS.TXDE bit is set by hardware when the data in the TDR register is transferred to the transmit shift register (indicating that data is being transmitted).
Page 508: Figure 23-6 Start Bit Detection
an interruption occurs and will not Set the NEF noise flag. If there are six ‘0’ samples at the 3 bits, and at the 8 , 10 bits, a start bit is confirmed to have been received, and USART_STS.RXDNE is set to 1, but the NE noise flag will not be set. If USART_CTRL1.RXDNEIEN has been set to 1, an interrupt will be generated.
Page 509: Framing Error
stop bit on the bus, indicating that a framing error has occurred. The USART_STS.FEF is set together with the USART_STS.RXDNE at the end of the 1.5th stop bit. The 1.5 stop bits are sampled at points 16, 17 and 18. The 1.5 stop bits can be divided into two parts: one is 0.5 clock cycles, during which nothing happens.
Page 510: Overrun Error
Overrun error When USART_STS.RXDNE is still '1', and the data currently received in the shift register needs to be transferred to the RDR register, an overflow error will be detected, and the hardware will set USART_STS.OREF. When this bit is set, the value in the RDR register is not lost, but the data in the shift register is overwritten.
Page 511: Receiver's Tolerance Clock Deviation
USARTDIV and USART_BRCF register configuration Example 1: If USARTDIV = 27.75, then： DIV_Decimal = 16*0.75 = 12 = 0x0C DIV_Integer = 27=0x1B So USART_BRCF = 0x1BC Example 2: If USARTDIV = 20.98, then： DIV_Decimal = 16*0.98 = 15.68 Nearest integer: DIV_Decimal = 16 = 0x10, out of configurable range, so a carry to integer is required So DIV_Integer = 20+1 = 21 = 0x15 DIV_Decimal = 0x0 So USART_BRCF = 0x150...
Page 512: Parity Control
errors, receiver side oscillator variations, variations due to transmission lines (usually due to The inconsistency between the low-to-high transition timing of the transceiver and the high-to-low transition timing of the transceiver), these factors will affect the overall clock system variation. Only when the sum of the above four changes is less than the tolerance of the USART receiver, the USART asynchronous receiver can work normally.
Page 513: Dma Application
an odd number, the check is passed, indicating that no errors occurred during the transmission process. If it is not an odd number, it means that an error has occurred, the USART_STS.PEF flag is set to '1', and if USART_CTRL1.PEIEN is enabled, an interrupt is generated. DMA Communication The USART supports the DMA mode using multi-buffer configuration, which can realize high-speed data communication.
Page 514: Figure 23-7 Transmission Using Dma
Figure 23-7 Transmission Using DMA TXDE flag set by hardware cleared by DMA DMA writes Data1 DMA writes DataN DMA writes Data0 into USART_DAT into USART_DAT into USART_DAT DMA request Data 0 Data 1 Data N TX line Software waits TXC=1 TXC flag set by hardware...
Page 515: Hardware Flow Control
Figure 23-8 Reception Using DMA Data 0 Data 1 Data N RX line RXDNE flag set by hardware cleared by DMA DMA reads Data0 DMA reads Data1 DMA reads DataN from USART_DAT from USART_DAT from USART_DAT DMA request DMA transfer is complete DMA TXCF flag set by hardware...
Page 516: Figure 23-10 Rts Flow Control
RTS flow control Set USART_CTRL3.RTSEN to enable RTS. RTS is the output signal used to indicate that the receiver is ready. When data arrives in RDR, nRTS is asserted, notifying the sender to stop data transmission at the end of the current frame. when , nRTS is asserted.
Page 517: Figure 23-11 Cts Flow Controls
Figure 23-11 CTS Flow Controls CTSF = 1 CTSF = 1 CTS line Writing Data 3 in Data register Data register empty empty Data 2 Data 3 CTS = 1, CTS = 0, Transmit delay Transmit Data 3 Start Start Stop Stop Data 2...
Page 518: Figure 23-12 Mute Mode Using Idle Line Detection
Figure 23-12 Mute Mode Using Idle Line Detection RXDNE = 1 RXDNE = 1 Data1 Data2 Data3 Data4 IDLE Data5 Data6 RCVWU Normal Mode Mute Mode Idle frame detected RCVWU written to 1 Address mark detection By configuring the USART_CTRL1.WUM bit to 1, the USART performs address mark detection. The address of the receiver is programmable through the USART_CTRL2.ADDR[3:0] bits.
Page 519: Synchronous Mode
Figure 23-13 Mute Mode Detected Using Address Mark RXDNE=1 RXDNE=1 RXDNE=1 In this example, the current address of the receiver is 1 ADDR ADDR Addr IDLE Data1 Data2 IDLE Data3 Data4 Data5 RCVWU Mute Mode Normal Mode Mute Mode Error address Current address Error address RCVWU written to 1...
Page 520: Figure 23-14 Usart Synchronous Transmission Example
Synchronousreceiving The receiver in synchronous mode works differently than in asynchronous mode. Data is sampled on CK without any oversampling. But setup time and hold time (depending on baud rate, 1/16 bit time) must be considered. Figure 23-14 USART Synchronous Transmission Example MISO MOSI USART...
Page 521: Single-Wire Half-Duplex Mode
Figure 23-16 USART Data Clock Timing Example (WL=1) Clock（CLKPOL=0，CLKPHA=0） Clock（CLKPOL=0，CLKPHA=1） Clock（CLKPOL=1，CLKPHA=0） Clock（CLKPOL=1，CLKPHA=1） Data on TX (from master) MSB Stop Start LSB Data on RX (from slave) Figure 23-17 RX Data Sampling / Holding Time SCLK(capture strobe on SCLK rising edge in this example) Data on RX valid DATA bit (from slave)
Page 522: Irda Low Power Mode
Through the USART_CTRL3.HDMEN bit, you can choose whether to enable half-duplex mode. When using single- wire half-duplex, USART_CTRL2. CLKEN, USART_CTRL2. LINMEN, USART_CTRL3. SCMEN, USART_CTRL3. IRDAMEN, these bits should be kept clear. After the half-duplex mode is turned on, the TX pin and the RX pin are internally connected, and the RX pin is no longer used.
Page 523: Lin Mode
Figure 23-18 IrDBlock Diagram TX pin Transmit Encoder IRDAMEN NORMAL = 0 or 1 USART MODE Receive RX pin Decoder Figure 23-19 IrDA Data Modulation (3/16)-Normal Mode Start TX normal Stop frame TX pin frame 3/16 RX pin frame Start RX normal Stop frame...
Page 524: Lin Reception
LIN Reception Whether the bus is idle or during the transmission of a data frame, as long as the break frame appears, it can be detected. The break symbol detection is independent of the USART receiver. By configuring the USART_CTRL2.LINBDL bit, 10-bit or 11-bit break character detection can be selected. When the receiver detects the start bit, the circuit samples each subsequent bit at the 8th, 9th, and 10th oversampling clock points of each bit.
Page 525: Figure 23-20 Break Detection In Lin Mode (11-Bit Break Length-The Linbdl Bit Is Set)
Figure 23-20 Break Detection in LIN Mode (11-bit break length-the LINBDL bit is set) Case 1: break signal not long enough => break discarded, LINBDF is not set Break frame RX line Idle Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8...
Page 526: Smartcard Mode (Iso7816)
Figure 23-21 Break Detection And Framing Error Detection in LIN Mode In these examples, we suppose that LINBDL=1(11-bit break length),WL=0(8-bit data) Break occurring after an Idle： frame1 RX line Idle frame2 frame3 1 frame time 1 frame time RXDNE/FEF LINBDF Break occurring while a data is being received：...
Page 527: Figure 23-22 Iso7816-3 Asynchronous Protocol
The example given in the following figure illustrates the signal on the data line with and without parity errors. Figure 23-22 ISO7816-3 Asynchronous Protocol Without Parity error Guard time Start With Parity error Guard time Line pulled low by receiver during stop Start In case of parity error The break frame has no meaning in smart card mode.
Page 528: Interrupt Request
Figure 23-23 Use 1.5 Stop Bits to Detect Parity Errors 1.5 Stop Bit Parity Bit Bit 7 1 bit time 1.5 bit time sampling at sampling at 16th, 17th, 18th 8th, 9th, 10th 0.5 bit time 1 bit time sampling at sampling at 8th, 9th, 10th 8th, 9th, 10th...
Page 529: Mode Support
Mode Support Table 23-8 USART Mode Setting Communication Mode USART1 USART2 USART3 UART4 UART5 Asynchronous mode Hardware flow control mode DMA communication mode Multiprocessor Synchronous mode Smartcard mode Single-wire half duplex mode IrDA infrared mode Note: Y = support this mode, N = do not support this mode USART Register USART Register Overview Table 23-9 USART Register Overview...
Page 530: Usart Status Register (Usart_Sts)
Offset Register STPB USART_CTRL2 ADDR[3:0] [1:0] 010h Reserved Reset Value USART_CTRL3 014h Reserved Reset Value USART_GTP GTV[7:0] PSCV[7:0] 018h Reserved Reset Value USART Status Register (USART_STS) Address offset : 0x00 Reset value : 0x0000 00C0 Bit Field Name Description 31:10 Reserved Reserved, the reset value must be maintained CTSF...
Page 531 Bit Field Name Description 1: The transmitting data buffer is empty. Transmission complete. This bit is set to 1 after power-on reset. If USART_STS.TXDE is set, this bit is set when the current data transmission is completed. Setting USART_CTRL1.TXCIEN bit will generate an interrupt. This bit is cleared by software.
Page 532: Usart Data Register (Usart_Dat)
Bit Field Name Description When the data is not synchronized or a large amount of noise is detected, and the stop bit is not received and recognized at the expected time, it will be judged that a framing error has been detected, and this bit will be set to 1. First read USART_STS, then read USART_DAT can cleared this bit.
Page 533: Usart Baud Rate Register (Usart_Brcf)
USART Baud Rate Register (USART_BRCF) Address offset : 0x08 Reset value : 0x0000 0000 Note: When USART_CTRL1.UEN=1, this register cannot be written;The baud counter stops counting if USART_CTRL1.TXEN or USART_CTRL1.RXEN are disabled respectively. Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:4 DIV_Integer[11:0] Integer part of baud rate divider.
Page 534 Bit Field Name Description Wake up mode from mute mode. 0: Idle frame wake up. 1: Address identifier wake up. PCEN Parity control enable 0: Parity control is disabled. 1: Parity control is enabled. PSEL Parity selection. 0: even check. 1: odd check.
Page 535: Usart Control Register 2 Register (Usart_Ctrl2)
Bit Field Name Description cleared by hardware. Or when an address mismatch frame is received, it is set to 1 by hardware. 0: The receiver is in normal operation mode. 1: The receiver is in mute mode. SDBRK Send Break Character. The software transmits a break character by setting this bit to 1.
Page 536: Usart Control Register 3 Register (Usart_Ctrl3)
Bit Field Name Description CLKPHA Clock phase. This bit is used to set the phase of CK pin in synchronous mode. 0: Sample the first data at the first clock edge. 1: Sample the first data at the second clock edge. Note: This bit cannot be used for UART4/5.
Page 537 Bit Field Name Description 31:11 Reserved Reserved, the reset value must be maintained CTSIEN CTS interrupt enable. If this bit is set to 1, an interrupt will be generated when USART_STS.CTSF bit is set. 0:CTS interrupt is disabled. 1:CTS interrupt is enabled. Note: This bit cannot be used for UART4/5 CTSEN CTS enable.
Page 538: Usart Guard Time And Prescaler Register (Usart_Gtp)
Bit Field Name Description 0: Half-duplex mode is disabled. 1: Half-duplex mode is enabled. IRDALP IrDA low-power mode. This bit is used to select the low power consumption mode for IrDA mode. 0: Normal mode. 1: Low power mode. IRDAMEN IrDA mode enable.
Page 539 11111111: divide the source clock by 255. In IrDA normal mode: PSCV can only be set to 00000001. In Smartcard mode: PSCV[4:0] is used to set the frequency division of Smartcard clock generated by peripheral clock (PCLK1/ PCLK2). Coefficient. The actual frequency division coefficient of is twice the set value of PSCV[4:0].
Page 540: Low Power Universal Asynchronous Receiver Transmitter (Lpuart)
24 Low Power Universal Asynchronous Receiver Transmitter (LPUART) Introduction Low power universal asynchronous receiver transmitter (LPUART) is a low power, full duplex, asynchronous serial communication interface. The LPUART can be clock provided by LSE, HSI, SYSCLK and PCLK1. When 32.768kHz LSE is selected as the clock source, the LPUART can work in STOP2 low-power mode with a maximum communications up to 9600bps.
Page 541: Functional Block Diagram
– Oneprogrammable 4-byte frame Functional Block Diagram Figure 24-1 LPUART Block Diagram CPU/DMA Receive data register(RDR) Transmission data register(TDR) Receive buffer Transmission shift register Receive shift register CTRL register Hardware data flow control Wake up Tx control Rx control controller STS register Interrupt control INTEN register...
Page 542: Lpuart Frame Format
The following pins are required in hardware flow control mode: CTS (Clear To Send): When transmitter detects that CTS is valid (low level), the next data is sent. RTS (Request To Send): When receiver is ready to receive new data, pull the RTS pin low. LPUART has the following characteristics: •...
Page 543: Transmission Process
Transmission process During an LPUART transmission, the least significant bit of the data is shifted out on TX pin. In this mode, the LPUART_DAT register contains a buffer between the internal bus and the transmitter shift register (see Figure 24-1). Each character is preceded by a low level starting bit;...
Page 544: Receiver
Figure 24-3 TXC Changes During Transmission Software Software clears TXC and Write Data0 directly Software clears TXC and enable TXEN writes Data2 in in LPUART_DAT writes Data1 in LPUART_DAT without waiting LPUART_DAT LPUART_DAT Data0 Data1 Data2 TXC flag Set by hardware Set by hardware Set by hardware Send stop bit...
Page 545 Return to Step 2 and continue receiving data. Note: Please be sure to initialize the LPUART module before using the receiver. When receiving a data frame: • The LPUART_STS.FIFO_NE bit is set, and the contents of the shift register are transferred to the RDR (Receiver Data Register).
Page 546: Fractional Baud Rate Generation
Figure 24-4 Data Sampling for Noise Detection Receiving signal line Sampling clock The length of a bit Table 24-1 Data Sampling for Noise Detection Sampling Values NF State Received Bit Value When noise is detected in a receiving frame, you can do the following: •...
Page 547: Parity Control
Configure baud rates through LPUART_BRCFG1 and LPUART_BRRCFG2 For example, baud rate = 4800bps, clock frequency = 32768Hz. LPUARTDIV = 32768/4800 = 6.82667.LPUART_BRCFG1 = 6 and the value of LPUART_BRCFG2 is calculated by adding fractions in the table below (the value of LPUART_BRCFG2 is 0xEFh). Decimal Addition Carry To The Next Integer Bit Field...
Page 548: Dma Application
Table 24-2 Parity Frame Format PCDIS bit LPUART Frame | Start bit | 8-bit data | parity bit | stop bit | | Start bit | 8 bits data | stop bit | Transfer mode: Parity is enabled by resetting the LPUART_CTRL.PCDIS bit. If parity fails, the LPUART_STS.PEF flag is set to '1', and an interrupt occurs if LPUART_INTEN.PEIE is set.
Page 549: Figure 24-5 Sending Using Dma
Figure 24-5 Sending Using DMA Data frame 0 Stop bit Data frame 1 Stop bit Stop bit Data frame 2 TX line Transfer is over, DMA Software enable controller ignores this request to send data DMA writes Data0 DMA writes Data1 DMA writes Data2 in LPUART_DAT in LPUART_DAT...
Page 550: Hardware Flow Control
Figure 24-6 Receiving Using DMA Data frame 0 Stop bit Data frame 1 Stop bit Stop bit Data frame 2 RX line Cleared by DMA Set by hardware FIFO_NE detection operation DMA reads Data0 DMA reads Data1 DMA reads Data2 in LPUART_DAT in LPUART_DAT in LPUART_DAT...
Page 551: Figure 24-8 Rts Flow Control
threshold condition is achieved, otherwise it will be driven low.How is the RTS valid can be selected by the LPUART_CTRL.RTS_THSEL[1:0] bits. The RTS threshold can be selected to be effective when the FIFO is half full, 3/4 full, or full. Below is an example of communication with RTS flow control enabled. Figure 24-8 RTS Flow Control Waiting to read data Read data register...
Page 552: Low Power Wake Up
Low Power Wake Up LPUART can work in STOP2 mode. If the LPUART_CTRL.WUSTP is set, it can wake up the system on EXTI line 23 when a specific waking up event occurs. The LPUART waking up event can be handled in the following ways (through the LPUART_CTRL.WUSEL[1:0]) : •...
Page 553: Lpuart Status Register (Lpuart_Sts)
Offset Register LPUART_BRCFG1 INTEGER[15:0] 00Ch Reserved Reset Value LPUART_DAT DAT[7:0] 010h Reserved Reset Value LPUART_BRCFG2 DECIMAL[7:0] 014h Reserved Reset Value LPUART_WUDAT WUDAT[31:0] 018h Reset Value LPUART Status Register (LPUART_STS) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:9 Reserved Reserved, the reset value must be maintained.
Page 554: Lpuart Interrupt Enable Register (Lpuart_Inten)
Bit Field Name Description 0: Buffer is not full. 1: Buffers is full.RX data should be read out in preparation for receiving new data FIFO_OV FIFO overrun flag. 0: Buffer did not overrun 1: Buffer overrun. TX complete flag. 0: TX is disabled or not complete. 1: TX transmission is complete.
Page 555: Lpuart Control Register (Lpuart_Ctrl)
Bit Field Name Description PEIE Parity check error interrupt enable 0: Disable parity error interrupt 1: Enable parity error interrupt LPUART Control Register (LPUART_CTRL) Address offset: 0x08 Reset value: 0x0000 0200 Bit Field Name Description 31:15 Reserved Reserved, the reset value must be maintained. SMPCNT Specify sampling method 0: 3 sample bits, noise detection is allowed (LPUARTDIV should be large...
Page 556: Lpuart Baud Rate Configuration Register 1 (Lpuart_Brcfg1)
Bit Field Name Description 0: Normal mode 1: Loopback self-test mode PCDIS Parity control 0: Enables parity bit 1: Disables parity bit FLUSH Clear receive buffer 0: Disables buffer clear 1: Clear buffer content TXEN TX enable 0: Disables TX 1: Enables TX PSEL Odd parity enable...
Page 557: Lpuart Baud Rate Configuration Register 2 (Lpuart_Brcfg2)
Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. DAT[7:0] Write to the data register when sending Read the data register when receiving LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2) Address offset: 0x14 Reset value: 0x0000 0000 Bit Field Name Description...
Page 558 Bit Field Name Description whether the conditions for wake up from STOP2 mode is matched (byte match or frame match): LPUART_CTRL.WUSEL[1:0] = 10 is used to wake up byte matching. In this case, the first byte is valid LPUART_CTRL.WUSEL[1:0] = 11 is used to wake up frame matching. In this case, all 4 bytes are valid 533 / 652...
Page 559: Serial Peripheral Interface/Inter-Ic Sound
25 Serial Peripheral Interface/Inter-IC Sound (SPI/I Introduction This module is about SPI/I S. It works in SPI mode by default and users can choose to use I S by setting the value of registers. Serial peripheral interface (SPI) is able to work in master or slave mode, support full-duplex and simplex high-speed communication mode, and have hardware CRC calculation and configurable multi-master mode.
Page 560: I 2 S Features
• Single-byte send and receive buffer with DMA capability: generates send and receive requests • Maximum interface speed: 16Mbps S Features • Simplex communication (send or receive only) • Master or slave operations • 8-bit linear programmable prescaler for accurate audio sampling frequencies (8KHz to 96KHz) •...
Page 561: Spi Function Description
SPI function Description General Description Figure 25-1 SPI Block Diagram address and data bus Read Receive buffer MOSI LSBFF SPI_CTRL2 control bit Shift register SSOEN TDMAEN RDMAEN MISO INTEN INTEN INTEN SPI_STS Send buffer BUSY OVER MODERR UNDER CHSIDE Write Communication circuit BR[2:0] LSBFF...
Page 562: Figure 25-2 Selective Management Of Hardware/Software
The software slave device management is enabled when SPI_CTRL1.SSMEN = 1 (Figure 25-2). The NSS pin is not used in software NSS mode. In this mode the internal NSS signal level is driven by writing the SPI_CTRL1.SSEL bit (master mode SPI_CTRL1.SSEL = 1, slave mode SPI_CTRL1.SSEL = 0). Hardware NSS mode The software slave device management is disabled when SPI_CTRL1.SSMEN = 0.
Page 563: Figure 25-3 Master And Slave Applications
Figure 25-3 Master And Slave Applications Slave Master MSBit MSBit LSBit LSBit MISO 8-bit shift register 8-bit shift register MOSI SPI clock generator NSS(1) NSS(1) Not used if NSS is managed by software Note: NSS pin is set as input SPI is a ring bus structure.
Page 564: Data Format
Figure 25-4 Data Clock Timing Diagram CLKPHA=1 CLKPOL=1 CLKPOL=0 MISO （from master） SPI_CTRL1 determines whether the data frame format is 8 or 16 bits MISO （from slave）（to slave） Capture strobe CLKPHA=0 CLKPOL=1 CLKPOL=0 MISO （from master） SPI_CTRL1 determines whether the data frame format is 8 or 16 bits MISO （from slave）...
Page 565: Figure 25-5 Schematic Diagram Of The Change Of Te/Rne/Busy When The Host Is Continuously Transmitting In Full Duplex Mode
MOSI pin. At the same time, the data receives on the MISO pin is serially shifted into the shift register in the same order and then loaded into the SPI_DAT register in parallel. The software operation process is as follows: Set SPI_CTRL1.SPIEN = 1, enable SPI module.
Page 566: Figure 25-6 Schematic Diagram Of Te/Busy Change When Host Transmits Continuously In One-Way Only Mode
Wait for SPI_STS.TE bit to be set to '1', and write the second data to be sent into SPI_DAT. Repeat this operation to send subsequent data; After writing the last data to SPI_DAT, wait for SPI_STS.TE bit to set '1'; then wait for SPI_STS.BUSY bit to be cleared to complete the transmission of all data.
Page 567: Figure 25-7 Schematic Diagram Of Rne Change When Continuous Transmission Occurs In Receive-Only Mode (Bidirmode = 0 And Ronly = 1)
Figure 25-7 Changes of RNE during Continuous Transmission Occurs in Receive-only Mode (BIDIRMODE = 0 and RONLY = 1) Configure：CLKPOL=1.CLKPHA=1,RONLY=1 DATA1=0xAA DATA2=0xBB DATA3=0xCC MISO/MOSI （in） Set by hardware Clear by software RNE flag Rx buffer 0xAA 0xBB 0xCC （read fromSPI_DAT） Wait until RNE=1,read 0xAA from SPI_DAT Wait until RNE=1,read 0XBB from SPI_DAT Wait until RNE=1,read 0xCC from SPI_DAT...
Page 568: Figure 25-9 Schematic Diagram Of Te/Busy Change During Continuous Transmission In Slave Unidirectional Transmit- Only Mode
Figure 25-8 Change of TE/RNE/BUSY during The Slave Is Continuously Transmitting in Full Duplex Mode Slave mode：CLKPOL=1.CLKPHA=1 DATA1=0x11 DATA2=0x22 DATA3=0x33 MISO/MOSI (out) TE flag Set by hardware Clear by software Tx buffer 0x11 0x22 0x33 （write to SPI_DAT） The flag set/clear by hardware BUSY flag DATA1=0xAA DATA2=0xBB...
Page 569 • Slave one-wire bidirectional transmit mode (SPI_CTRL1.MSEL=0, SPI_CTRL1.BIDIRMODE=1 and SPI_CTRL1.BIDIROEN=1) When the slave device receives the first edge of the clock signal, the transmitting process starts. No data is received in this mode, and the software must ensure that the data to be sent has been written in the SPI_DAT register before the SPI master device starts data transmission.
Page 570: Status Flag
recommended to enable the SPI module before the host sends the clock). In some configurations, when the last data is sent, the BUSY flag (SPI_STS.BUSY) can be used to wait for the end of the data sending. Continuous and discontinuous transmission. When sending data in master mode, if the software is fast enough to detect each TE (SPI_STS.TE) rising edge (or TE interrupt), and the data is written to the SPI_DAT register immediately before the end of the ongoing transmission.
Page 571: Disabling The Spi
BUSY flag bit (BUSY) When the transmission starts, the hardware sets the BUSY flag (SPI_STS.BUSY) to 1, and after the transmission ends, the hardware sets the BUSY flag to 0. Only when the device is in the master one-wire bidirectional receive mode, the BUSY flag (SPI_STS.BUSY) will be set to 0 when the communication is in progress.
Page 572: Spi Communication Using Dma
the SPI module will be turned off; 2. If you want to enter the shutdown mode, you must wait for the BUSY flag (SPI_STS.BUSY) to be set to 0 before entering the shutdown mode (or turn off the SPI module clock). SPI Communication Using DMA Users can choose DMA for SPI data transmission, the application program can be released, and the system efficiency can be greatly improved.
Page 573: Crc Calculation
Figure 25-12 Reception Using DMA CLKPOL=1.CLKPHA=1 DATA1=0xAA DATA2=0xBB DATA3=0xCC MISO/MOSI (in) Clear by DMA RNE flag Set by hardware read Rx buffer 0xAA 0xBB 0xCC （read from SPI_DAT） DMA request DMA read from SPI_DAT DMA flag Set by hardware Clear by software （DMA transfer complete）...
Page 574: Error Flag
Error Flag Master mode failure error (MODERR) The following two conditions will cause the master mode failure error: • In NSS pin hardware management mode, the master device NSS pin is pulled low; • In NSS pin software management mode, the SPI_CTRL1.SSEL bit is set to 0. •...
Page 575 550 / 652...
Page 576: I 2 S Function Description
S Function Description The block diagram of I2S is shown in the figure below: Figure 25-13 I S Block Diagram Address and data bus Tx buffer SPI_STS MODER BUSY OVER UNDER CHSIDE MOSI/SD 16-bit LSBFF control bit Shift register MISO 16-bit Communication circuit Rx buffer...
Page 577: Supported Audio Protocols
synchronization between systems. Note: F is the sampling frequency of audio signal In master mode, I2S uses its own clock generator to generate clock signals for communication, and this clock generator is also the clock source of the master clock output (SPI_I2SPREDIV.MCLKOEN = 1, the master clock output is enabled).
Page 578: Figure 25-14 I 2 S Philips Protocol Waveform (16/32-Bit Full Precision, Clkpol = 0)
Figure 25-14 I S Philips Protocol Waveform (16/32-bit full precision, CLKPOL = 0) Receive Send Left channel (data format 16-bit or 32-bit) Right channel Figure 25-15 I S Philips Protocol Standard Waveform (24-bit frame, CLKPOL = 0) Recieve Send The remaining 8 bits are forced to 0 24-bit data...
Page 579: Figure 25-16 I 2 S Philips Protocol Standard Waveform (16-Bit Extended To 32-Bit Packet Frame, Clkpol = 0)
Figure 25-16 I S Philips Protocol Standard Waveform (16-bit extended to 32-bit packet frame, CLKPOL = 0) Recieve Send The remaining 16 bits are forced to 0 16-bit data Right channel Left channel 32-bit data If 16-bit data needs to be packed into 32-bit data frame format, the CPU only needs to read or write the SPI_DAT register once for each frame of data transmission.
Page 580: Figure 25-17 The Msb Is Aligned With 16-Bit Or 32-Bit Full Precision, Clkpol = 0
Figure 25-17 The MSB Is Aligned with 16-bit or 32-bit Full Precision, CLKPOL = 0 Send Receive Left channel (16-bit or 32-bit) Right Channel Figure 25-18 MSB Aligns 24-bit Data, CLKPOL = 0 Send Receive 8-bit remaining 0 forced 24-bit data Right channel Left channel 32-bit 555 / 652...
Page 581: Figure 25-19 Msb-Aligned 16-Bit Data Is Extended To 32-Bit Packet Frame, Clkpol = 0
Figure 25-19 MSB-aligned 16-bit Data Is Extended to 32-bit Packet Frame, CLKPOL = 0 Receive Send 16-bit remaining 0 forced 16-bit data Right channel Left channel 32-bit LSB alignment standard In 16-bit or 32-bit full-precision frame format, LSB alignment standard is the same as MSB alignment standard. Figure 25-20 LSB Alignment 16-bit or 32-bit Full Precision, CLKPOL = 0 Send Receive...
Page 582: Figure 25-21 Lsb Aligns 24-Bit Data, Clkpol = 0
Figure 25-21 LSB Aligns 24-bit Data, CLKPOL = 0 Send Receive 8-bit data forced 0 24-bit data Right channel Left channel 32-bit If the 24-bit data needs to be packed into the 32-bit data frame format, the CPU needs to read or write the SPI_DAT register twice during each frame of data transmission.
Page 583: Clock Generator
In the PCM standard, there are two frame structures, short frame and long frame. The user can select the frame structure by setting the SPI_I2SCFG.PCMFSYNC bits. The WS signal indicates frame synchronization information. The WS signal for synchronizing long frames is 13 bits effective; the WS signal length for synchronizing short frames is 1 bit.
Page 584: Figure 25-25 I 2 S Clock Generator Structure
Figure 25-25 I S Clock Generator Structure MCLK 8-bit Linear Divider Divider Divider + by 2 by 4 reshaping I2Sx CLK stage MCLKOEN ODD_ MCLK LDIV[7:0] BITS EVEN Note: The clock source of I Sx CLK is MSI, HSI, HSE or PLL system clock that drives AHB clock. The bit rate of I2S determines the data flow on the I2S data line and the frequency of the I2S clock signal.
Page 585: I 2 S Transmission And Reception Sequence
Table 25-2 Use The Standard 8mhz HSE Clock to Get Accurate Audio Frequency Sysclk s_Ldiv s_Odd_Even Target Real F (Hz) Error Mclk (Hz) （Mhz） 16 bits 32 bits 16 bits 32 bits 16bit 16 bits 32 bits 16 bits without 96000 93750 93750...
Page 586: Master Mode
When I2S works in master mode, the CLK pin outputs the serial clock, the WS pin generates the channel selection signal, and sets the SPI_I2SPR.MCLKOEN bit to select whether to output the master clock (MCLK). The transmitting process begins when data is written to the transmit buffer. When the data of the current channel is moved from the transmit buffer to the shift register in parallel, the flag bit TE (SPI_STS.TE) is set to '1'.
Page 587: Status Flag
steps: • Data length is 16 bits, channel length is 32 bits (SPI_I2SCFG.TDATTLEN = 00, SPI_I2SCFG.CHBITS = 1), LSB alignment standard (SPI_I2SCFG.STDSEL = 10). Wait for the penultimate RNE flag (SPI_STS.RNE) bit to be set to' 1'. Software delay, waiting for 17 I S clock cycles.
Page 588: Error Flag
(SPI_STS.BUSY) is set to 0 by hardware (software operation is invalid). In master receiving mode (SPI_I2SCFG.MODCFG = 11), the BUSY flag (SPI_STS.BUSY) is set to 0 during receiving. When the I2S module is turned off or the transmission is completed, this flag is set to 0. In the slave continuous communication mode, between each data item transmission, the BUSY flag (SPI_STS.BUSY) goes low in 1 I S clock cycle.
Page 589: Dma Function
DMA Function Working in I2S mode, it does not need data transmission protection function, so it does not need to support CRC, other DMA functions are the same as SPI mode. SPI and I S Register Description SPI Register Overview Table 25-4 SPI Register Overview Offset Register...
Page 590 Bit Field Name Description BIDIRMODE Bidirectional data mode enable 0: Select the "two-wire one-way" mode. 1: Select the "one-wire bidirectional" mode. Note: Not used in I S mode. BIDIROEN Output enable in bidirectional mode 0: Output disable (receive-only mode). 1: Output enabled (send-only mode). In master mode, the "one-wire"...
Page 591 Bit Field Name Description SSEL Internal slave device selection This bit only has meaning when the SPI_CTRL1.SSMEN bit is set. It determines the NSS level, and I/O operations on the NSS pin have no effect. Note: Not used in I S mode.
Page 592: Spi Control Register 2 (Spi_Ctrl2)
SPI Control Register 2 (SPI_CTRL2) Address: 0x04 Reset value: 0x0000 Bit Field Name Description 15:8 Reserved Reserved, the reset value must be maintained. TEINTEN Send buffer empty interrupt enable 0: Disable TE interrupt. 1: Enable TE interrupt, and interrupt request is generated when TE flag (SPI_STS.TE) is set to '1'.
Page 593 Bit Field Name Description 15:8 Reserved Reserved, the reset value must be maintained. BUSY Busy flag 0: SPI is not busy. 1: SPI is busy communicating or the send buffer is not empty. This bit is set or reset by hardware. Note: special attention should be paid to the use of this sign, see Section 25.3.3 and Section 25.3.4 for details.
Page 594: Spi Data Register (Spi_Dat)
Bit Field Name Description 1: The receive buffer is not empty. SPI Data Register (SPI_DAT) Address: 0x0C Reset value: 0x0000 Bit Field Name Description 15:0 DAT[15:0] Data register Data to be sent or received The data register corresponds to two buffers: one for write (send buffer); The other is for read (receive buffer).Write operation writes data to send buffer;...
Page 595: Spi Tx Crc Register（Spi_ Crctdat
Bit Field Name Description 15:0 CRCRDAT Receive CRC register When CRC calculation is enabled, CRCRDAT[15:0] will contain the calculated CRC value of subsequent received bytes. This register is reset when ‘1’ is written to the SPI_CTRL1.CRCEN bit. The CRC calculation uses the polynomial in SPI_CRCPOLY. When the data frame format is set to 8 bits, only the lower 8 bits participate in the calculation and follow the CRC8 standard;...
Page 596 Bit Field Name Description 15:12 Reserved Reserved, the reset value must be maintained. MODSEL S mode selection 0: Select SPI mode. 1: Select I S mode. Note: this bit can only be set when SPI or I S is turned off. S enable 0: Disable I 1: Enable I...
Page 597: Spi_I2S Prescaler Register (Spi_I2Sprediv)
Bit Field Name Description CHBITS Channel length (number of data bits per audio channel) 0: 16 bits wide. 1: 32 bits wide. Writing to this bit is meaningful only when SPI_I2SCFG.TDATLEN = 00, otherwise the channel length is fixed to 32 bits by hardware. Note: For correct operation, this bit can only be set when I S is turned off.
Page 598: Controller Area Network (Can)
26 Controller Area Network (CAN) Introduction As a CAN network interface, the basic extended CAN supports CAN protocols 2.0A and 2.0B. It can efficiently process a large number of received messages and greatly reduce the consumption of CPU resources. The priority characteristics of message sending can be configured by software, and the hardware function of CAN can support time-triggered communication mode for some applications with high security requirements.
Page 599: Can Module
requirement of CAN messages. Figure 26-1 Topology of CAN Network Node 1 CAN_H CAN- transc CTRL eiver CAN_L Node 2 Node 3 Node n CAN Module CAN module can automatically receive and transmit CAN messages, and supports standard identifiers (11 bits) and extended identifiers (29 bits).
Page 600: Normal Mode
pin, the CAN bus is idle and synchronization is completed. Normal mode After the initialization is completed, the software configures CAN to enter normal mode. Clear the CAN_MCTRL.INIRQ and wait for the hardware to clear the CAN_MSTS.INIRQ bit to confirm that CAN enters normal mode.
Page 601: Send Mailbox
bit cleared to confirm the sleep mode has exited.Please refer to Figure 26-2. Figure 26-2 CAN OperatingMode SLPRQ = 0 SLPAK = 0 11 recessive bits SLPRQ = 0 INIRQ = 0 INIRQ = 1 INIAK = 0 INIAK = 1 11 recessive bits Sleep mode Initialization mode...
Page 602: Can Test Mode
Figure 26-3 Single CAN Block Diagram Transmit Mailbox 0 Transmit Transmitter Mailbox 1 Transmit Mailbox 2 Memory CAN-CTRL Access Controller Receive FIFO0 Mailbox 0 Mailbox 1 Mailbox 2 Acceptance Filter Receive FIFO1 Mailbox 0 Mailbox 1 Mailbox 2 CAN Test Mode In the initialization mode, a test mode must be selected by combining the CAN_BTIM.SLM bit and CAN_BTIM.LBM bit.
Page 603: Figure 26-4 Loopback Mode
Figure 26-4 Loopback Mode CAN-CTRL transceiver CAN_Bus Silent mode In silent mode , CAN can normally receive data frames and remote frames, but can only send recessive bits, and can't really send messages. If CAN needs to send overload flag, active error flag or ACK bit(these are dominant bits), such dominant bits are internally connected back so as to be detected by the CAN core.
Page 604: Figure 26-5 Silent Mode
Figure 26-5 Silent Mode CAN-CTRL transceiver CAN_Bus Loopback silence mode In loopback silent mode, the CANRX pin is disconnected from the CAN bus, while the CANTX pin is driven to the recessive bit state. It can be used for "Hot Selftest" just like CAN can be tested in loop-back mode, but not affect the whole CAN system connected by CANTX and CANRX.
Page 605: Can Debugging Mode
CAN DebugMode CAN can continue to work normally or stop working according to the state of the following configuration bits: • DBG_CTRL.CAN_STOP bit of CAN in the debug support(DBG) module.See paragraph 28.3.2 Section: Peripheral debugging support. • CAN_MCTRL.DBGF bit see paragraph 26.7.3.1 Section: CAN_MCTRL. When the microcontroller is in debug mode, Cortex ®...
Page 606: Canceling Transmission
Canceling transmission Setting the CAN_TSTS.ABRQM bit can abort sending the request. If the mailbox is ready or pending, the transmitrequest will be aborted immediately. If the mailbox is in the transmitting state, the request to abort may lead to two kinds of results: •...
Page 607: Receiving Management
Figure 26-7 Transmit Mainbox States Highest priority PENDING Ready Non-Highest priority EMPTY Start Write Data to Tx mailbox Transmit succeeded TRANSMIT TXOKM = 1 Receive Management FIFOs with 3 levels depth are used to store received messages. When the application reads the FIFO output mailbox, it reads the first received message in the FIFO.
Page 608: Figure 26-8 Receive Fifo Status
Figure 26-8 Receive FIFO States Valid Mesage Valid Mesage Receive FIFOx Receive FIFOx Receive FIFOx Release Release Mailbox Pending Mailbox Pending Mailbox null Mailbox null Mailbox null Mailbox Pending Mailbox null Mailbox null Mailbox null Valid Mesage Receive FIFOx Receive FIFOx Mailbox Pending Mailbox Pending Valid Mesage...
Page 609: Identifier Filtering
When the FIFO overrun, the FFOVR bit will be set . If the FIFO overrun interrupt is currently enabled (the CAN_INTE.FOVITE bit is set), a FIFO overrun interrupt request will be generated. Identifier Filtering In the CAN network, when basic CAN is in the transmitter state, it broadcasts a message to each node by sending a message to the bus;...
Page 610: Identifier List Mode
Figure 26-9 Filter Bit Width Setting-register Organization 32 bit Mask Mode(CAN_FS1.FSCx = 1;CAN_FM1.FBx = 0) USER ID STDID[10:0]/EXTID[28:18] EXTID[17:0] FiR1 Register filter ID FBC[31:21] FBC[20:3] FBC2 FBC1 FBC0 FiR2 Register filter filter Mask FBC[31:21] FBC[20:3] FBC2 FBC2 FBC2 32 bit List Mode(CAN_FS1.FSCx = 1;CAN_FM1.FBx = 1) USER ID STDID[10:0]/EXTID[28:18] EXTID[17:0]...
Page 611: Filter Matchindex
The filter ID is used to store the identifier format. At this time, there is no mask for comparison, and the mask bit can be used to store one more filter ID. However, at this time, the identifier of the message needs to be exactly the same as the filter ID format, otherwise it will fail to pass the filter.
Page 612: Message Storage
determined by the filter group number, and the filter group with lower number has the higher priority.Within a filter group,the lower the filter number,the higher the priority. Figure 26-10 Examples of Filter Mechanisms Configure: Filter Filter Filter Filter Filter FIFO0_1 FIFO0_2 FIFO1_0 FIFO1_1...
Page 613: Bit Timing
message. Once the software has processed the message, such as reading it out, the software should set the CAN_RFFx.RFFOM bit to release the message, so as to reserve storage space for later messages. Table 26-3 Receive Mailbox Register List Offset from the base address of the receiving mailbox Register name CAN_RMIx CAN_RMDTx...
Page 614: Figure 26-11 Bit Sequence
Figure 26-11 Bit sequence One-bit time SYNC_SEG PROP_SEG 1 PHASE_SEG 1 PHASE_SEG 2 Sampling Point Notes = time period of the APB1 clock, PCLK = (CAN_BTIM.BRTP[9:0] + 1) x t PCLK x (CAN_BTIM.TBS1[3:0] + 1), x (CAN_BTIM.TBS2[2:0] + 1), One-bit time = 1 x t BaudRate = One-bit time 589 / 652...
Page 615: Figure 26-12 Various Can Frames
Figure 26-12 Various CAN Frames 2bit Arbitration Field 12bit Ctrl Field 6bit Data Field 8*Nbit CRC Field 16bit 7bit ID[10:0] Data[N] Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) 44 + 8 * Nbit or Overload Frame CRC Field 16bit 2bit Arbitration Field 32bit Ctrl Field 6bit Data Field 8*Nbit...
Page 616: Can Interrupt
CAN Interrupt Figure 26-13 Event Flag and Interrupt Generation FMPITE0 FFMP0 CAN_RX0_IRQn FFITE0 FFULL0 FOVITE0 FFOVR0 FMPITE1 FFMP1 CAN_RX1_IRQn FFITE1 FFULL1 FOVITE1 FFOVR1 CAN_TX_IRQn RQCPM0 TMEITE CAN_ RQCPM1 TSTS RQCPM2 ERRITE EWGITE EWGFL EPVITE EPVFL ERRINT BOFITE BOFFL CAN_MSTS LECITE CAN_SCE_IRQn 1 LEC 6 WKUITE...
Page 617: Error Management
• Transmit interrupts(CAN_TX_IRQn): Transmit mailbox x becomes empty, and the corresponding CAN_TSTS.RQCPMx bit is set(x=1/2/3). • Error and status change interrupt(CAN_SCE_IRQn): CAN enters sleep mode; Wake-up condition, the start of frame bit (SOF) is monitored on the CAN receiving pin. Error condition, please refer to the CAN error status register (CAN_ESTS) for details of the error.
Page 618: Can Configuration Flow
CAN Configuration Process This chapter will introduce common configuration procedure of CAN while other details like functions of each mode and register bits are revealed in other part of this manual. CAN configuration flow can divided into serval phases. Some of the configurations can be changed anytime as long as prior requirements are satisfyied (e.g., filter value). •...
Page 619: Can Register File
– After some time or after waiting for transmit interrupts, come back to check transmit status in CAN_TSTS. Repeat step 2~3 for new message transmission. • For Reception: User can also change a filter value (CAN_FiRx) when the corresponding filter is deactivated. To deactivate –...
Page 620: Can Register Address Overview
CAN Register Overview Table 26-4 CAN Register Overview Offset Register CAN_MCTRL 000h Reset Value CAN_MSTS 004h Reset Value CAN_TSTS 008h Reset Value CAN_RFF0 00Ch Reset Value CAN_RFF1 010h Reset Value CAN_INTE 014h Reset Value CAN_ESTS RXEC[7:0] TXEC[7:0] 018h Reset Value CAN_BTIM TBS2[2:0] TBS1[3:0]...
Page 621 Offset Register CAN_TMI1 STDID[10:0]/EXTID[28:18] EXTID[17:0] 190h Reset Value CAN_TMDT1 MTIM[15:0] DLC[3:0] 194h Reset Value CAN_TMDL1 DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 198h Reset Value CAN_TMDH1 DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 19Ch Reset Value CAN_TMI2 STDID[10:0]/EXTID[28:18] EXTID[17:0] 1A0h Reset Value CAN_TMDT2 MTIM[15:0] DLC[3:0] 1A4h Reset Value CAN_TMDL2 DATA3[7:0]...
Page 622 Offset Register CAN_RMDL1 DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 1C8h Reset Value CAN_RMDH1 DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 1CCh Reset Value 1D0h 1FFh CAN_FMC 200h Reset Value CAN_FM1 FB[13:0] 204h Reset Value 208h CAN_FS1 FSC[13:0] 20Ch Reset Value 210h CAN_FFA1 FAF[13:0] 214h Reset Value 218h CAN_FA1 FAC[13:0]...
Page 623: Can Control And Status Register
Offset Register CAN_F1B2 FBC[31:0] 24Ch Reset Value CAN_F13B1 FBC[31:0] 2A8h Reset Value CAN_F13B2 FBC[31:0] 2ACh Reset Value CAN Control and Status Register Abbreviations used in register descriptions, please refer to 1.1 section. CAN Master Control Register (CAN_MCTRL) Address offset: 0x00 Reset value: 0x0001 0002 Bit Field Name...
Page 624 Bit Field Name Description 1: enable time trigger communication mode. Notes: For more information about time-triggered communication mode, please refer to 26.4.2: Time-triggered communication mode. ABOM Automatic bus-off management This bit determines the conditions under which the CAN hardware can exit the bus-off state.
Page 625 Bit Field Name Description When the CAN_MCTRL.AWKUM bit is set and the SOF bit is detected in the CAN Rx signal, the hardware clears this bit. This bit is set after reset, that is, CAN is in sleep mode after reset. INIRQ Initialization request clear this bit by software can make CAN exit from initialization mode: when...
Page 626 Bit Field Name Description Notes: When CAN_INTE.SLKITE=0, this bit should not be queried, but the CAN_MSTS.SLPAK bit should be queried to know the sleep state. WKUINT Wakeup interrupt When CAN is in sleep state, once the start of frame bit (SOF) is detected, the hardware will set this bit;...
Page 627 Bit Field Name Description LOWM2 Lowest priority flag for mailbox 2 When multiple mailboxes are waiting to send messages, and the priority of mailbox 2 is the lowest, hardware sets this bit. LOWM1 Lowest priority flag for mailbox 1 When multiple mailboxes are waiting to send messages, and the priority of mailbox 1 is the lowest, hardware sets this bit.
Page 628 Bit Field Name Description When this bit is cleared, other sending status bits (CAN_TSTS.TXOKM2, CAN_TSTS.ALSTM2 and CAN_TSTS.TERRM2 bits) of mailbox 2 are also cleared. ABRQM1 Abort request for mailbox 1 Set this bit, the software can stop the sending request of mailbox 1, and the hardware clears this bit when the sending message of mailbox 1 is idle.
Page 629 Bit Field Name Description RQCPM0 Request completed mailbox 0 When the last request (send or abort) for mailbox 0 was completed, the hardware sets this bit. Writing '1' to this bit by software can clear it; When the hardware receives the send request, it can also clears this bit (the CAN_TMI0.TXRQ bit is set).
Page 630 CAN Receive FIFO 1 Register (CAN_RFF1) Address offset: 0x10 Reset value: 0x0000 0000 Bit Field Name Description 31:6 Reserved Reserved, the reset value must be maintained. RFFOM1 Release FIFO 1 output mailbox. The software releases the output mailbox of the receive FIFO by setting this bit. If the receiving FIFO is empty, it will have no effect on setting this bit, that is, it will be meaningful to set this bit only when there is a message in the FIFO.
Page 631 Bit Field Name Description 31:18 Reserved Reserved, the reset value must be maintained. SLKITE Sleep interrupt enable 0: when the CAN_MSTS.SLAKINT bit is set, no interrupt is generated; 1: when the CAN_MSTS.SLAKINT bit is set, an interrupt is generated. WKUITE Wakeup interrupt enable 0: when CAN_MSTS.WKUINT bit is set, no interrupt is generated;...
Page 632 Bit Field Name Description 0: When CAN_RFF0.FFULL bit is set, no interrupt is generated; 1: When CAN_RFF0.FFULL bit is set, an interrupt is generated. FMPITE0 FIFO 0 message pending interrupt enable 0: When CAN_RFF0.FFMP[1:0] bits are non-0, no interrupt is generated; 1: When CAN_RFF0.FFMP[1:0] bits are not 0, an interrupt is generated.
Page 633 Bit Field Name Description 100: recessive dislocation（CAN transmits recessive but detect dominant on the bus）; 101: dominant dislocation(CAN transmits dominant but detect recessive on the bus); 110: CRC error; 111: Set by software. Reserved Reserved, the reset value must be maintained. BOFFL Bus-off flag When going bus-off, hardware sets this bit.
Page 634: Can Mailbox Register
Bit Field Name Description CAN be extended or shortened by CAN hardware in each bit. x (RSJW[1:0] + 1). Reserved Reserved, the reset value must be maintained. 22:20 TBS2[2:0] Time segment 2 This bit field defines how many time units time period 2 occupies. x (TBS2[2:0] + 1).
Page 635 Bit Field Name Description mailbox. 0: Use standard identifier; 1: Use extended identifiers. RTRQ The Remote transmission request 0: data frame; 1: Remote frame. TXRQ Transmit mailbox request It is set by the software to request to send the data of the mailbox. When the data transmission is completed and the mailbox is empty, hardware clears it.
Page 636 Tx Mailbox Low Byte Data Register(CAN_TMDLx) (x=0..2) When the mailbox is not empty, all bits in this register are write-protected. Address offset: 0x188, 0x198, 0x1A8 Reset value: undefined Bit Field Name Description 31:24 DATA3[7:0] Data byte 3 Data byte 3 of the message. 23:16 DATA2[7:0] Data byte 2...
Page 637 Bit Field Name Description Data byte 5 of the message. DATA4[7:0] Data byte 4 Data byte 4 of the message. Receive FIFO Mailbox Identifier Register (CAN_RMIx) (x=0..1) Address offset: 0x1B0, 0x1C0 Reset value: undefined Notes: All receiving mailbox registers are read-only. Bit Field Name Description...
Page 638 Bit Field Name Description 31:16 MTIM[15:0] Message time stamp This field contains the value of the 16-bit timer at the time of sending the message SOF. 15:8 FMI[7:0] Filter match index Here is the filter serial number of the information transfer stored in the mailbox. For details of identifier filtering, please refer to 26.4.5 section: Identifier filtering.
Page 639: Can Filter Register
Bit Field Name Description 31:24 DATA7[7:0] Data byte 7 Data byte 7 of the message. 23:16 DATA6[7:0] Data byte 6 Data byte 6 of the message. 15:8 DATA5[7:0] Data byte 5 Data byte 5 of the message. DATA4[7:0] Data byte 4 Data byte 4 of the message.
Page 640 Bit Field Name Description 31:28 Reserved Reserved, the reset value must be maintained. 13:0 Filter mode Working mode of filter group X 0: Two 32-bit registers of CAN_FiRx work in identifier mask mode; 1: Two 32-bit registers of CAN_FiRx work in identifier list mode. CAN Filter Scale Register (CAN_FS1) Address offset: 0x20C Reset value: 0x0000 0000...
Page 641 Bit Field Name Description 31:28 Reserved Reserved, the reset value must be maintained. 13:0 FAFx Filter FIFO assignment for filter x After the message is filtered by a certain filter, it will be stored in its associated FIFO. 0: the filter is associated to FIFO0; 1: the filter is associated to FIFO1.
Page 642 Bit Field Name Description 31:0 FBC[31:0] Filter bits Identifier pattern Each bit of the register corresponds to the level of the corresponding bit of the expected identifier. 0: the corresponding bit is expected to be dominant; 1: The corresponding bit is expected to be recessive. Mask bit pattern Each bit of the register indicates whether the corresponding identifier register bit must be consistent with the corresponding bit of the expected identifier.
Page 643: Universal Serial Bus Full-Speed Device Interface (Usb_Fs_Device)
27 Universal Serial Bus Full-speed Device Interface (USB_FS_Device) Introduction Universal serial bus full-speed device interface (USB_FS_Device) module is a peripheral that conforms to the USB2.0 full-speed protocol. It contains the USB PHY of the physical layer and does not require an additional PHY chip.
Page 644: Clock Configuration
Clock Configuration The USB 2.0 protocol specification stipulates that the USB full-speed module uses a fixed 48MHz clock. In order to provide an accurate 48MHz clock to USB_FS_Device, a two-stage clock configuration is required, as follows: • In the first stage, the 48MHz working clock is obtained by accurate frequency division of PLLCLK, so when using USB_FS_Device, it is necessary to ensure that the PLLCLK clock is 48MHz, otherwise USB_FS_Device cannot work normally;...
Page 645: Buffer Description Table
If only endpoint 0 and endpoint 1 are used, the buffer description table only needs 16 bytes. If only endpoint 0 and endpoint 7 are used, the buffer description table needs 64 bytes. Although endpoint 1 to endpoint 6 are not used, but The description table of endpoint 7 starts from 56 bytes, so it will occupy 64 bytes of space.
Page 646: Double-Buffered Endpoints
the very bottom of the buffer description table. The USB module cannot access/modify the data of other endpoint packet buffers other than the currently allocated endpoint packet buffer area, For example: when the endpoint 0 packet receive buffer receives a data larger than the current endpoint 0 packet receive buffer from the PC host, the endpoint 0 only receives data up to the endpoint 0 packet receive buffer size, other redundant data is discarded and a buffer overflow exception occurs.
Page 647: Table 27-1 Dattog And Sw_Buf Definitions
mechanism is introduced to improve the efficiency of bulk transfer, and flow control is implemented. When the unidirectional endpoint uses the double buffer mechanism, both the receive buffer and the transmit buffer on the endpoint will be used, one of the buffers is used by the USB module, and the other buffer is used by the microcontroller, use the data toggle bit in the endpoint register to select which buffer is currently used, and introduce two flags for this: DATTOG and SW_BUF.
Page 648 to ADDR3_RX_0/CNT3_RX_0, after receiving the data from the USB bus, the USB module fills the data into the buffer1 corresponding to ADDR3_RX_1/CNT3_RX_1. When a transaction transfer on the USB bus is completed, the hardware will toggle DATTOG = 0. If the application has not finished processing the data in buffer0 corresponding to ADDR3_RX_0/CNT3_RX_0, the software will not toggle SW_BUF (SW_BUF = 0).
Page 649: Usb Transfer
Figure 27-4 Double Buffered Bulk Endpoint Example The Tx buffer of endpoint 3 DATTOG=1 Application (buffer0) SW_BUF=0 Usb bus The Rx buffer of endpoint 3 (buffer1) 512 bytes packet buffer USB transfer completed hardware toggle: DATTOG=0 SW_BUF == 0 The Tx buffer of endpoint 3 Application DATTOG=0 (buffer0)
Page 650 IN transaction When the host wants to read the data of the USB device, the host sends a PID IN token packet to the USB device. After the USB device receives the IN token packet correctly, if the address matches a configured endpoint address, the USB module will access the corresponding USB_ADDRn_TX and USB_CNTn_TX registers according to the buffer description table entry of the endpoint, and store the values in these two registers to the internal 16-bit ADDR register and CNT register that cannot be accessed by the application.
Page 651: Control Transfer
• If the device address information and endpoint information in the OUT or SETUP token packet are valid, and the status of the endpoint specified in the token packet is VALID, USB device moves data from the hardware buffer that cannot be accessed by the application to the endpoint data packet receiving buffer that can be accessed by the application.
Page 652 direction status remains unchanged; • If it is the last Data stage, before enabling the reception of the last OUT transaction, the software sets the Tx direction status that was not used in the previous Data stage to NAK, so that even if the host starts the Status stage immediately after the last Data stage, the USB device can still remain in the state of waiting for the end of the control transfer, and the Rx direction state is set to VALID, ready to receive the last packet of data;...
Page 653: Figure 27-5 Control Transfer
Figure 27-5 Control Transfer USB bus SETUP(0) DATA0 Tx = NAK Rx = NAK Tx = VALID Tx = STALL Rx = STALL Rx = VALID OUT(1) IN(1) DATA1 DATA1 Tx = STALL Tx = NAK Rx = NAK Rx = STALL Tx = VALID Tx = STALL Rx = STALL...
Page 654: Usb Events And Interrupts
each frame of transmission, but in order to save bandwidth, isochronous transfer does not have a retransmission mechanism, that is, there is no handshake stage, there is no handshake packet after the data packet, so there is no need to use the data toggle mechanism, and the isochronous transfer only transmits the PID DATA0 data packet. The isochronous endpoint uses a double buffer mechanism to reduce the processing pressure of the application.
Page 655: Table 27-4 Resume Event Detection
• Wait for the internal reference voltage to stabilize, because it takes a start-up time to turn on the internal voltage, during which the USB transceiver is in an indeterminate state • Clear the USB_CTRL.FRST bit • Clear the USB_STS register, remove pending interrupts, and enable other units Note: Every time the USB module is enabled after system reset or power-on reset, the pull-up resistor on the DP signal line needs to be configured.
Page 656: Usb Interrupt
Note: The USB_CTRL.RESUM bit can only be set when USB_CTRL.FSUSPD = 1, i.e. the USB module is in suspend state. USB interrupt The USB controller has 3 interrupt lines, which are as follows: • USB low priority interrupt (channel 21): can be triggered by all USB events; •...
Page 657: Usb Endpoint N Register (Usb_Epn), N=[0
Offset Register USB_EP1 EPADDR[3:0] 004h Reserved Reset Value USB_EP2 EPADDR[3:0] 008h Reserved Reset Value USB_EP3 EPADDR[3:0] 00Ch Reserved Reset Value USB_EP4 EPADDR[3:0] 010h Reserved Reset Value USB_EP5 EPADDR[3:0] 014h Reserved Reset Value USB_EP6 EPADDR[3:0] 018h Reserved Reset Value USB_EP7 EPADDR[3:0] 01Ch Reserved Reset Value...
Page 658 Reset value: 0x0000 0000 Bit Field Name Description 31：16 Reserved Reserved, the reset value must be maintained. CTRS_RX Correct receive flag This bit is set by hardware when an OUT or SETUP transaction on this endpoint completes successfully. If USB_CTRL.CTRSM = 1, the corresponding interrupt will be generated.
Page 659 Bit Field Name Description token packet. Note: 、 Software can only read this bit, not write this bit. 、 This bit USB_EPn.SETUP is only valid for control endpoints. 10：9 EP_TYPE[1:0] Endpoint type EP_TYPE[1:0] Description BULK: bulk endpoint CONTROL: control endpoint ISO: isochronous endpoint INTERRUPT: interrupt endpoint EP_KIND...
Page 660: Usb Control Register (Usb_Ctrl)
Bit Field Name Description 、 Software can read and write this bit, but writing 0 is invalid, and writing 1 toggles this bit. 、 Double-buffered bulk endpoint, which controls the transmission status according to the buffer status used, refer to section 27.4.3. 、...
Page 661 Bit Field Name Description CTRSM Correct transfer interrupt enable 0: Disable correct transfer interrupt 1: Enable correct transfer interrupt, when USB_STS.CTRS = 1, an interrupt is generated. PMAOM Packet buffer overflow/underflow interrupt enable 0: Disable packet buffer overflow/underflow interrupt 1: Enable packet buffer overflow/underflow interrupt, when USB_STS.PMAO = 1, an interrupt is generated.
Page 662: Usb Interrupt Status Register (Usb_Sts)
Bit Field Name Description transceiver are still present Note: 、 To enter the low power consumption mode (bus powered device), the software must first set USB_CTRL.FSUSPD, and then set USB_CTRL.LP_MODE. LP_MODE Low power mode 0: No effect 1: Enter low power mode in suspend mode. Activity on the USB bus (wake event) resets this bit (software can also reset this bit) Note: 、...
Page 663 Bit Field Name Description PMAO Packet buffer overflow/underflow interrupt flag This bit is set by hardware when the packet buffer cannot hold all the transmitted data. Notes: (1) Software can read and write this bit, but only writing 0 is valid, and writing 1 is invalid.
Page 664: Usb Frame Number Register (Usb_Fn)
Bit Field Name Description invalid. ESOF Expected start of frame interrupt flag This bit is set by hardware when the USB module does not receive the expected PID SOF token packet. Note: 、 Software can read and write this bit, but only writing 0 is valid, and writing 1 is invalid.
Page 665: Usb Device Address Register (Usb_Addr)
Bit Field Name Description Represents the state of the USB D+ line, and can detect the occurrence of a resume condition in the suspend state. RXDM_STS D- status Represents the state of the USB D- line, and can detect the occurrence of a resume condition in the suspend state.
Page 666: Buffer Description Table
Reset value: 0x0000 0000 Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:3 BUFTAB[12:0] Buffer table This bit holds the starting address of the buffer description table. The buffer description table is used to indicate the address and size of the endpoint packet buffer of each endpoint, aligned by 8 bytes (the lowest 3 bits are 000).
Page 667: Receive Buffer Address Register N (Usb_Addrn_Rx)
Bit Field Name Description 15:10 Reserved Reserved, the reset value must be maintained. 9：0 CNTn_TX[9:0] Number of bytes sent The number of data bytes to send on the next PID IN token packet Note: As shown in Table 27-2 and Table 27-3, the double-buffered IN endpoint and the isochronous IN endpoint require two USB_CNTn_TX registers: USB_CNTn_TX_0 and USB_CNTn_TX_1.
Page 668: Table 27-8 Endpoint Packet Receive Buffer Size Definition
Bit Field Name Description 14:10 NUM_BLK[4:0] Number of memory blocks Records the number of memory blocks allocated to the endpoint packet receive buffer and determines the size of the endpoint packet receive buffer that is ultimately used. For details, please refer to the following Table 27-8. CNTn_RX[9:0] Number of bytes received Written by the USB module to record the actual number of bytes of the latest PID...
Page 669: Debug Support (Dbg)
28 Debug support (DBG) Overview ® N32L40x uses Cortex -M4F core, which integrates hardware debugging module. Support instruction breakpoint (stop when instruction fetches value) and data breakpoint (stop when data access). When the kernel is stopped, the user can view the internal state of the kernel and the external state of the system. After the user's query operation is completed, the kernel and peripherals can be restored, and the corresponding program can continue to be executed.
Page 670: Jtag/Swd Function
• ITM: Instrumentation trace macrocell • FPB: Flash patch breakpoint • DWT: Data watchpointtrigger Reference: • Cortex ® -M4F Technical Reference Manual (TRM) • ARM debugging interface V5 structure specification • ARM CoreSight development tool set (r1p0 version) technical reference manual The system supports low-power mode debugging and debugging of some peripherals.
Page 671: Mcu Debug Function
Table 28-1 Debug Port Pin Debug Port Pin Allocation JTMS/SWDIO PA13 JTCK/SWCLK PA14 JTDI PA15 JTDO NJTRST • When both JTAG debugging interface and SWD debugging interface are enabled, the 5-wire JTAG debugging interface will be used by default after reset. •...
Page 672: Peripherals Debug Support
Peripherals Debug Support When the corresponding bit of the peripheral control bit in the DBG_CTRL register is set to 1, the corresponding peripheral enters the debugging state after the core stops: • Timer peripheral: the timer counter stops and debugs. •...
Page 673: Debug Control Register (Dbg_Ctrl)
Bit Rield Name Description 27:24 SER_NUM[3:0] Series type indication bit. 1 is G series, 2 is L series. 23:20 DEV_NUM_L[3:0] Lower 4 digits of equipment model. Device model consists of 12 bits, including high, medium and low, representing the model of MCU. 19:16 FLASH[3:0] FLASH capacity indicator (capacity: N*32K).
Page 674 Bit Field Name Description WWDG_STOP WWDG debug pause bit. Set or cleared by software. 0: WWDG running state has no effect. 1: Pause the WWDG counter. IWDG_STOP IWDG debug pause bit. Set or cleared by software. 0: IWDG running state has no effect. 1: Pause the IWDG counter.
Page 675: Unique Device Serial Number (Uid)
29 Unique Device Serial Number (UID) Introduction MCU series products have two built-in unique device serial numbers with different lengths, namely 96-bit UID (Unique device ID) and 128-bit UCID (Unique Customer ID). These two device serial numbers are stored in the system configuration block of the flash memory, and the information is programmed during manufacture, and any MCU microcontroller is guaranteed to be unique under any circumstances.
Page 676: 30 Version History
30 Version History Version Date Changes V2.0 2022.07.08 Initial version. Add RTC OUT(PC13) duty cycle description Add PB3 description in Debug mode at chapter 5.2.2 Add MCO output LSE duty cycle at chapter 4.2.13 3.2.3 Chapter LPRUN mode supports CAN/ADC Modify BOR_LEVEL0 in chapter 2.2.4.7 V2.1 2022.09.05...
Page 677 This document is the exclusive property of NSING TECHNOLOGIES PTE. LTD.(Hereinafter referred to as NSING). This document, and the product of NSING described herein (Hereinafter referred to as the Product) are owned by NSING under the laws and treaties of Republic of Singapore and other applicable jurisdictions worldwide. The intellectual properties of the product belong to Nations Technologies Inc.

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