NSING N32G030 Series User Manual

32-bit arm cortex-m0 microcontroller

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N32G030 series

32-bit ARM Cortex

-M0 microcontroller

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Page 1 N32G030 series ® 32-bit ARM Cortex -M0 microcontroller User manual 1 / 526...
Page 2: Table Of Contents
Contents 1 Abbreviations In The Text ............................26 1.1 L ..........................26 BBREVIATIONS EGISTERS 1.2 A ..............................26 VAILABLE ERIPHERALS 2 Memory And Bus Architecture ..........................27 2.1 S ..............................27 YSTEM RCHITECTURE 2.1.1 Bus Architecture ............................27 2.1.2 Bus Address Mapping ............................ 29 2.1.3 Boot Management ............................
Page 3 4.2 C ..............................68 LOCK ONTROL 4.2.1 Clock Tree Diagram ............................71 4.2.2 Hse Clock ............................... 71 4.2.3 Hsi Clock ............................... 72 4.2.4 Pll Clock ................................ 73 4.2.5 Lse Clock ............................... 73 4.2.6 Lsi Clock ................................ 74 4.2.7 System Clock (Sysclk) Selection ........................74 4.2.8 Clock Security System (Clkss) ........................
Page 4 5.3.5 Gpio Port Pull-Up/Pull-Down Register (Gpiox_Pupd) ................120 5.3.6 Gpio Port Input Data Register (Gpiox_Pid) ....................121 5.3.7 Gpio Port Output Data Register (Gpiox_Pod) ..................... 122 5.3.8 Gpio Port Bit Set/Clear Register (Gpiox_Pbsc) ................... 122 5.3.9 Gpio Port Configuration Lock Register (Gpiox_ Plock) ................123 5.3.10 Gpio Alternate Function Low Register (Gpiox_Afl) ................
Page 5 7.4.5 Peripheral/Memory Address Incrementation ....................147 7.4.6 Channel Configuration Procedure ........................ 147 7.4.7 Flow Control ..............................148 7.4.8 Circular Mode .............................. 148 7.4.9 Error Management ............................148 7.4.10 Interrupt ..............................149 7.4.11 Dma Request Mapping ..........................149 7.5 D ................................150 EGISTERS 7.5.1 Dma Register Overview ..........................
Page 6 9.3.7 Pwm Input Mode ............................180 9.3.8 Forced Output Mode ............................181 9.3.9 Output Compare Mode ..........................181 9.3.10 Pwm Mode ..............................183 9.3.11 One-Pulse Mode ............................185 9.3.12 Clearing The Ocxref Signal On An External Event ..................187 9.3.13 Complementary Outputs And Dead-Time Insertion ..................
Page 7 10.3.2 Counter Mode ............................231 10.3.3 Clock Selection ............................236 10.3.4 Capture/Compare Channels ........................240 10.3.5 Input Capture Mode ........................... 243 10.3.6 Pwm Input Mode ............................244 10.3.7 Forced Output Mode..........................245 10.3.8 Output Compare Mode ..........................245 10.3.9 Pwm Mode ..............................247 10.3.10 One-Pulse Mode ............................
Page 8 11.4.1 Register Overview ........................... 285 11.4.2 Control Register 1 (Timx_Ctrl1) ......................285 11.4.3 Dma/Interrupt Enable Registers (Timx_Dinten) ..................286 11.4.4 Status Registers (Timx_Sts) ........................287 11.4.5 Event Generation Registers (Timx_Evtgen) .................... 287 11.4.6 Counters (Timx_Cnt) ..........................288 11.4.7 Prescaler (Timx_Psc) ..........................288 11.4.8 Automatic Reload Register (Timx_Ar) ....................
Page 9 13.4.1 Operate Process ............................312 13.5 I ................................ 313 EGISTERS 13.5.1 Iwdg Register Overview .......................... 313 13.5.2 Iwdg Key Register (Iwdg_Key) ....................... 313 13.5.3 Iwdg Pre-Scaler Register (Iwdg_Prediv) ....................313 13.5.4 Iwdg Reload Register (Iwdg_Relv) ......................314 13.5.5 Iwdg Status Register (Iwdg_Sts) ......................315 14 Window Watchdog (Wwdg) ..........................
Page 10 15.11 A ................................ 335 EGISTERS 15.11.1 Adc Register Overview..........................335 15.11.2 Adc Status Register (Adc_Sts) ........................336 15.11.3 Adc Control Register 1 (Adc_Ctrl1) ......................337 15.11.4 Adc Control Register 2 (Adc_Ctrl2) ......................337 15.11.5 Adc Sampling Time Register 1 (Adc_Sampt1) ..................341 15.11.6 Adc Sampling Time Register 2 (Adc_ Sampt2) ..................
Page 11 17.3.3 Error Conditions Description ........................368 17.3.4 Dma Application ............................369 17.3.5 Packet Error Check(Pec) .......................... 371 17.3.6 Smbus ..............................371 17.4 D ................................373 EBUG 17.5 I ..............................374 NTERRUPT EQUEST 17.6 I ................................374 EGISTERS 17.6.1 c Register Overview ..........................374 17.6.2 c Control Register 1 (I2c_Ctrl1) ......................
Page 12 18.7.6 Usart Control Register 2 Register (Usart_Ctrl2) ..................420 18.7.7 Usart Control Register 3 Register (Usart_Ctrl3) ..................422 18.7.8 Usart Guard Time And Prescaler Register (Usart_Gtp) ................423 19 Low Power Universal Asynchronous Receiver Transmitter (Lpuart) ............... 425 19.1 I ................................
Page 13 20.4.3 s Transmit And Receive Sequence ......................467 20.4.4 Status Flag ............................... 469 20.4.5 Error Flag ..............................470 20.4.6 s Interrupt .............................. 470 20.4.7 Dma Function ............................470 20.5 S ..........................470 EGISTER ESCRIPTION 20.5.1 Spi Register Overview ..........................470 20.5.2 Spi Control Register 1 (Spi_Ctrl1) (Not Used In I s Mode) ..............
Page 14 21.4.5 Rtc Initial Status Register (Rtc_Initsts) ....................494 21.4.6 Rtc Prescaler Register (Rtc_Pre) ......................496 21.4.7 Rtc Wakeup Timer Register (Rtc_Wkupt) ....................496 21.4.8 Rtc Alarm A Register (Rtc_Alarma) ......................497 21.4.9 Rtc Alarm B Register (Rtc_ Alarmb) ....................... 497 21.4.10 Rtc Write Protection Register (Rtc_Wrp) ....................
Page 15 24.3.5 Hdiv Quotient Register (Hdiv_Quotient) ....................517 24.3.6 Hdiv Remainder Register (Hdiv_Remainder) ..................517 24.3.7 Hdiv Divide By Zero Register (Hdiv_Divby0) ..................517 24.4 S ................................ 518 EGISTERS 24.4.1 Sqrt Register Overview ..........................518 24.4.2 Sqrt Control Status Register (Sqrt_Ctrlsts) ....................518 24.4.3 Sqrt Radicand Register (Sqrt_Radicand) ....................
Page 16 List of Table Table 2-1 List Of Peripheral Register Addresses ..................29 Table 2-2 List Of Boot Mode ........................... 31 Table 2-3 Flash Bus Address List........................32 Table 2-4 Option Byte List ..........................36 Table 2-5 Read Protection Configuration List ....................38 Table 2-6 Flash Read-Write-Erase Permission Control Table ..............
Page 17 Table 5-20 OSC_IN/OSC_OUT Alternate Function I/O Remapping............113 Table 5-21 OSC32 Alternate Function Remapping..................113 Table 5-22 OSC Alternate Function Remapping ..................114 Table 5-23 ADC External Trigger Injection Conversion Alternate Function Remapping ....... 114 Table 5-24 ADC External Trigger Regular Conversion Alternate Function Remapping ......114 Table 5-25 ADC ...............................
Page 18 Table 10-3 Timx Internal Trigger Connection ..................... 265 Table 10-4 Output Control Bits Of Standard Ocx Channel ............... 274 Table 11-1 Register Overview ........................285 Table 12-1 Pre-Scaler Division Ratios ......................291 Table 12-2 6 Trigger Inputs Corresponding To LPTIM_CFG.TRGSEL[2:0] Bits ........292 Table 13-1 IWDG Counting Maximum And Minimum Reset Time ............
Page 19 Table 19-2 Parity Frame Format ........................433 Table 19-3 LPUART Interrupt Requests ..................... 437 Table 19-4 LPUART Register Overview ...................... 437 Table 20-1 SPI Interrupt Request ........................ 457 Table 20-2 Use The Standard 8mhz HSE Clock To Get Accurate Audio Frequency....... 467 Table 20-3 I S Interrupt Request ........................
Page 20 List of Figure Figure 2-1 Bus Architecture ..........................28 Figure 2-2 Bus Address Map ........................... 29 Figure 3-1 Power Supply Block Diagram ...................... 52 Figure 3-2 Power On Reset/Power Down Reset Waveform ................. 53 Figure 3-3 PVD Threshold Diagram ......................54 Figure 4-1 System Reset Generation ......................
Page 21 Figure 9-13 Control Circuit In External Clock Mode 1 ................175 Figure 9-14 External Trigger Input Block Diagram ................... 175 Figure 9-15 Control Circuit In External Clock Mode 2 ................176 Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage) ........... 177 Figure 9-17 Capture/Compare Channel 1 Main Circuit ................
Page 22 Figure 10-9 TI2 External Clock Connection Example ................238 Figure 10-10 Control Circuit In External Clock Mode 1 ................239 Figure 10-11 External Trigger Input Block Diagram ................. 239 Figure 10-12 Control Circuit In External Clock Mode 2 ................240 Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage) .........
Page 23 Figure 12-8 Input Waveforms Of Input1 And Input2 When The Decoder Module Is Working Normally ................................. 300 Figure 12-9 Input1 And Input2 Input Waveforms When Decoder Module Is Not Working ....300 Figure 13-1 Functional Block Diagram Of The Independent Watchdog Module ........311 Figure 14-1 Watchdog Block Diagram ......................
Page 24 Figure 18-14 USART Synchronous Transmission Example ............... 405 Figure 18-15 USART Data Clock Timing Example (WL=0) ..............406 Figure 18-16 USART Data Clock Timing Example (WL=1) ..............407 Figure 18-17 RX Data Sampling / Holding Time ..................407 Figure 18-18 IrDA Block Diagram ....................... 409 Figure 18-19 Irda Data Modulation (3/16)-Normal Mode .................
Page 25 Transmitted Discontinuously........................ 453 Figure 20-11 Transmission Using DMA ....................... 455 Figure 20-12 Reception Using DMA ......................456 Figure 20-13 I S Block Diagram ........................458 Figure 20-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0) ......460 Figure 20-15 I S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0) ......
Page 26: Abbreviations In The Text
1 Abbreviations 1.1 List of Abbreviations for Registers The following abbreviations are used in register descriptions: read/write(rw) Software can read and write this bit. read-only(r) Software can only read this bit. write-only(w) Software can only write this bit, and reading this bit will return the reset value.
Page 27: Memory And Bus Architecture
2 Memory and Bus Architecture 2.1 System Architecture 2.1.1 Bus Architecture The main system consists of the following parts: • Two main drive units: − ® Cortex -M0 core system bus − General purpose DMA • Six passive units − Internal SRAM −...
Page 28: Figure 2-1 Bus Architecture
Figure 2-1 Bus Architecture Flash Flash Control Cortex-M0 System Bus Core Fmax:48MHz SRAM NVIC HDIV SQRT System Bus2 AFIO AFIO EXTI EXTI AFIO GPIOA GPIOA SPI1/I2S1 EXTI TIM3 GPIOB GPIOB SPI2 GPIOA IWDG LPTIM GPIOC GPIOC USART1 WWDG GPIOB USART2 GPIOD GPIOF GPIOC...
Page 29: Bus Address Mapping
arbitration uses a Round Robin algorithm. The bus matrix consists of two driver components (CPU system bus, DMA bus) and six slave components (Flash memory interface, SRAM, ADC, and AHB system bus 1/2). Some AHB peripherals are connected to AHB system bus 1 through a bus matrix, and AHB system bus 2 is connected to two AHB2APB Bridges.
Page 30 Address range Peripherals 0x4002_3400 – 0x4002_7FFF Reserved 0x4002_3000 – 0x4002_33FF 0x4002_2400 – 0x4002_2FFF Reserved 0x4002_2000 – 0x4002_23FF FLASH 0x4002_1400 – 0x4002_1FFF Reserved 0x4002_1000 – 0x4002_13FF 0x4002_0C00 – 0x4002_0FFF Reserved 0x4002_0800 – 0x4002_0BFF 0x4002_0400 – 0x4002_07FF SQRT 0x4002_0000 – 0x4002_03FF 0x4001_8000 – 0x4001_FFFF Reserved 0x4001_4800 –...
Page 31: Boot Management
Address range Peripherals 0x4000_1000 – 0x4000_13FF TIM6 0x4000_0C00 – 0x4000_0FFF LPTIM 0x4000_0800 – 0x4000_0BFF Reserved 0x4000_0400 – 0x4000_07FF TIM3 0x4000_0000 – 0x4000_03FF BEEPER 2.1.3 Boot Management 2.1.3.1 Boot address During system startup, you can select the BOOT mode after the reset through the BOOT0 pin and the user option byte BOOT configuration.
Page 32: Memory System
Note: BOOT0 and GPIO are multiplexed, and input drop - down is used by default during power-on. 2.1.3.3 Embedded boot loader The embedded boot loader is stored in System Memory for reprogramming Flash Memory through USART1. The USART1 interface can run not only with an external clock (HSE) but also with the internal 8MHz oscillator (HSI). For further details, please refer to bootstrap manual”.
Page 33 Memory Area Page Name Address Range Size register FLASH_OPTKEY 0x4002_2008 – 0x4002_200B FLASH_STS 0x4002_200C – 0x4002_200F FLASH_CTRL 0x4002_2010 – 0x4002_2013 FLASH_ADD 0x4002_2014 – 0x4002_2017 Reserved 0x4002_2018 – 0x4002_201B FLASH_OB 0x4002_201C – 0x4002_201F FLASH_WRP 0x4002_2020 – 0x4002_2023 FLASH_ECC 0x4002_2024 – 0x4002_2027 The Flash memory is organized into 32-bit wide memory units, which can store codes and data constants.
Page 34 specific sequence is: Firstly, writing KEY1 = 0x45670123 in the FLASH_KEY register. Secondly, writing KEY2 = 0xCDEF89AB in the FLASH_KEY register. If there is an error in sequence or key value, a bus error will be returned and the FLASH_CTRL register will be locked until the next reset.
Page 35 • Wait for the FLASH_ STS.BUSY bit to change to '0'; • Read the written address and verify the data. Note: when the FLASH_STS.BUSY bit is '1', you cannot write to any register. 2.2.1.4.3 Option byte erase and programming The option byte area is programmed differently from the main memory block. The number of option bytes is limited to 7 bytes (2 bytes for write protection, 2 bytes for read protection, 1 byte for configuration and 2 bytes for storing user data).
Page 36: Table 2-4 Option Byte List
2.2.1.7 Option byte Option byte block is mainly used to configure read-write protection, boot mode configuration, software/hardware watchdog and reset options when the system is in power-down or stop mode, and bus address space is allocated to the option byte block for read-write access. They consist of byte with 7 options bytes: 2 byte for write protection, 2 bytes for read protection, 1 byte for configuration option, 2 bytes defined by user, These 7 bytes need to be written through the bus.
Page 37: Write Protection
− USER[3]: nBOOT0 configuration option, which can be queried by FLASH_OB[5] − USER[2]: nRST_PD configuration option, which can be queried through FLASH_OB[4] 0: A reset occurs when PD mode is entered 1: No reset occurs when entering PD mode − USER[1]: nRST_STOP configuration option, which can be queried through FLASH_OB[3] 0: A reset occurs when entering STOP mode 1: No reset occurs when entering the STOP mode...
Page 38: Table 2-5 Read Protection Configuration List
FLASH_CTRL.OPTWE bit by software, and after that, you can write the correct key value series in FLASH_OPTKEY to release the write protection of the option byte. 2.2.1.9 Read protection The user code in Flash can be protected against unauthorized reading by setting read protection. Read protection is set by configuring RDP bytes in the option byte block.
Page 39: Table 2-6 Flash Read-Write-Erase Permission Control Table
Internally, automatically write 0xA5 to read protection option byte; When the system is reset (such as software reset, etc.), the option byte block (including the new RDP value 0xA5) will be reloaded into the system, and the read protection will be released; •...
Page 40 Level Protection Level Perform user Main Flash System Memory SRAM Access area Before 4KB of Flash Read-Write- Read-Write- Read-Write- Read-Write-Erase main memory area Erase Erase Erase After 4KB of Flash Read-Write- Read-Write- Read-Write- Read-Write-Erase main memory area Erase Erase Erase Flash main memory Allow Allow...
Page 41 area mass erase Flash option byte area Read-only Read-only Read-only Flash system memory Prohibit Read-write-erase Prohibit area Read and Read and SRAM (All) Read and write write write Boot Mode SRAM Protect Changing A Perform User Level Protection Level Main Flash System Memory SRAM Access To Areas...
Page 42 Flash system memory Prohibit Prohibit Prohibit Prohibit area Read and Read and Read and SRAM (All) Read and write write write write Before 4KB of Flash main memory area After 4KB of Flash main memory area Flash main memory No modification is area mass erase allowed.
Page 43: Sram
Read and Read and Read and SRAM (All) Read and write write write write Before 4KB of Flash Prohibit Read-only Read-only Read-only main memory area After 4KB of Flash Read-write- Read-write- Prohibit Read-write-erase main memory area erase erase Change to L0 or L2 is Flash main memory Allow Allow...
Page 44: Flash Register Description
In PD mode, data cannot be retained in SRAM; in other operating modes (RUN/LPRUN/SLEEP/STOP), data can be retained normally. The main features are as follows: • The maximum capacity is 8KB in total. • Support byte/half word/word reading and writing. •...
Page 45 2.2.3.2.1 FLASH access control register (FLASH_AC) Address offset: 0x00 Reset value: 0x0000 0030 Bit Field Name Description 31:6 Reserved Reserved,the reset value must be maintained. PRFTBFS Pre-fetch buffer status This bit indicates the state of the pre-fetch buffer 0: The pre-fetch buffer is disabled. 1: The pre-fetch buffer is enabled.
Page 46 Reset value: 0xXXXX XXXX Bit Field Name Description 31:0 OPTKEY Used to unlock the FLASH_CTRL.OPTWE bit. 2.2.3.2.4 FLASH status register (FLASH_STS) Address offset: 0x0C Reset value: 0x0000 0000 Bit Field Name Description 31:8 Reserved Reserved,the reset value must be maintained ECCERR ECC error Error reading FLASH, hardware set this to '1', write '1' to clear this state.
Page 47 2.2.3.2.5 FLASH control register (FLASH_CTRL) Address offset: 0x10 Reset value: 0x0000 0080 Bit Field Name Description 31:14 Reserved Reserved,the reset value must be maintained ECCERRITE ECC error interrupt This bit allows interrupts to occur when the FLASH_STS.ECCERR bit changes to '1'.
Page 48 Bit Field Name Description OPTER Erase option bytes 0: Disable option bytes erase mode; 1: Enable option bytes erase mode. OPTPG Program option bytes 0: Disable option bytes program mode; 1: Enable option bytes program mode. Reserved Reserved,the reset value must be maintained Mass erase 0: Disable mass erase mode;...
Page 49 Bit Field Name Description RDPRT2 Read protection level L2 0: Read protection L2 is disabled. 1: Read protection L2 is enabled. Note: this bit is read-only. 30:26 Reserved Reserved,the reset value must be maintained 25:18 Data1[7:0] Data1 Note: this bit is read-only. 17:10 Data0[7:0] Data0...
Page 50: Power Control (Pwr)
Bit Field Name Description 31:16 Reserved Reserved,the reset value must be maintained 15:0 WRPT Write protection This register contains the write protection option byte loaded by option byte area. 0: Write protection takes effect. 1: Write protection is invalid. Note: these bits are read-only. 2.2.3.2.9 FLASH ECC register (FLASH_ECC) Address offset: 0x24...
Page 51 supplies. Voltage regulator has two modes, normal mode and low power mode. − VDD: 1.8V~5.5V, which mainly provides power input for MR, IO and clock reset system. − VDDA: 1.8V~5.5V, which powers most analog peripherals. For details, please refer to the electrical characteristics section of the relevant data sheet.
Page 52: Power Supply Supervisor
Figure 3-1 Power Supply Block Diagram VDDA domain COMP OPAMP (VDD)VDDA (VSS)VSSA VDD domain eFlash GPIOs Wakeup Logic Voltage regulator 8K SRAM POR/PDR_VDD PVD Digital Peripherals HSE LSE POR/PDR_VDDD HSI LSI PLL 3.1.2 Power Supply Supervisor 3.1.2.1 Power on reset (POR) and power down reset (PDR) Power on reset (POR) and power down reset (PDR) circuits are integrated inside the chip.
Page 53: Figure 3-2 Power On Reset/Power Down Reset Waveform
Figure 3-2 Power On Reset/Power Down Reset Waveform VDD/VDDA 20mV hysteresis Temporization RSTTEMPO RESET 3.1.2.2 Programmable voltage detector (PVD) The PVD monitors the power supply by comparing the VDD voltage with the relevant bits in the power control register (PWR_CTRL). PWR_CTRL.PLS select the threshold of the monitoring voltage. Enable PVD by setting the PWR_CTRL.PVDEN.
Page 54: Nrst
Figure 3-3 PVD Threshold Diagram VDD/VDDA 100mV PVD threshold hysteresis PVD output 3.1.3 NRST NRST is an analog PAD. In STOP mode, PWR detects NRST reset event and asynchronously switches voltage regulator back to normal mode. 3.2 Power Modes The MCU has five power modes: RUN, LPRUN, SLEEP, STOP and PD. Different mode has different performance and power consumption.
Page 55: Table 3-2 Peripheral Running Status
Mode Condition Enter Exit Voltage regulator is running in NORMAL mode. CPU enters SLEEP mode, the core is turned down; SLEEP all peripherals are configurable, regulator CPU returns from ISR Any interrupts wakeup event. is running in NORMAL mode; Interrupts & Events can wakeup CPU. CPU enters deep SLEEP, peripherals clock are disabled.
Page 56: Lprun Mode
TIMER LPTIMER IWDG WWDG Temperature Sensor LPCOMP Systick Timer HDIV/SQRT Gpios 3 Pins Note: (1) Y: Yes (Enable), O: Optional (Disabled by default, Enabled by software), -: Not available. (2) The pins that can wake up from the PD are PA0 (WKUP0), PC13 (WKUP1), PA2 (WKUP2), and NRST. 3.2.1 LPRUN Mode In LPRUN mode, the system clock source can be configured as LSI or LSE by RCC_LSCTRL.LPRUNCLKSEL;...
Page 57: Stop Mode
can run and wake up the CPU when an interrupt or event occurs. 3.2.2.1 Entering SLEEP mode Entering SLEEP mode by executing WFI (Wait For Interrupt) or WFE (Wait For Event) instruction with SCB_SCR.SLEEPDEEP = 0. Depending on the SCB_SCR.SLEEPONEXIT, there are two options for SLEEP mode entry: •...
Page 58: Pd Mode
• External 32.768kHz crystal oscillator (LSE OSC): It can be turned on by RCC_LSCTRL.LSEEN. ADC should be disabled when entering STOP mode to avoid unnecessary power consumption. Note: if the application needs to disable the external clock before entering the STOP mode, it must first switch the system clock to HSI and then deassert RCC_CTRL.HSEEN bit.
Page 59: Peripheral Debug Support
3.3.2 Peripheral Debug Support In addition to supporting debug in low power mode, it also supports some peripherals to stop operating in debug state (TIM1, TIM3, TIM6, TIM8, LPTIM, I C1, I C2, IWDG, WWDG). For specific operations and features, please refer to the description of the other bit fields of the DBG_CTRL register in Chapter 3.4.9.
Page 60 Bit Field Name Description 31:10 Reserved Reserved,the reset value must be maintained. Tune VDDD PDR trigger level during STOP mode. 0: VDDD PDR trigger at 1.0V 1: VDDD PDR trigger at 1.2V Only VDDD POR/PDR can reset this bit. PLS[3:0] PVD level selection.
Page 61: Power Control Status Register (Pwr_Ctrlsts)
Bit Field Name Description PDSTP Enter STOP/PD mode selection Software will set and clear this bit. 0: Enter STOP mode when CPU enters DEEP SLEEP mode. 1: Enter PD mode when CPU enters DEEP SLEEP mode. Reserved Reserved, the reset value must be maintained. 3.4.3 Power Control Status Register (PWR_CTRLSTS) Address offset: 0x04...
Page 62: Power Control Register 2 (Pwr_Ctrl2)
Bit Field Name Description 0: VDD/VDDA is higher than the PVD threshold selected with PWR_CTRL.PLS[3:0] 1: VDD/VDDA is lower than the PVD threshold selected with PWR_CTRL.PLS[3:0] DBGPDF DBGPD mode status bit. When entering DBGPD mode, hardware sets this bit to '1'. Hardware clears this bit when software sets PWR_CTRL.CLRDBGPDF = 1.
Page 63: Power Control Register 4 (Pwr_Ctrl4)
Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. LSIEN Control PWR to enable LSI. 0: PWR continues requesting LSI clock after system enter STOP mode 1: PWR stops requesting LSI clock after system enter STOP mode Reserved Reserved, the reset value must be maintained.
Page 64: Power Control Register 5 (Pwr_Ctrl5)
3.4.7 Power Control Register 5 (PWR_CTRL5) Address offset: 0x24 Reset value: 0x0000 0007 Bit Field Name Description 31:4 Reserved Reserved, the reset value must be maintained. SLPMRSEL VDDD output voltage selection after system enters STOP mode. Before configuring these bits, software must first configure PWR_CTRL6.SLPMREN = '11'. 00: Reserved 01: VDDD output voltage is 1.5V 10: Reserved...
Page 65 Reset value: 0x0000 0000 Only VDDD POR/PDR can reset this register. Only after connecting to the Debugger, software can write access to this register. Bit Field Name Description 31:21 Reserved Reserved, the reset value must be maintained. TIM8STP TIM8 stops operating when core enters debug state. This bit is set or cleared by software.
Page 66 Bit Field Name Description WWDGSTP WWDG stops operating when core enters debug state. This bit is set or cleared by software. 0: The counter of WWDG operates normally 1: The counter of WWDG stops operating IWDGSTP IWDG stops operating when core enters debug state. This bit is set or cleared by software.
Page 67: Reset And Clock Control (Rcc)
4 Reset and Clock Control (RCC) 4.1 Reset Control Unit N32G030 supports the following two types of reset: ⚫ Power Reset ⚫ System Reset 4.1.1 Power Reset A power reset occurs in the following circumstances: • Power-on/ Power-down reset (POR/PDR reset). •...
Page 68: Clock Control Unit
• EMC reset The reset source can be identified by checking the reset flags in the Control/Status register (RCC_CTRLSTS). 4.1.2.1 Software reset A software reset can be generated by setting the SYSRESETREQ bit in Cortex ® -M0 Application Interrupt and Reset ®...
Page 69 • HSE oscillator clock • PLL clock • LSI oscillator clock • LSE oscillator clock The devices have the following two secondary clock sources: • LSI: 30 kHz low-speed internal RC can be used to drive independent watchdog (IWDG) and drive RTC,LPTIMER and LPUART through program selection.
Page 70 • Flash memory programming interface clock is always the HSI clock RCC provides Cortex system timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. Either the above clock or the Cortex clock (HCLK) can be selected to drive the SysTick by programming the SysTick control and status registers.
Page 71: Clock Tree Diagram
4.2.1 Clock Tree Diagram Figure 4-2 Clock Tree Clock Tree Legend: ADC1MSEL HSE = High-speed external clock signal HSI = High-speed internal clock signal ADC 1M LSE = Low-speed external clock signal Prescaler ADC_CLK 1M LSI = Low-speed internal clock signal /1/2/ /32 FLASH_CLK to Flash programming...
Page 72: Hsi Clock
⚫ HSE user external clock(Input through the PF0 pin) In HSE bypass mode or crystal mode, RCC_CTRL.HSEEN needs to be set to 1. If RCC_CTRL.HSEEN=0, HSE will be turned off. To reduce distortion of the clock output and shorten the start-up settling time, the crystal/ceramic resonator and load capacitor must be placed as close as possible to the oscillator pins of the chip.
Page 73: Pll Clock
the HSI clock frequency of each chip has been calibrated to 1% (25°C) before leaving the factory. If the user application is subject to voltage or temperature variations, this may affect the accuracy of the RC oscillator. The HSI frequency can be trimmed by using the RCC_CTRL.HSITRIM[4:0] bits. The RCC_CTRL.HSIRDF bit flag indicates if the HSI RC oscillator is stable.
Page 74: Lsi Clock
4.2.5.1 LSE crystal clock source The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It provides a low-power and accurate clock source for real-time clock or other timing functions. The LSE clock can be switched on and switched off by setting the RCC_LSCTRL.LSEEN bit. The RCC_LSCTRL.LSERD bit flag indicates if the LSE clock is stable.
Page 75: Rtc Clock
clock, and the PLL clock is used as the system clock), the clock failure will cause a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If HSE clock (divided or not) is selected as PLL input clock then upon HSE clock failure, the PLL will be turned off.
Page 76: Rcc Registers
The selection is controlled by RCC_CFG.MCO[2:0] bits. 4.3 RCC Registers 4.3.1 RCC Register Overview Table 4-1 RCC Register Overview Offset Register RCC_CTRL HSITRIM[4:0] 000h Reserved Reserved Reset Value MCORES PLLOUTDIV PLLPRE PLLMULFCT APB2PRES APB1PRES AHBPRES SCLKSW RCC_CFG SCLKSTS2 [3:0] [2:0] [1:0] [1:0] [3:0]...
Page 77: Clock Control Register (Rcc_Ctrl)
RCC_AHBPRST 028h Reserved Reserved Reserved Reset Value LPUARTSEL LPTIMSEL ADC1MPRES ADCPLLPRES ADCHPRES RCC_CFG2 [2:0] [2:0] [4:0] [4:0] [3:0] 02Ch Reserved Reserved Reset Value RCC_EMCCTRL 030h Reserved Reset Value 4.3.2 Clock Control Register (RCC_CTRL) Address offset: 0x00 Reset value: 0x0080 0083 Bit Field Name Description...
Page 78: Clock Configuration Register (Rcc_Cfg)
Bit Field Name Description Set and cleared by software. This bit can only be written when the HSE oscillator is disabled. 0: Disable the bypass function of HSE oscillator 1: Enable the bypass function of HSE oscillator HSERDF External high-speed clock ready flag Set by hardware once HSE is ready.
Page 79 Bit Field Name Description 31:28 MCOPRES[3:0] MCO prescaler Set and cleared by software. 0010: PLL clock divided by 2 0011: PLL clock divided by 3 0100: PLL clock divided by 4 0101: PLL clock divided by 5 0110: PLL clock divided by 6 0111: PLL clock divided by 7 1000: PLL clock divided by 8 1001: PLL clock divided by 9...
Page 80 Bit Field Name Description 00: PLL input clock divided by 1 01: PLL input clock divided by 2 10: PLL input clock divided by 3 11: PLL input clock divided by 4 19:16 PLLMULFCT[3:0] PLL multiplication factor. Set and clear through software. This bit can only be written when the PLL is off. *M /N The actual PLL M value should be this register value + 3, M = PLLMULFCT + 3.
Page 81: Clock Interrupt Register (Rcc_Clkint)
Bit Field Name Description Set and cleared by hardware to indicate which clock source is used as system clock 000: HSI oscillator used as system clock 001: HSE oscillator used as system clock 010: PLL used as system clock 011: LSE used as system clock 100: LSI used as system clock SCLKSW[2:0] System clock switch...
Page 82 Bit Field Name Description 0: Not used 1: Clear HSERDIF flag HSIRDICLR HSI ready interrupt clear Set by the software to clear the HSIRDIF flag. 0: Not used 1: Clear the HSIRDIF flag LSERDICLR LSE ready interrupt clear Set by the software to clear the LSERDIF flag. 0: Not used 1: Clear LSERDIF flag LSIRDICLR...
Page 83: Apb2 Peripheral Reset Register (Rcc_Apb2Prst)
Bit Field Name Description 0: No clock security system interrupt caused by HSE clock failure 1: Clock security system interrupt caused by HSE clock failure Reserved Reserved, the reset value must be maintained. RAMCPIF RAMC parity interrupt status. Set by hardware, set by software to clear PERRCLR 1: RAMC parity error occurs 0: No RAMC parity error occurs PLLRDIF...
Page 84 Bit Field Name Description 31:15 Reserved Reserved, the reset value must be maintained. USART1RST USART1 reset Set and cleared by software. 0: Clear reset 1: Reset USART1 TIM8RST TIM8 reset Set and cleared by software. 0: Clear reset 1: Reset TIM8 TIM1RST TIM1 reset Set and cleared by software.
Page 85: Apb1 Peripheral Reset Register (Rcc_Apb1Prst)
Bit Field Name Description 0: Clear reset 1: Reset alternate function IO 4.3.6 APB1 Peripheral Reset Register (RCC_APB1PRST) Address offset: 0x10 Reset value: 0x0000 0000 Bit Field Name Description 31:29 Reserved Reserved, the reset value must be maintained PWRRST Power interface reset Set and cleared by software.
Page 86: Ahb Peripheral Clock Enable Register (Rcc_Ahbpclken)
Bit Field Name Description BEEPRST BEEPER reset Set and cleared by software. 0: Clear reset 1: Reset BEEPER TIM6RST 4.3.6.1 TIM6 timer reset Set and cleared by software. 0: Clear reset 1: Reset TIM6 timer LPTIMRST LPTIMR timer reset Set and cleared by software. 0: Clear reset 1: Reset LPTIM Reserved...
Page 87: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Pclken)
Bit Field Name Description 0: Disable CRC clock 1: Enable CRC clock HSQRTEN HSQRT clock enable Set and cleared by software. 0: Disable HSQRT clock 1: Enable HSQRT clock FLITFEN Flash interface clock enable Set and cleared by software. 0: Disable the flash interface clock 1: Enable the flash interface clock Reserved Reserved, the reset value must be maintained.
Page 88: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Pclken)
Bit Field Name Description 0: Disable TIM1 clock 1: Enable TIM1 clock Reserved Reserved, the reset value must be maintained. SPI2EN SPI2 clock enable Set and cleared by software. 0: Disable SPI2 clock 1: Enable SPI2 clock SPI1EN SPI1 clock enable Set and cleared by software.
Page 89 Bit Field Name Description OPAMPEN OPAMP clock enable Set and cleared by software. 0: Disable OPAMP clock 1: Enable OPAMP clock 30:29 Reserved Reserved, the reset value must be maintained PWREN Power interface clock enable Set and cleared by software. 0: Disable the power interface clock 1: Enable the power interface clock 27:23...
Page 90: Low Speed Clock Control Register (Rcc_Lsctrl)
Bit Field Name Description COMPEN Comparator clock enable 0: Disable the comparator clock 1: Enable the comparator clock Reserved Reserved, the reset value must be maintained BEEPEN BEEPER clock enable Set and cleared by software. 0: Disable BEEPER clock 1: Enable BEEPER clock TIM6EN TIM6 timer clock enable Set and cleared by software.
Page 91: Control/Status Register (Rcc_Ctrlsts)
Bit Field Name Description 1: LPRUN mode selects LSE clock RTCRST RTC software reset 0: Clear reset 1: Reset RTC RTCEN RTC clock enable Set and clear by software 0: RTC clock disabled 1: RTC clock is enabled RTCSEL[1:0] RTC clock source selection. The software sets these bits to select the RTC clock source.
Page 92 Bit Field Name Description 31:12 Reserved Reserved, the reset value must be maintained EMCCLPRSTF EMCCLAMP reset flag Set by hardware when EMCCLAMP is reset. It is cleared by writing RMRSTF bit or por_rst_n reset. 0: No EMCCLAMP reset occurred 1: EMCCLAMP reset occurred EMCGBRSTF EMCGB reset flag Set by hardware when EMCGB is reset.
Page 93: Ahb Peripheral Reset Register (Rcc_Ahbprst)
Bit Field Name Description Set by hardware when POR/PDR is reset. Cleared by writing to the RMRSTF bit 0: No POR/PDR reset occurred 1: POR/PDR reset occurred PINRSTF External pin reset flag Set by hardware when a reset from the NRST pin occurs. It is cleared by writing RMRSTF bit or por_rst_n reset.
Page 94: Clock Configuration Register 2(Rcc_Cfg2)
Bit Field Name Description 0: Clear reset 1: Reset HDIV Reserved Reserved, the reset value must be maintained. HSQRTRST HSQRT reset Set and cleared by software. 0: Clear reset 1: Reset HSQRT Reserved Reserved, the reset value must be maintained. 4.3.13 Clock Configuration Register 2(RCC_CFG2) Address offset: 0x2c Reset value: 0x0000 3800...
Page 95 Bit Field Name Description 101: Select COMP output Others: Not allowed, and no clock will be generated 20:16 Reserved Reserved, the reset value must be maintained. 15:11 ADC1MPRE[4:0] ADC 1M clock prescaler Set and cleared by software to configure the division factor of ADC 1M clock source. 00000: ADC 1M clock source not divided 00001: ADC 1M clock source divided by 2 00010: ADC 1M clock source divided by 3...
Page 96: Emc Control Register 3 (Rcc_Emcctrl)
Bit Field Name Description 0101: HCLK clock divided by 8 0110: HCLK clock divided by 10 0111: HCLK clock divided by 12 1000: HCLK clock divided by 16 Others: HCLK clock divided by 32 4.3.14 EMC Control Register 3 (RCC_EMCCTRL) Address offset: 0x30 Reset value: 0x0000 0000 Bit Field...
Page 97 Bit Field Name Description Set and cleared by software. and reset by por_rst_n 0: Disable reset request 1: Enable reset request GBNRST0 GBN0 reset Set and cleared by software. and reset by por_rst_n 0: Disable reset request 1: Enable reset request CLPRST3 EMC clamp3 reset Set and cleared by software.
Page 98 Bit Field Name Description GBNDET2 GBN2 detection enble Set and cleared by software. and reset by por_rst_n 0: Disable detection 1: Enable detection GBNDET1 GBN1 detection enble Set and cleared by software. and reset by por_rst_n 0: Disable detection 1: Enable detection GBNDET0 GBN0 detection enble Set and cleared by software.
Page 99: Gpio And Afio
5 GPIO and AFIO 5.1 Summary This design supports 40 GPIO, divided into 4 groups (GPIOA/GPIOB/GPIOC/ GPIOF), GPIOA and GPIOB each has 16 pins, GPIOC has 3 pins and GPIOF has 5 pins. GPIO ports share pins with other multiplexed peripherals, allowing users to configure them flexibly according to their needs.
Page 100: Function Description
Figure 5-1 Basic Structure Of I/O Ports Write Bit set/clear register P-MOS Output data register Output Read / Write control Pull N-MOS diode Alternate function output From on-chip peripheral Push-pull, open-drain or disabled I/O Pin Pull diode down On / Off Read Input data register...
Page 101: Table 5-2 I/O List Of Functional Features Of The Pin
PMODE[1:0] POTYPE PUPD[1:0] I/O Configuration Input pull-up Input pull-down Reserved Analog Reserved In addition, the GPIOx_DS.DSy bit can be used to configure the high/low drive strength, and the GPIOx_SR.SRy bit can be used to configure the high/low slew rate. The input and output characteristics of I/O under different configurations are shown in the following table: Table 5-2 I/O List Of Functional Features Of The Pin Feature GPIO Input...
Page 102: Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode
• Read access to the input data register provides the I/O Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode. Write Bit set/clear register Output data register Pull Read / Write diode I/O Pin Pull diode down Read Input data register TTL Schmitt trigger 5.2.1.2...
Page 103: Figure 5-3 Output Mode
Figure 5-3 Output Mode P-MOS Write Bit set/clear register Output data Output register control Pull N-MOS diode Read / Write Push-pull or open-drain I/O Pin Pull diode down Read Input data register TTL Schmitt trigger 5.2.1.3 Alternate function mode When the I/O port is configured as alternate function mode: •...
Page 104: Status After Reset
Figure 5-4 Alternate Function Mode Write Bit set/clear register P-MOS Output data register Output Read / Write control Pull N-MOS diode From on-chip peripheral Alternate function output Push-pull or open-drain I/O Pin Pull diode down Read Input data register TTL Schmitt trigger Alternate function input To on-chip peripheral 5.2.1.4 Analog function mode...
Page 105: Individual Bit Setting And Bit Clearing
function mode (GPIOx_PMODE.PMODEx [1:0] = 11b). However, there are the following exceptions to the signal. • NRST has no GPIO function by default: − NRST pull-up input • After reset, the SWD pins related to the debugging system are enabled by default:: −...
Page 106: Table 5-3 I/O List Of Functional Features Of The Pin
peripheral, if it is remapped to a different pin, then the input is remapping choose one of multiple, and the output will be connected to the remapped position, and the original position will be disconnected). 5.2.5.2 SWD alternate function I/O remapping Table 5-3 I/O List Of Functional Features Of The Pin Alternate Function Remapping...
Page 107: Table 5-6 Tim3 Alternate Function I/O Remapping
Alternate Function Remapping TIM8_CH1 PB12 TIM8_CH2 PB13 TIM8_CH3 PB11 PB14 TIM8_CH4 PB15 TIM8_CH1N TIM8_CH2N TIM8_CH3N PB15 5.2.5.6 TIM3 alternate function I/O remapping Table 5-6 TIM3 Alternate Function I/O Remapping Alternate Function Remapping AF10 TIM3_ETR PB10 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 107 / 526...
Page 108: Table 5-7 Lptim Alternate Function I/O Remapping
5.2.5.7 LPTIM alternate function I/O remapping Table 5-7 LPTIM Alternate Function I/O Remapping Alternate Function Remapping LPTIM _ETR LPTIM _IN1 LPTIM _IN2 LPTIM _OUT 5.2.5.8 Usartx alternate function I/O remapping 5.2.5.9 USART1 alternate function I/O remapping Table 5-8 USART1 Alternate Function I/O Remapping Alternate Function Remapping USART1_CTS...
Page 109: Table 5-10 Lpuart Alternate Function I/O Remapping
Alternate Function Remapping USART2_TX AF10 PA14 USART2_RX PA10 AF10 PA13 PA15 USART2_CK 5.2.5.11 LPUART alternate function I/O remapping Table 5-10 LPUART Alternate Function I/O Remapping Alternate Function Remapping LPUART_CTS PB13 PA15 LPUART_RTS PB14 AF10 LPUART_TX PB10 AF11 LPUART_RX PB11 5.2.5.12 I2Cx alternate function I/O remapping 5.2.5.13 I2C1 alternate function I/O remapping Table 5-11 I2C1 Alternate Function I/O Remapping Alternate Function...
Page 110: Table 5-12 I2C2 Alternate Function I/O Remapping
Alternate Function Remapping PB10 PA10 PA13 C1_SDA PB11 PA14 C1_SMBA 5.2.5.14 I2C2 alternate function I/O remapping Table 5-12 I2C2 Alternate Function I/O Remapping Alternate Function Remapping PA11 C2_SCL PB10 PB13 PA10 PA12 C2_SDA PB11 PB14 C2_SMBA 110 / 526...
Page 111: Table 5-13 Spi1/I2S Alternate Function I/O Remapping
5.2.5.15 SPIx/I2S alternate function I/O remapping 5.2.5.16 SPI1/I2S alternate function I/O remapping Table 5-13 SPI1/I S Alternate Function I/O Remapping Alternate Function Remapping SPI1_I S_NSS_WS PA15 PB12 SPI1_I S_SCLK_CK PA13 PB13 SPI1_I S_MISO_MCK PA14 PB14 SPI1_I S_MOSI_SD PB10 PB15 111 / 526...
Page 112: Table 5-14 Spi2 Alternate Function I/O Remapping
5.2.5.16.1 SPI2 alternate function I/O remapping Table 5-14 SPI2 Alternate Function I/O Remapping Alternate Function Remapping SPI2_ NSS PB12 SPI2_ SCLK PB10 PB13 PA10 SPI2_ MISO PA12 PB14 PA11 SPI2 _MOSI PB15 5.2.5.17 COMP alternate function I/O remapping Table 5-15 COMP Alternate Function I/O Remapping Alternate Function Remapping COMP_OUT...
Page 113: Table 5-18 Rtc Alternate Function I/O Remapping
Alternate Function Remapping PB3~PB4 PB11~PB12 5.2.5.20 RTC alternate function I/O remapping PC13 can be used for RTC TAMPER1 tamper pin, RTC Timestamp, RTC output (RTC alarm, Wakeup event or calibration output (256Hz or 1Hz)). PA0 can be used for RTC TAMPER2 tamper pin. PA10 or PB15 can be used for RTC REFCLKIN reference clock input pin.
Page 114: Table 5-22 Osc Alternate Function Remapping
entering the low power mode (PD). LSE crystal mode RCC_LSCTRL.LSEEN bit is enabled, alternate mode is on Analog function mode RCC_LSCTRL.LSEEN bit is disabled, RCC_LSCTRL.LSEBP is LSE external clock mode Input pull-down enabled, alternate mode is enabled The default is analog function mode; PC14 and PC15 decide which mode and I/O function they are in according to RCC_LSCTRL.LSEEN, RCC_LSCTRL.LSEBP, chip mode signal, GPIOx_PMODE, GPIOx_POTYPE and GPIOx_PUPD.
Page 115: I/O Configuration Of Peripherals
5.2.6 I/O Configuration Of Peripherals Table 5-25 ADC PAD Configuration Analog function mode Table 5-26 PVD PAD Configuration PVD_IN Analog function mode Table 5-27 TIM1/TIM8 TIM Pin Configuration PAD Configuration Mode Channel x input capture Alternate function push-pull TIM1/8_CHx Output compare channel x Alternate function push-pull TIM1/8_CHxN Complementary output channel x...
Page 116: Table 5-31 I2C
Table 5-31 I C Pin Configuration PAD Configuration Cx_SCL C clock Alternate function open-drain Cx_SDA C data Alternate function open-drain Cx_SMBA SMBA data Alternate function open-drain Table 5-32 SPI SPI Pin Configuration PAD Configuration Master mode Alternate function push-pull SPIx_SCLK Slave mode Alternate function push-pull Full duplex mode / Master mode...
Page 117: Gpio Locking Mechanism
Alternate Function Pad Configuration EVENTOUT Event output Alternate function push-pull RTC_OUT RTC output Alternate function push-pull Clock output Alternate function push-pull Input floating or input with pull-up or input EXTI input line External interrupt input with pull-down 5.2.7 GPIO Locking Mechanism The locking mechanism is used to freeze the I/O configuration to prevent accidental changes.
Page 118 Offset Register Reset Value Reserved Reserved Reserved GPIOx_POTYPE x=A,B,C,F Reserved x=A,B Reserved 004h Reset Value Reserved Reserved Reserved Reserved GPIOx_SR x=A,B,C,F Reserved x=A,B Reserved 008h Reset Value Reserved Reserved Reserved Reserved GPIOx_PUPD x=A,B,C,F 00Ch Reset Value Reserved Reserved Reserved GPIOx_PID x=A,B,C,F Reserved x=A,B...
Page 119: Gpio Port Mode Description Register (Gpiox_Pmode)
Offset Register Reserved GPIOx_PBC x=A,B,C,F Reserved x=A,B Reserved 028h Reset Value Reserved Reserved Reserved Reserved GPIOx_DS x=A,B,C,F Reserved x=A,B Reserved 02Ch Reset Value Reserved Reserved Reserved Reserved 5.3.2 GPIO Port Mode Description Register (GPIOx_PMODE) Offset address : 0x00 Reset value : 0xEBFF FFFF (x=A); 0xFFFF FFFF (x=B); 0xFC00 0000 (x=C); 0x0000 F03F (x=F) Bit Field Name Description...
Page 120: Gpio Slew Rate Configuration Register (Gpiox_Sr)
Bit Field Name Description 31:16 Reserved Reserved,the reset value must be maintained 15:0 POTy Output type of port GPIOx (x = A,B,C,F) pin PINy: 0: Output push-pull mode (state after reset) 1: Output open-drain mode Note: when x = A,B, y = 0…15; When x = C, y = 13, 14, 15, the remaining bits are reserved, and the reserved bits are read-only;...
Page 121: Gpio Port Input Data Register (Gpiox_Pid)
Bit Field Name Description 31:30 PUPDy[1:0] Pull-up and pull-down mode of port GPIOx (x = A,B,C,D,F) pin PINy: 29:28 00: no pull-up/pull-down 27:26 01: Pull up 25:24 10: Pull down 23:22 11: Reserved 21:20 Note: when x = A,B, y = 0…15; 19:18 When x = C, y = 13, 14, 15, the remaining bits are reserved, and the reserved bits are 17:16...
Page 122: Gpio Port Output Data Register (Gpiox_Pod)
5.3.7 GPIO Port Output Data Register (GPIOx_POD) Offset address : 0x14 Reset value : 0x0000 0000 (x=A,B,C,F) Bit Field Name Description 31:16 Reserved Reserved,the reset value must be maintained 15:0 PODy Output data of port GPIOx (x = A,B,C,F) pin PINy These bits are readable or writable by software, and the corresponding POD bits can be independently set/cleared.
Page 123: Gpio Port Configuration Lock Register (Gpiox_ Plock)
Bit Field Name Description These bits can only be written. 0: Does not affect the corresponding PODy bit 1: Set the corresponding PODy bit to 1 Note: when x = A,B, y = 0…15; When x = C, y = 13, 14, 15, the remaining bits are reserved, and the reserved bits are read-only;...
Page 124: Gpio Alternate Function Low Register (Gpiox_Afl)
Bit Field Name Description read-only. 5.3.10 GPIO Alternate Function Low Register (GPIOx_AFL) Offset address : 0x20 Reset value : 0xFFFF FFFF (x = A,B); 0x0000 0000 (x = C); 0xFF00 0FFF (x = F) Bit Field Name Description 31:28 AFSELy[3:0] Alternate function configuration bits for port GPIOx (x = A,B,C,F) pins PINy (y = 27:24 0…7)
Page 125: Gpio Port Bit Clear Register (Gpiox_Pbc)
Bit Field Name Description 31:28 AFSELy[3:0] Alternate Function Configuration Bits for Port GPIOx (x = A,B,C,F) Pins PINy (y = 27:24 8…15) 23:20 0000: AF0 19:16 0001: AF1 15:12 0010: AF2 11:8 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 1000: AF8 1001: AF9...
Page 126: Gpio Driver Strength Configuration Register (Gpiox_ Ds)
Bit Field Name Description 0: No effect on the corresponding PODy bit 1: Clear the corresponding PODy bit to 0 Note: when x = A,B, y = 0…15; When x = C, y = 13, 14, 15, the remaining bits are reserved, and the reserved bits are read-only;...
Page 127: Afio Configuration Register (Afio_Cfg)
Offset Register EXTI11_CFG EXTI10_CFG EXTI9_CFG EXTI8_CFG AFIO_EXTI_CFG3 010h Reserved [3:0] [3:0] [3:0] [3:0] Reset Value EXTI15_CFG EXTI14_CFG EXTI13_CFG EXTI12_CFG AFIO_EXTI_CFG4 014h Reserved [3:0] [3:0] [3:0] [3:0] Reset Value 5.4.2 AFIO Configuration Register (AFIO_CFG) Offset address : 0x00 Reset value : 0x0000 0000 Bit Field Name Description...
Page 128: Afio External Interrupt Configuration Register 1 (Afio_Exti_Cfg1)
Bit Field Name Description 0001: Select EXTI1 rugular to convert external trigger 1111: Select EXTI15 rugular to convert external trigger 10:0 Reserved Reserved,the reset value must be maintained 5.4.3 AFIO External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1) Offset address : 0x08 Reset value : 0x0000 0000 Bit Field Name...
Page 129: Afio External Interrupt Configuration Register 3 (Afio_Exti_Cfg3)
Bit Field Name Description 31:30 Reserved Reserved,the reset value must be maintained 15:0 EXTIx_CFG[3:0] EXTIx configuration (x = 4...7) These bits are readable and writable by software and are used to select the input source for the EXTIx external interrupt. EXTI4 configuration: 0000: PA4 pin 0001: PB4 pin...
Page 130: Afio External Interrupt Configuration Register 4 (Afio_Exti_Cfg4)
Bit Field Name Description 0101: reserved Other: reserved 5.4.6 AFIO External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4) Offset address : 0x14 Reset value : 0x0000 0000 Bit Field Name Description 31:30 Reserved Reserved,the reset value must be maintained 15:0 EXTIx_CFG[3:0] EXTIx configuration (x = 12...15) These bits are readable and writable by software and are used to select the input source for the EXTIx external interrupt.
Page 131: Systick Calibration Value Register
processing and efficient processing of late interrupts. The nested vectored interrupt controller manages interrupts including core exceptions. 6.1.1 Systick Calibration Value Register The system tick calibration value is fixed at 6000. When the system tick clock is set to 6MHz (the maximum value of HCLK/8), 1 ms time base is generated.
Page 132 Position Priority Priority Type Name Description Address communication interrupt Settable TIM8_CC TIM8 capture comparison interrupt 0x0000 008C LPTIM (connected to EXTI line 23) Settable LPTIM/TIM6 0x0000 0090 /TIM6 global interrupt Settable ADC global interrupt 0x0000 0094 Settable SPI2 SPI2 global interrupt 0x0000 0098 Settable C1 global interruption...
Page 133: External Interrupt/Event Controller (Exti)
6.2 External Interrupt/Event Controller (EXTI) 6.2.1 Introduction The extended interrupt/event controller contains 24 edge detection circuits that trigger interrupt/event triggers. Each input line can be independently configured with pulse or pending input types, and three trigger event types including rising edge, falling edge or double edge, which can also be independently shielded. Interrupt requests that hold the state line in the pending register can be cleared by writing '1' in the corresponding bit of the pending register.
Page 134: Functional Description
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram AMBA APB BUS Pheripheral Interface PCLK2 Falling Rising Software Interrupt Pending Trigger Trigger Interrupt Mask Request Seletion Selection Event register register register register register To NVIC interrupt controller Pulse Input Edge detect circuit generator Line Event...
Page 135 − Configure the mask bit (EXTI_IMASK) for 24 interrupt lines. − Configure the trigger configuration bits of selected interrupt line(EXTI_RT_CFG and EXTI_FT_CFG); − Configure the enable and mask bits of the NVIC interrupt channel corresponding to the externed interrupt controller so that the requests in the 24 interrupt lines can be correctly responded to. •...
Page 136: Exti Line Mapping
6.2.4 EXTI Line Mapping Figure 6-2 External Interrupt Generic I/O Mapping EXTI1_CFG[3:0] Control EXTI2_CFG[3:0] Control EXTI3_CFG[3:0] Control EXTI0_CFG[3:0] Control AFIO_EXTI_CFG1 EXTI0 EXTI1 EXTI3 EXTI2 Register EXTI4_CFG[3:0] Control EXTI5_CFG[3:0] Control EXTI6_CFG[3:0] Control EXTI7_CFG[3:0] Control EXTI7 EXTI4 EXTI5 AFIO_EXTI_CFG2 EXTI6 Register EXTI9_CFG[3:0] Control EXTI10_CFG[3:0] Control EXTI11_CFG[3:0] Control EXTI8_CFG[3:0] Control...
Page 137 • EXTI line 19 is connected to the RTC tamper for detection or timestamp wake up event • EXTI line 20 is connected to the RTC wake up event • EXTI line 21 is reserved • EXTI line 22 is connected to the LPUART wake up event •...
Page 138: Exti Registers
6.3 Exti Registers EXTI base address: 0x40010400 6.3.1 EXTI Register Overview Table 6-2 EXTI Register Overview Offset Register EXTI_IMASK 000h Reserved Reset Value EXTI_EMASK 004h Reserved Reset Value EXTI_RT_CFG 008h Reserved Reset Value EXTI_FT_CFG 00Ch Reserved Reset Value EXTI_SWIE 010h Reserved Reset Value EXTI_PEND...
Page 139: Event Mask Register(Exti_Emask)
1: open the interrupt request from line x Reserved Reserved,the reset value must be maintained. 20:0 IMASKx Interrupt mask on line x. (x is 0,1,2…19,20) 0: Mask the interrupt request from line x; 1: open the interrupt request from line x 6.3.3 Event Mask Register(EXTI_EMASK) Address offset : 0x04...
Page 140: Falling Edge Trigger Selection Register(Exti_Ft_Cfg)
20:0 RT_CFGx The rising edge on line x triggers the configuration bit. (x is 0,1,2…19,20) 0: Disables rising edge trigger (interrupts and events) on input line x. 1: Enable rising edge trigger (interrupts and events) on input line x. 6.3.5 Falling Edge Trigger Selection Register(EXTI_FT_CFG) Address offset : 0x0C Reset value : 0x00000000...
Page 141: Interrupt Request Pending Register(Exti_Pend)
Reserved Reserved,the reset value must be maintained. 20:0 SWIEx Software interrupt on line x. (x is 0,1,2…19,20) When the bit is' 0 ', writing '1' sets the corresponding pending bit in EXTI_PEND. If this interrupt is allowed in EXTI_IMASK and EXTI_EMASK, an interrupt will be generated.
Page 142 Bit Field Name Description 31:4 Reserved Reserved,the reset value must be maintained. TSSEL[3:0] Select external interrupt input as trigger source of timestamp event. 0: Select EXTI0 as the trigger source of timestamp event; 1: select EXTI1 as the trigger source of timestamp event; ……...
Page 143: Dma Controller
7 DMA Controller 7.1 Introduction The DMA controller can access totally 5 AHB slaves: Flash, SRAM, ADC, ABP1 and APB2. DMA Controller is controlled by CPU to perform fast data transfer from source to destination. After configuration, data can be transferred without CPU intervention.
Page 144: Block Diagram
7.3 Block Diagram Figure 7-1 DMA Block Diagram Flash Flash Interface controller Cortex-M0 SRAM Bridge 1 Bridge 2 USART2 USART1 I2C1 SPI1 I2C2 Arbiter SPI2 TIM3 TIM1 DMA requests AHB slave TIM6 device DMA requests TIM8 LPUART 7.4 Function Description DMA controller and Cortex ®...
Page 145: Channel Priority And Arbitration
7.4.2 Channel Priority And Arbitration The DMA uses an arbitration strategy to handle multiple requests from different channels. The priority of each channel is programmable in the channel control register (DMA_CHCFGx). 4 levels of priority: • Very high priority • High priority •...
Page 146 Destina- Number Source Tion Source: Transfer Operations Destination: Address Width Width Transfer Address / Data (R: Read, W: Write) / Data (Bit) (Bit) (Bit) 0x0 / B1B0 1: R B1B0 [15:0] @0x0, W B0 [7:0] @0x0 0x0 / B0 0x2 / B3B2 2: R B3B2 [15:0] @0x2, W B2 [7:0] @0x1 0x1 / B2 0x4 / B5B4...
Page 147: Peripheral/Memory Address Incrementation
to the place we want with extra bits i.e. 0 padding. If user wants to configure an 8-bit register but is aligned to a 32- bit address boundary, the source size should be set to 8 bits and destination to 32 bits so extra bits will be padded with 0.
Page 148: Flow Control
user as the DMA-enabled user, otherwise it will cause DMA transfer errors to occur. 7.4.7 Flow Control Three major flow controls are supported: • Memory to memory • Memory to peripheral • Peripheral to memory Flow control is controlled by two register bits in each DMA channel configuration register. Flow control is used to control source/destination and direction of DMA channel.
Page 149: Interrupt
7.4.10 Interrupt • Transfer complete interrupt: An interrupt is generated when channel data transfer is complete. Interrupt is a level signal. Each channel has its dedicated interrupt, interrupt mask control and interrupt status bit. interrupt status bit is cleared when interrupt flag clear bit is set.
Page 150: Dma Registers
Table 7-4 DMA Request Mapping DMA channel select Peripheral DMA request DMA channel select Peripheral DMA request adc_dma Tim1_ch2 sel = sel = sel = 1 Usart1_tx sel = 25 Tim1_ch3 sel = 2 Usart1_rx sel = 26 Tim1_ch4 sel = 3 Usart2_tx sel = 27 Tim1_com...
Page 151: Dma Interrupt Status Register (Dma_Intsts)
Offset Register Reset Value DMA_CHCFG2 01Ch Reserved Reset Value DMA_TXNUM2 NDTX[15:0] 020h Reserved Reset Value DMA_PADDR2 ADDR[31:0] 024h Reset Value DMA_MADDR2 ADDR[31:0] 028h Reset Value 02Ch DMA_CHSEL2 CH_SEL[5:0] Reserved Reset Value DMA_CHCFG3 030h Reserved Reset Value DMA_TXNUM3 NDTX[15:0] 034h Reserved Reset Value DMA_PADDR3 ADDR[31:0]...
Page 152: Dma Interrupt Flag Clear Register (Dma_Intclr)
Bit Field Name Description 0: Transfer error no happened on channel x. 1: Transfer error happened on channel x. 18/14/10/6/2 HTXFx Half transfer flag for channel x (x=1…5). Hardware sets this bit when half transfer is done. This bit is cleared by software by writing ‘1’...
Page 153: Dma Channel X Configuration Register (Dma_Chcfgx)
Bit Field Name Description 0: No action. 1: Reset DMA_INTSTS.GLBF bit of corresponding channel. 7.5.4 DMA Channel x Configuration Register (DMA_CHCFGx) Note: the x is channel number, x = 1…5 Address offset: 0x08+20 * (x–1) Reset value: 0x0000 0000 Bit Field Name Description 31:15...
Page 154: Dma Channel X Transfer Number Register (Dma_Txnumx)
Bit Field Name Description PINC Peripheral increment mode. Software can enable/disable peripheral address increment mode. 0: Peripheral address won't increase with each transfer. 1: Peripheral address increase with each transfer. CIRC Circular mode. Software can set/clear this bit. 0: Channel will stop after one round of transfer. 1: Channel configure as circular mode.
Page 155: Dma Channel X Peripheral Address Register (Dma_Paddrx)
Bit Field Name Description Number of data to be transferred (0～65535). Software can read/write the number of transfers when channel is disable and it will be read only after channel enable. Every successful transfer of corresponding DMA channel will decrease this register by 1. If circular mode is enable, it will automatically reload pre-set value when it reach zero.
Page 156: Dma Channel X Channel Request Select Register (Dma_Chselx)
Bit Field Name Description DMA_CHCFGx.MSIZE equal to 10 DMA will ignore bit [1:0] of MADDR. 7.5.8 DMA Channel x Channel Request Select Register (DMA_CHSELx) Note: the x is channel number, x = 1…5 Address offset: 0x18+20 * (x–1) Reset value: 0x0000 0000 Bit Field Name Description...
Page 157: Crc Calculation Unit
8 CRC Calculation Unit 8.1 CRC Introduction This module integrates the functions of CRC32 and CRC16, and the cyclic redundancy check (CRC) calculation unit obtains any CRC calculation result according to a fixed generator polynomial. In other applications, CRC technology is mainly used to verify the correctness and integrity of data transmission or data memory.
Page 158: Crc Function Description
Figure 8-1 CRC Calculation Unit Block Diagram CRC32 CRC16 Ctrl&Data Regs AHBInf 8.3 CRC Function Description 8.3.1 CRC32 CRC alculation unit contains one 32-bit data register: • Writing this register to input CRC data. • Reading this register to get the calculated CRC result. Every writing operation to this data register triggers the calculation of this new data with the previous calculation result (CRC calculation is performed on the whole 32-bit word rather than byte by byte).
Page 159: Crc Registers
8.4 CRC Registers 8.4.1 CRC Register Overview The following table lists the registers and reset values of CRC. Table 8-1 CRC Register Overview Offset Register CRC32DAT CRC32DAT[31:0] 000h Reset Value CRC32IDAT CRC32IDAT[7:0] 004h Reserved Reset Value CRC32CTRL 008h Reserved Reset Value CRC16CTRL 00Ch Reserved...
Page 160: Crc32 Control Register (Crc_Crc32Ctrl)
Bit Field Name Description 31:8 Reserved Reserved,the reset value must be maintained CRC32IDAT[7:0] Independent 8-bit data register. General 8 bits data register. It is for temporary stored 1-byte data. CRC_ CRC32CTRL.RESET bit reset signal will not impact this register. Note: this register is not a part of CRC calculation and can be used to store any data. 8.4.4 CRC32 Control Register (CRC_CRC32CTRL) Address offset: 0x08...
Page 161: Crc16 Input Data Register (Crc_Crc16Dat)
Bit ield Name Description Clear CRC16 results. 0: Not clear. 1: Clear to default value 0x0000. Set this bit to 1 will only maintain 1 clock cycle, hardware will clear automatically. (Software read always 0). ENDHL Data to be verified start to calculate from MSB or LSB. 0: From MSB to LSB 1: From LSB to MSB This bit is only for data to be verified.
Page 162: Lrc Result Register (Crc_Lrc)
ensure that 16-bit initial values are configured properly) 8.4.8 LRC Result Register (CRC_LRC) Address offset: 0x18 Reset value: 0x0000 0000 Bit Field Name Description 31:8 Reserved Reserved,the reset value must be maintained LRCDAT[7:0] LRC check value register. Software need to write initial value before use. And then each writing data to CRCDR will be XOR with LCR register value.
Page 163: Advanced Control Timers (Tim1 And Tim8)
9 Advanced Control Timers (TIM1 and TIM8) 9.1 TIM1 and TIM8 Introduction The advanced control timers (TIM1 and TIM8) are mainly used for the following occasions: counting the input signal, measuring the pulse width of the input signal and generating the output waveform, etc. Advanced timers have functions such as complementary output functions, dead-time insertion and break function.
Page 164: Tim1 And Tim8 Function Description
Figure 9-1 Block Diagram Of TIM1 And TIM8 Polarity TIMx_BKIN selection Clock failure event From clock controller CSS(Clock Security System) PVD abnormal (Power supply voltage detection) LOOKUP(Core Hardfault) Comparator polarity CK_TIM18 from RCC Internal clock(CK_INT) To another timer, ADC Polarity selection ETRF TRGO Edge detector...
Page 165: Counter Mode
9.3.1.1 Prescaler description The TIMx_PSC register consists of a 16-bit counter that can be used to divide the counter clock frequency by any factor between 1 and 65536. Because this controller has a buffer, it can be dynamically changed at runtime. The new prescaler value will only be adopted during the next update event.
Page 166: Figure 9-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
update by setting TIMx_CTRL1.UPDIS=1. When an update event is generated, the counter will still be cleared and the prescaler counter will also be set to 0 (but the prescaler value will remain unchanged). The figures below shows some examples of the counter behavior and the update flags for different division factors in the up-counting mode.
Page 167: Figure 9-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 9-4 Timing Diagram Of The , Update Event When ARPEN=0/1 Up-Counting ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 168: Figure 9-5 Timing Diagram Of The Down-Counting, Internal Clock Divided Factor = 2/N
the auto-reload value and generate a counter underflow event. The process of configuring update events and updating registers in down-counting mode is the same as in up-counting mode, refer to Section9.3.2.1. The figure below shows some examples of the counter behavior and the update flags for different division factors in the down-counting mode.
Page 169: Figure 9-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N
Note: if an update is generated due to a counter overflow, the auto-reload value will be updated before the counter is reloaded. Figure 9-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N Internal clock CK_PSC divided by 2 CNTEN Timer clock = CK_CNT Counter register...
Page 170: Figure 9-7 A Center-Aligned Sequence Diagram That Includes Counter Overflows And Underflows (Arpen = 1)
Figure 9-7 A Center-Aligned Sequence Diagram That Includes Counter Overflows And Underflows (ARPEN = 1) Counter underflow CNTEN CK_PSC Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Write a new value in TIMx_AR...
Page 171: Figure 9-8 Repeat Count Sequence Diagram In Down-Counting Mode
The repetition counter is decremented: • In the up-counting mode, each time the counter reaches the maximum value, an overflow occurs. • In down-counting mode, each time the counter decrements to the minimum value, an underflow occurs. • In center-aligned mode, each time the counter overflows or underflows. Its repetition rate is set by the value of the TIMx_REPCNT register.
Page 172: Clock Selection
Figure 9-9 Repeat Count Sequence Diagram In Up-Counting Mode CK_PSC CNTEN Timer clock = CK_CNT 01 ... 35 00 01 ... 35 36 00 01 ... 35 00 01 ... 35 36 00 01 ... 35 36 CNT_REG 36 00 00 01 Underflow Overflow...
Page 173: Figure 9-11 Control Circuit In Normal Mode, Internal Clock Divided By 1
• Two kinds of external clock mode : − external input pin − external trigger input ETR • Internal trigger input (ITRx): one timer is used as a prescaler for another timer. 9.3.4.1 Internal clock source (CK_INT) When the TIMx_SMCTRL.SMSEL is equal to “000”, the slave mode controller is disabled. The three control bits (TIMx_CTRL1.CNTEN、TIMx_CTRL1.
Page 174: Figure 9-12 Ti2 External Clock Connection Example
9.3.4.2 External clock source mode 1 Figure 9-12 TI2 External Clock Connection Example Filter (TIMx_CCMOD1.ICF[3:0]) Edge Detector TIMx_SMCTRL. CK_INT rising TSEL[2:0] Internal clock mode Polarity Selection （ TIMx_CCEN.CC2P ） ITRx TRGI rising TI1_ED External clock mode 1 TI1FP1 TI2FP2 CK_PSC ETRF ETRF rising External clock mode 2...
Page 175: Figure 9-13 Control Circuit In External Clock Mode 1
Figure 9-13 Control Circuit In External Clock Mode 1 CNTEN Timer clock = CK_CNT=CK_PSC Counter register TITF Write TITF=0 9.3.4.3 External clock source mode 2 This mode is selected by TIMx_SMCTRL .EXCEN equal to 1. The counter can count on every rising or falling edge of the external trigger input ETR.
Page 176: Capture/Compare Channels
• Turn on the counter by setting TIMx_CTRL1. CNTEN equal to ‘1’ The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to the counter is due to a resynchronization circuit on the ETRP signal. Figure 9-15 Control Circuit In External Clock Mode 2 CNTEN CK _INT...
Page 177: Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage) From slave mode controller TI2FP1 Divider /1,/2,/4,/8 TI2F_Rising From channel 2 IC1PSC TI1FP1 TI2F_Falling TIMx_CCMOD1. Polarity Selection IC1PSC[1:0] TIMx_CCMOD1.CC1SEL[3:0] TIMx_CCEN.CC2P TIMx_CCEN.CC1EN Filter Down counter TIMx_CCMOD1.IC1F[ Edge Detector 3:0] TI1F_Rising TI1F To the slave TI1F_Falling mode controller Polarity Selection...
Page 178: Figure 9-17 Capture/Compare Channel 1 Main Circuit
Figure 9-17 Capture/Compare Channel 1 Main Circuit CC1SEL[1] CC1SEL[0] Input IC1PSC CC1EN mode Read CCDAT1H TIM1_EVTGEN.CC1GN Read CCDAT1L Read in APB Bus progress MCU Peripheral interface 16 bit High 8-bits Capture/ Capture/ transfer compare compare Counter preload register shadow register Low 8-bits Output Comparator...
Page 179: Input Capture Mode
Figure 9-18 Output Part Of Channelx (x= 1,2,3, Take Channel 1 As Example) To the master mode controller Output enable Output enable circuit circuit Polarity Seletion TIM1_CCEN.CC1NEN ETRF Ocref_clr_int TIM1_CCEN. TIM1_CCEN.CC1EN TIM1_CCEN.CC1NEN CC1P TIM1_CCEN.CC1EN TIM1_BKDT.MOEN TIM1_BKDT.MOEN CNT=CCR1 TIM1_BKDT.OSSI TIM1_BKDT.OSSI OC1REFC TIM1_BKDT.OSSR TIM1_BKDT.OSSR CNT>CCR1...
Page 180: Pwm Input Mode
the TIMx_CCDATx register. The overcapture flag TIMx_STS.CCxOCF is set equal to 1 when the counter value is captured in the TIMx_CCDATx register and TIMx_STS.CC1ITF is already pulled high. Unlike the former, TIMx_STS.CCxOCF is cleared by writing 0 to it. To capture the counter value on the rising edge of the TI1 input into the TIMx_CCDAT1 register, the configuration flow is as follows: •...
Page 181: Forced Output Mode
• Configure TIMx_SMCTRL.TSEL=101 to select Filtered timer input 1 (TI1FP1) as valid trigger input. • Configure TIMx_SMCTRL.SMSEL=100 to configure the slave mode controller to reset mode. • Configure TIMx_CCEN. CC1EN=1 and TIMx_CCEN.CC2EN=1 to enable capture. Figure 9-20 PWM Input Mode Timing TIMx_CNT 0004 0000...
Page 182 are as follow: • TIMx_CCMODx.OCxMD is for output compare mode, and TIMx_CCEN.CCxP is for output polarity. When the compare matches, if set TIMx_CCMODx.OCxMD=000, the output pin will keep its level;if set TIMx_CCMODx.OCxMD=001, the output pin will be set active;if set TIMx_CCMODx.OCxMD=010, the output pin will be set inactive;if set TIMx_CCMODx.OCxMD=011, the output pin will be set to toggle.
Page 183: Pwm Mode
Figure 9-21 Output Compare Mode, Toggle On OC1 TIM1_CNT 0069 006A 006B 8801 8800 TIM1_CCDAT1 006A 8801 Write 8801h in CCDAT1 register OC1REF=OC1 Match detected on CCDAT1 Interrupt generated if enabled 9.3.10 PWM Mode User can get a signal whose duty cycle is determined by the value of the TIMx_CCDATx register and whose frequency is determined by the value of the TIMx_AR register in PWM mode.
Page 184: Figure 9-22 Center-Aligned Pwm Waveform (Ar=8)
mode 1, the compare flag is set when the counter counts down corresponding to TIMx_CTRL1. CAMSEL=01. Figure 9-22 Center-Aligned PWM Waveform (AR=8) Counter register OCXREF CCDATx=0 CAMSEL=01 CCxITF CAMSEL=10 CAMSEL=11 OCXREF CCDATx=4 CAMSEL=01 CAMSEL=10 CCxITF CAMSEL=11 OCXREF CCDATx=7 CAMSEL=10或11 CCxITF OCXREF CAMSEL=01 CCDATx=8...
Page 185: One-Pulse Mode
• Up-counting User can set TIMx_CTRL1.DIR=0 to make counter counts up. Example for PWM mode1. When TIMx_CNT < TIMx_CCDATx, the OCxREF is high level, otherwise it will be low level. If the compare value in TIMx_CCDATx is greater than the auto-reload value, the OCxREF will remains 1. Conversely, if the compare value is 0, the OCxREF will remains 0.
Page 186: Figure 9-24 Example Of One-Pulse Mode
generated after a controllable delay t . The output mode needs to be configured as output compare mode or PWM DELAY mode. After selecting one-pulse mode, the counter will stop counting after the update event UEV is generated. Figure 9-24 Example Of One-Pulse Mode TIMx_AR TIMx_CCDAT1 Counter...
Page 187: Clearing The Ocxref Signal On An External Event
You can set TIMx_CCMODx.OCxFEN=1 to turn on OCx fast enable, after triggering the rising edge, the OCxREF signal will be forced to be converted to the same level as the comparison match occurs immediately, regardless of the comparison result. OCxFEN fast enable only takes effect when the channel mode is configured for PWM1 and PWM2 modes.
Page 188 is independently for each output. User can control the complementary signals OCx and OCxN by setting the combination of several control bits, which TIMx_CCEN.CCxEN, TIMx_CCEN.CCxNEN, TIMx_BKDT.MOEN, TIMx_CTRL2.OIx, TIMx_CTRL2.OIxN, TIMx_BKDT.OSSI, and TIMx_BKDT.OSSR. When switching to the IDLE state, the dead- time will be activated. If user set TIMx_CCEN.CCxEN and TIMx_CCEN.CCxNEN at the same time, a dead-time will be insert.
Page 189: Figure 9-26 Complementary Output With Dead-Time Insertion
Figure 9-26 Complementary Output With Dead-Time Insertion OCxREF Complementary output with dead-time insertion Delay OCxN Delay Dead-time waveform with delay greater OCxREF than the negative pulse Delay OCxN Dead-time waveform OCxREF with delay larger than the positive pulse OCxN Delay User can set TIMx_BKDT.DTGN to programme the dead-time delay for each of the channels.
Page 190: Break Function
9.3.14 Break Function The output enable signals and inactive levels will be modified when setting the corresponding control bits when using the break function. However, at any time, the output of OCx and OCxN cannot at the active level at the same time, meaning it must satisfy (CCxP^OIx) ^(CCxNP^OIxN)!=0.
Page 191: Debug Mode
is high. • If TIMx_DINTEN.BIEN=1, when TIMx_STS.BITF=1, an interrupt will be generated. • If user set TIMx_BKDT.AOEN, the TIMx_BKDT.MOEN will be set automatically when the next UEV happened. User can use this to regulate. If user did not set TIMx_BKDT.AOEN, the TIMx_BKDT.MOEN will remain low until been set 1 again.
Page 192: Timx And External Trigger Synchronization
9.3.16 TIMx and External Trigger Synchronization TIMx timers can be synchronized by a trigger in slave modes (reset, trigger and gated). 9.3.16.1 Slave mode: reset mode In reset mode, the trigger event can reset the counter and the prescaler updates the preload registers TIMx_AR, TIMx_CCDATx, and generates the update event UEV (TIMx_CTRL1.UPRS=0).
Page 193: Figure 9-29 Control Circuit In Trigger Mode
(TIMx_SMCTRL.TSEL=110); When a rising edge is detected on TI2, the counter starts counting, and the trigger flag is set (TIMx_STS.TITF=1); The delay between the rising edge of TI2 and the actual start of the counter is caused by the resynchronization circuit at the TI2 input.
Page 194: Figure 9-30 Control Circuit In Gated Mode
Figure 9-30 Control Circuit In Gated Mode Counter clock=CK_CNT=CK_PSC Counter register 30 31 32 33 36 37 38 CNTEN TITF Clear TITF 9.3.16.4 Slave mode: trigger mode + external clock mode 2 In reset mode, trigger mode and gate control mode, the counter clock can be selected as external clock mode 2, and the ETR signal is used as the external clock source input.
Page 195: Timer Synchronization
Figure 9-31 Control Circuit In Trigger Mode + External Clock Mode2 Counter clock=CK_CNT=CK_PSC Counter register CNTEN TITF 9.3.17 Timer Synchronization All TIM timers are internally connected for timer synchronization or chaining. For more details, see 10.3.14. 9.3.18 Generating Six Step PWM output In order to modify the configuration of all channels at the same time, the configuration of the next step can be set in advance (the preloaded bits are OCxMD, CCxEN and CCxNEN).
Page 196: Encoder Interface Mode
Figure 9-32 6-Step PWM Generation, COM Example (OSSR=1) (CCRx) Counter (CNT) OCxREF write COM=1 COM event CCxEN=1 write OCxMD=100 CCxEN=1 CCxNEN=0 CCxNEN=0 OCxMD=100(forced inactive) OCxMD=100 OCxN write CCxNEN=0 CCxEN=1 和OCxMD=100 CCxNEN=0 CCxEN=1 OCxMD=100(forced inactive) CCxNEN=0 OCxMD=100 OCxN write CCxNEN=1 CCxEN=1 和OCxMD=101 CCxEN=0 CCxNEN=0...
Page 197: Figure 9-33 Example Of Counter Operation In Encoder Interface Mode
Active Edge Signals Rising Falling Rising Falling (TI1FP1 For TI2, TI2FP2 For TI1) Counting only at TI1 High Counting down Counting up Don't count Don't count Counting up Counting down Don't count Don't count Counting only at TI2 High Don't count Don't count Counting up Counting down...
Page 198: Figure 9-34 Encoder Interface Mode Example With Ic1Fp1 Polarity Inverted
Figure 9-34 Encoder Interface Mode Example With IC1FP1 Polarity Inverted forward jitter backward jitter Counter down 198 / 526...
Page 199: Interfacing With Hall Sensor
9.3.20 Interfacing With Hall Sensor Connect the Hall sensor to the three input pins (CC1, CC2 and CC3) of the timer, and then select the XOR function to route the inputs of TIMx_CH1, TIMx_CH2 and TIMx_CH3 through the XOR gate as the output of TI1 to channel 1 for capturing signal.
Page 200: Advanced-Control
Figure 9-35 Example Of Hall Sensor Interface Interfacing timer Counter(CNT) (CCDAT2) CCDAT1 TRGO=OC2REF Advanced-control timers(TIM1&TIM8) OC1N OC2N OC3N Write CCxEN、CCxNEN and OCxMD for next step 200 / 526...
Page 201: Timx Register Description(X=1, 8)
9.4 TIMx Register Description(X=1, 8) For abbreviations used in registers, see section 1.1 These peripheral registers can be operated as half word (16-bits) or one word (32-bits). 9.4.1 Register Overview Table 9-2 Register Overview Offset Register TIMx_CTRL1 000h Reset Value TIMx_CTRL2 004h Reset Value...
Page 202: Control Register 1 (Timx_Ctrl1)
Offset Register TIMx_PSC PSC[15:0] 028h Reserved Reset Value 02Ch TIMx_AR AR[15:0] Reserved Reset Value TIMx_REPCNT REPCNT[7:0] 030h Reserved Reset Value TIMx_CCDAT1 CCDAT1[15:0] 034h Reserved Reset Value TIMx_CCDAT2 CCDAT2[15:0] 038h Reserved Reset Value TIMx_CCDAT3 CCDAT3[15:0] 03Ch Reserved Reset Value TIMx_CCDAT4 CCDAT4[15:0] 040h Reserved Reset Value...
Page 203 Bit Field Name Description 1: Enable CLRSEL OCxREF clear selection 0: Select the external OCxREF clear from ETR 1: Select the internal OCxREF clear from comparator 14:12 Reserved Reserved, the reset value must be maintained C1SEL Channel 1 selection 0: Select external CH1 signal from IOM 1: Select internal CH1 signal from COMP IOMBKPEN Enabling IOM as BKP...
Page 204: Control Register 2 (Timx_Ctrl2)
Bit Field Name Description 0: If update interrupt or DMA request is enabled, any of the following events will generate an update interrupt or DMA request: – Counter overflow/underflow – The TIMx_EVTGEN.UDGN bit is set – Update generation from the slave mode controller 1: If update interrupt or DMA request is enabled, only counter overflow/underflow will generate update interrupt or DMA request UPDIS...
Page 205 Bit Field Name Description Output idle state 3 (OC3 output). See TIMx_CTRL2.OI1 bit. OI2N Output idle state 2 (OC2N output). See TIMx_CTRL2.OI1N bits. Output idle state 2 (OC2 output). See TIMx_CTRL2.OI1 bit. OI1N Output Idle state 1 (OC1N Output) 0: When TIMx_BKDT.MOEN = 0, after dead-time OC1N = 0 1: When TIMx_BKDT.MOEN = 0, after dead-time OC1N = 1 Output Idle state 1 0: When TIMx_BKDT.MOEN = 0, if OC1N is implemented, after dead-time OC1 = 0...
Page 206: Slave Mode Control Register (Timx_Smctrl)
Bit Field Name Description CCPCTL Capture/ Compare preloaded control 0: No preloading of CCxEN, CCxNEN and OCxMD bits occurs. 1: Preloading of CCxEN, CCxNEN and OCxMD bits occurs. they are updated only when a commutation event COM occurs (TIMx_EVTGEN.CCUDGN bit set or rising edge on TRGI depending on CCUSEL bit) Note: this bit only applied to channels with complementary outputs.
Page 207 Bit Field Name Description 11:8 EXTF[3:0] External trigger filter These bits are used to define the frequency at which the ETRP signal is sampled and the bandwidth of the ETRP digital filtering. In effect, the digital filter is an event counter that generates a validate output after consecutive N events are recorded.
Page 208: Dma/Interrupt Enable Registers (Timx_Dinten)
Bit Field Name Description SMSEL[2:0] Slave mode selection When an external signal is selected, the active edge of the trigger signal (TRGI) is linked to the selected external input polarity (see input control register and control register description) 000: Disable slave mode. If TIMx_CTRL1.CNTEN = 1, the prescaler is driven directly by the internal clock.
Page 209 Bit Field Name Description COMDEN COM DMA request enable 0: Disable COM DMA request 1: Enable COM DMA request CC4DEN Capture/Compare 4 DMA request enable 0: Disable capture/compare 4 DMA request 1: Enable capture/compare 4 DMA request CC3DEN Capture/Compare 3 DMA request enable 0: Disable capture/compare 3 DMA request 1: Enable capture/compare 3 DMA request CC2DEN...
Page 210: Status Registers (Timx_Sts)
9.4.6 Status Registers (TIMx_STS) Offset address: 0x10 Reset value: 0x0000 0000 Bit Field Name Description 31：18 Reserved Reserved, the reset value must be maintained CC6ITF Capture/Compare 6 interrupt flag See TIMx_STS.CC1ITF description. CC5ITF Capture/Compare 5 interrupt flag See TIMx_STS.CC1ITF description. 15：13 Reserved Reserved, the reset value must be maintained...
Page 211: Event Generation Registers (Timx_Evtgen)
Bit Field Name Description COMITF COM interrupt flag This bit is set by hardware once a COM event is generated (when TIMx_CCEN.CCxEN, TIMx_CCEN.CCxNEN, TIMx_CCMOD1.OCxMD have been updated). This bit is cleared by software. 0: No COM event occurred 1: COM interrupt pending CC4ITF Capture/Compare 4 interrupt flag See TIMx_STS.CC1ITF description.
Page 212 Bit Field Name Description 15：8 Reserved Reserved, the reset value must be maintained Break generation This bit can generate a brake event when set by software. And at this time TIMx_BKDT.MOEN = 0, TIMx_STS.BITF = 1, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be generated.
Page 213: Capture/Compare Mode Register 1 (Timx_Ccmod1)
Bit Field Name Description UDGN Update generation This bit can generate an update event when set by software. And at this time the counter will be reinitialized, the prescaler counter will be cleared, the counter will be cleared in center-aligned or up- counting mode, but take TIMx_AR in down-counting mode the value of the register.
Page 214 Bit Field Name Description 001: Set channel 1 to the active level on match. When TIMx_CCDAT1 = TIMx_CNT, OC1REF signal will be forced high. 010: Set channel 1 as inactive level on match. When TIMx_CCDAT1 = TIMx_CNT, OC1REF signal will be forced low. 011: Toggle.
Page 215 Input capture mode: Bit Field Name Description 15:12 IC2F[3:0] Input Capture 2 Filter 11:10 IC2PSC[1:0] Input Capture 2 Prescaler CC2SEL[1:0] Capture/Compare 2 selection These bits are used to select the input/output and input mapping of the channel 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 216: Capture/Compare Mode Register 2 (Timx_Ccmod2)
Bit Field Name Description 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped to TRC. This mode is only active when the internal trigger input is selected by TIMx_SMCTRL.TSEL.
Page 217: Capture/Compare Enable Registers (Timx_Ccen)
Input capture mode: Bit Field Name Description 15:12 IC4F[3:0] Input Capture 4 filter 11:10 IC4PSC[1:0] Input Capture 4 Prescaler CC4SEL[1:0] Capture/Compare 4 selection These bits are used to select the input/output and input mapping of the channel 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 218 Bit Field Name Description 19：18 Reserved Reserved, the reset value must be maintained CC5P Capture/Compare 5 output polarity See TIMx_CCEN.CC1P description. CC5EN Capture/Compare 5 output enable See TIMx_CCEN.CC1EN description. 15:14 Reserved Reserved, the reset value must be maintained CC4P Capture/Compare 4 output polarity See TIMx_CCEN.CC1P description.
Page 219: Table 9-4 Output Control Bits Of Complementary Ocx And Ocxn Channels With Break Function
Bit Field Name Description CC1P Capture/Compare 1 output polarity When the corresponding channel of CC1 is in output mode: 0: OC1 active high 1: OC1 active low When the corresponding channel of CC1 is in input mode: At this time, this bit is used to select whether IC1 or the inverse signal of IC1 is used as the trigger or capture signal.
Page 220: Counters (Timx_Cnt)
Control Bits Output State MOEN OSSI OSSR Ccxen Ccxnen Ocx Output State Ocxn Output State OCxREF + polarity, Off-state (Output enabled with inactive state) OCx= OCxREF xor CCxP, OCx_EN=1 OCxN=CCxNP,OCxN_EN=1 Complementary to OCxREF + polarity + dead- OCxREF + polarity + dead-time, time, OCx_EN=1 OCxN_EN=1...
Page 221: Auto-Reload Register (Timx_Ar)
9.4.13 Auto-Reload Register (TIMx_AR) Offset address: 0x2C Reset values: 0xFFFF Bit Field Name Description 15:0 AR[15:0] Auto-reload value These bits define the value that will be loaded into the actual auto-reload register. See Section 9.3.1 for more details. When the TIMx_AR.AR [15:0] value is null, the counter does not work. 9.4.14 Repeat Count Registers (TIMx_REPCNT) Offset address: 0x30...
Page 222: Capture/Compare Register 2 (Timx_Ccdat2)
Bit Field Name Description CCDAT1 contains the value to be compared to the counter TIMx_CNT, signaling on the OC1 output. If the preload feature is not selected in TIMx_CCMOD1.OC1PEN bit, the written value is immediately transferred to the active register. Otherwise, this preloaded value is transferred to the active register only when an update event occurs.
Page 223: Capture/Compare Register 4 (Timx_Ccdat4)
Bit Field Name Description 15:0 CCDAT3[15:0] Capture/Compare 3 value ◼ CC3 channel is configured as output: CCDAT3 contains the value to be compared to the counter TIMx_CNT, signaling on the OC3 output. If the preload feature is not selected in TIMx_CCMOD2.OC3PEN bit, the written value is immediately transferred to the active register.
Page 224 Bit Field Name Description This bit can be set by software or hardware depending on the TIMx_BKDT.AOEN bit, and is asynchronously cleared to '0' by hardware once the brake input is active. It is only valid for channels configured as outputs. 0: OC and OCN outputs are disabled or forced to idle state.
Page 225: Dma Control Register (Timx_Dctrl)
Bit Field Name Description TIMx_BKDT.OSSR and TIMx_BKDT.OSSI bits also enable write protection. – LOCK Level 3 Except for register write protection in LOCK Level 2, TIMx_CCMODx.OCxMD and TIMx_CCMODx.OCxPEN bits (If the corresponding channel is configured in output mode) also enable write protection. Note: after the system reset, the LCKCFG bit can only be written once.
Page 226: Dma Transfer Buffer Register (Timx_Daddr)
Bit Field Name Description 00000: TIMx_CTRL1, 00001: TIMx_CTRL2, 00010: TIMx_SMCTRL, … ..10001：TIMx_BKDT 10010：TIMx_DCTRL 9.4.21 DMA Transfer Buffer Register (TIMx_DADDR) Offset address: 0x4C Reset value: 0x0000 Bit Field Name Description 15:0 BURST[15:0] DMA access buffer. When a read or write operation is assigned to this register, the register located at the address range (DMA base address + DMA burst length ×...
Page 227: Capture/Compare Register 5 (Timx_Ccdat5)
Bit Field Name Description OC6CEN Output compare 6 clear enable 14:12 OC6MD[2:0] Output compare 6 mode OC6PEN Output compare 6 preload enable OC6FEN Output compare 6 fast enable Reserved Reserved, the reset value must be maintained OC5CEN Output compare 5 clear enable OC5MD[2:0] Output compare 5 mode OC5PEN...
Page 228 Bit Field Name Description 15:0 CCDAT6[15:0] Capture/Compare 6 value ◼ CC6 channel can only configured as output: CCDAT6 contains the value to be compared to the counter TIMx_CNT, signaling on the OC6 output. If the preload feature is not selected in TIMx_CCMOD3.OC6PEN bit, the written value is immediately transferred to the active register.
Page 229: General-Purpose Timers (Tim3)
10 General-purpose Timers (TIM3) 10.1 General-purpose Timers Introduction The general-purpose timers (TIM3) is mainly used for the following occasions: counting the input signal, measuring the pulse width of the input signal and generating the output waveform, etc. 10.2 Main Features of General-purpose Timers •...
Page 230: General-Purpose Timers Description
Figure 10-1 Block Diagram Of Timx（X=3） TIMxCLK from RCC Internal clock(CK_INT) To another timer, ADC Polarity selection ETRF TRGO Edge detector Trigger controller TIMx_ETR pin Prescaler Input filter Reset, enable, COMP_TIM_ up/down, count OCREFCLR Slave mode controller TI1F_ED TRGI CK_PSC Encoder mode Psc Prescaler CK_CNT...
Page 231: Counter Mode
Figure 10-2 Counter Timing Diagram With Prescaler Division Change From 1 To 4 CNTEN CK_PSC Timer Clock = CK_CNT Counter register 89 8A 8B 8C Update event（UEV） Prescaler controller register Write a new value in TIMx_PSC Prescaler counter Prescaler buffer 10.3.2 Counter Mode 10.3.2.1 Up-counting mode...
Page 232: Figure 10-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
Figure 10-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N Internal clock divided by 2 CNTEN CK_PSC Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update interrupt flag(UDITF) Update event(UEV) Internal clock CK_PSC divided by N...
Page 233: Figure 10-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 10-4 Timing Diagram Of The Up-Counting, Update Event When ARPEN=0/1 ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 234: Figure 10-5 Timing Diagram Of The Down-Counting, Internal Clock Divided Factor = 2/N
10.3.2.2 Down-counting mode In down-counting mode, the counter will decrement from the value of the register TIMx_AR to 0, then restart from the auto-reload value and generate a counter underflow event. The process of configuring update events and updating registers in down-counting mode is the same as in up-counting mode, refer to 10.3.2.1.
Page 235: Figure 10-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N
or using a slave mode controller). In this case, the counter restarts from 0, as does the prescaler's counter. Please note: if the update source is a counter overflow, auto-reload update will occur before timer reload the counter. Figure 10-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N Internal clock CK_PSC divided by 2...
Page 236: Clock Selection
Figure 10-7 A Center-Aligned Sequence Diagram That Includes Counter Overflows And Underflows (ARPEN = 1) Counter underflow CNTEN CK_PSC Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Write a new value in TIMx_AR...
Page 237: Figure 10-8 Control Circuit In Normal Mode, Internal Clock Divided By 1
− external trigger input ETR • Internal trigger input (ITRx): one timer is used as a prescaler for another timer. 10.3.3.1 Internal clock source (CK_INT) When the TIMx_SMCTRL.SMSEL is equal to “000”, the slave mode controller is disabled. The three control bits (TIMx_CTRL1.CNTEN、TIMx_CTRL1.
Page 238: Figure 10-9 Ti2 External Clock Connection Example
10.3.3.2 External clock source mode 1 Figure 10-9 TI2 External Clock Connection Example Filter (TIMx_CCMOD1.ICF[3:0]) Edge Detector TIMx_SMCTRL. CK_INT rising TSEL[2:0] Internal clock mode Polarity Selection （ TIMx_CCEN.CC2P ） ITRx TRGI rising TI1_ED External clock mode 1 TI1FP1 TI2FP2 CK_PSC ETRF ETRF rising External clock mode 2...
Page 239: Figure 10-10 Control Circuit In External Clock Mode 1
Figure 10-10 Control Circuit In External Clock Mode 1 CNTEN Timer clock = CK_CNT=CK_PSC Counter register TITF Write TITF=0 10.3.3.3 External clock source mode 2 This mode is selected by TIMx_SMCTRL .EXCEN equal to 1. The counter can count on every rising or falling edge of the external trigger input ETR.
Page 240: Capture/Compare Channels
• Turn on the counter by setting TIMx_CTRL1. CNTEN equal to ‘1’ The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to the counter is due to a resynchronization circuit on the ETRP signal. Figure 10-12 Control Circuit In External Clock Mode 2 CNTEN CK _INT...
Page 241: Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage) From slave mode controller TI2FP1 Divider /1,/2,/4,/8 TI2F_Rising From channel 2 IC1PSC TI1FP1 TI2F_Falling TIMx_CCMOD1. Polarity Selection IC1PSC[1:0] TIMx_CCMOD1.CC1SEL[3:0] TIMx_CCEN.CC2P TIMx_CCEN.CC1EN Filter Down counter TIMx_CCMOD1.IC1F[ Edge Detector 3:0] TI1F_Rising TI1F To the slave TI1F_Falling mode controller Polarity Selection...
Page 242: Figure 10-14 Capture/Compare Channel 1 Main Circuit
Figure 10-14 Capture/Compare Channel 1 Main Circuit CC1SEL[1] CC1SEL[0] Input IC1PSC CC1EN mode Read CCDAT1H TIM1_EVTGEN.CC1GN Read CCDAT1L Read in APB Bus progress MCU Peripheral interface 16 bit High 8-bits Capture/ Capture/ transfer compare compare Counter preload register shadow register Low 8-bits Output Comparator...
Page 243: Input Capture Mode
Figure 10-15 Output Part Of Channelx （X = 1,2,3,4;Take Channel 4 As An Example） To the master mode controller Output enable Output enable Polarity circuit circuit selection TIM1_CCEN. CC4P Ocref_clr ETRF TIM1_CCEN.CC4EN OC4 REF CNT=CCDAT4 CNT>CCDAT4 Output mode controller TIM1_CCMOD2.OC2M D[2:0] Reads and writes always access preloaded registers when capturing/comparing.
Page 244: Pwm Input Mode
‘0011’. • By configuring TIMx_CCEN .CC1P=0, select the rising edge as the valid transition polarity on the TI1 channel. • Configure the input prescaler. In this example, configure TIMx_CCMOD1.IC1PSC= ‘00’ to disable the prescaler because we want to capture every valid transition. •...
Page 245: Forced Output Mode
Figure 10-16 PWM Input Mode Timing TIMx_CNT 0004 0000 0001 0002 0003 0004 0000 TIMx_CCDAT1 0004 0002 TIMx_CCDAT2 IC1 capture IC2 capture IC1 capture IC2 capture Pulse width Period Reset counter measurement measurement Because of only filter timer input 1 (TI1FP1) and filter timer input 2 (TI2FP2) are connected to the slave mode controller, the PWM input mode can only be used with the TIMx_CH1/TIMx_CH2 signals.
Page 246: Figure 10-17 Output Compare Mode, Toggle On Oc1
• Set TIMx_STS.CCxITF. • If user set TIMx_DINTEN.CCxIEN, a corresponding interrupt will be generated. • If user set TIMx_DINTEN.CCxDEN and set TIMx_CTRL2.CCDSEL to select DMA request, and DMA request will be sent. User can set TIMx_CCMODx.OCxPEN to choose capture/compare shawdow regisete using capture/compare preload registers(TIMx_CCDATx) or not.
Page 247: Pwm Mode
10.3.9 PWM Mode User can get a signal whose duty cycle is determined by the value of the TIMx_CCDATx register and whose frequency is determined by the value of the TIMx_AR register in PWM mode. And depends on the value of TIMx_CTRL1.CAMSEL, the TIM can generate PWM signal in edge-aligned mode or center-aligned mode.
Page 248: Figure 10-18 Center-Aligned Pwm Waveform (Ar=8)
Figure 10-18 Center-Aligned PWM Waveform (AR=8) Counter register OCXREF CCDATx=0 CAMSEL=01 CCxITF CAMSEL=10 CAMSEL=11 OCXREF CCDATx=4 CAMSEL=01 CAMSEL=10 CCxITF CAMSEL=11 OCXREF CCDATx=7 CAMSEL=10或11 CCxITF OCXREF CAMSEL=01 CCDATx=8 CCxITF CAMSEL=10 CAMSEL=11 OCXREF CCDATx>8 CAMSEL=01 CCxITF CAMSEL=10 CAMSEL=11 When using center-aligned mode, users should pay attention to the following considerations: •...
Page 249: One-Pulse Mode
User can set TIMx_CTRL1.DIR=0 to make counter counts up. Example for PWM mode1. When TIMx_CNT < TIMx_CCDATx, the PWM signal OCxREF is high level. Otherwise it will be low level. If the compare value in TIMx_CCDATx is greater than the auto-reload value, the OCxREF will remains 1. Conversely, if the compare value is 0, the OCxREF will remains 0.
Page 250: Figure 10-20 Example Of One-Pulse Mode
Figure 10-20 Example of One-pulse mode TIMx_AR TIMx_CCDAT1 Counter OCxREF The following is an example of a one-pulse mode: A rising edge trigger is detected from the TI2 input, and a pulse with a width of t is generated on OC1 after a PULSE delay of t DELAY...
Page 251: Clearing The Ocxref Signal On An External Event
the comparison result. OCxFEN fast enable only takes effect when the channel mode is configured for PWM1 and PWM2 modes. 10.3.11 Clearing the OCxREF Signal on an External Event If user set TIMx_CCMODx.OCxCEN=1, high level of ETRF input can be used to driven the OCxREF signal to low, and the OCxREF signal will remains low, until the next UEV happens.
Page 252: Timx And External Trigger Synchronization
10.3.13 TIMx and External Trigger Synchronization Same with advanced-control timer, refer to 9.3.16 10.3.14 Timer Synchronization All TIMx timers are internally inter connected to each other. This implementation allows any master timer to provide trigger to reset, start, stop or provide a clock for the other slave timers. The master clock is used for internal counter and can be prescaled.
Page 253: Figure 10-23 Tim3 Gated By Oc1Ref Of Tim1
10.3.14.2 Master timer to enable another timer In this example, TIM3 is enabled by the output compare of TIM1. TIM3 counter will start to count after the OC1REF output from TIM1 is high. Both counters are clocked based on CK_INT via a prescaler divide by 3 is performed /3).
Page 254: Figure 10-24 Tim3 Gated By Enable Signal Of Tim1
• Setting TIM3_CTRL1.CNTEN= ‘1’ to start TIM3. • Setting TIM1_CTRL1.CNTEN= ‘1’ to start TIM1. • Setting TIM1_CTRL1.CNTEN= ‘0’ to stop TIM1. Figure 10-24 TIM3 Gated By Enable Signal Of TIM1 TIM1 CK_INT CNTEN TIM3 TITF Clear TITF 10.3.14.3 Master timer to start another timer In this example, we can use update event as trigger source.TIM1 is master, TIM3 is slave.
Page 255: Figure 10-25 Trigger Tim3 With An Update Of Tim1
Figure 10-25 Trigger TIM3 With An Update Of TIM1 TIM1 CK_INT CNTEN TIM3 TITF Clear TITF 10.3.14.4 Start 2 timers synchronously using an external trigger In this example, TIM1 is enabled when TIM1's TI1 input rises, and TIM3 is enabled when TIM1 is enabled. To ensure the alignment of counters, TIM1 must be configured in master/slave mode.
Page 256: Encoder Interface Mode
Figure 10-26 Triggers Timers 1 And 3 Using The TI1 Input Of TIM1 TIM1 CK_INT CNTEN CK_PSC 02 03 04 05 06 07 08 09 TITF TIM3 CNTEN CK_PSC 01 02 03 04 05 06 07 08 09 TITF 10.3.15 Encoder Interface Mode The encoder uses two inputs TI1 and TI2 as an interface and the counter counts on every edge change on TI1FP1 or TI2FP2.
Page 257: Figure 10-27 Example Of Counter Operation In Encoder Interface Mode
Counting only at TI1 High Counting down Counting up Don't count Don't count Counting up Counting down Don't count Don't count Counting only at TI2 High Don't count Don't count Counting up Counting down Don't count Don't count Counting down Counting up Counting on High...
Page 258: Interfacing With Hall Sensor
Figure 9-43 Encoder Interface Mode Example With IC1FP1 Polarity Inverted forward jitter backward jitter Counter down 10.3.16 Interfacing with Hall Sensor Please refer to 9.3.20 10.4 TIMx Register Description(x=3) For abbreviations used in registers, see section 1.1 These peripheral registers can be operated as half word (16-bits) or one word (32-bits). 10.4.1 Register Overview Table 10-2 Register Overview...
Page 259: Control Register 1 (Timx_Ctrl1)
Offset Register TIMx_STS 010h Reset Value TIMx_EVTGEN 014h Reset Value TIMx_CCMOD1 Output compare Reset Value 018h TIMx_CCMOD1 Input capture Reset Value TIMx_CCMOD2 01Ch Output compare Reset Value TIMx_CCMOD2 01Ch Input capture Reset Value TIMx_CCEN 020h Reset Value TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC...
Page 260 Reset value: 0x0000 0000 Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained CLRSEL OCxREF clear selection 0: Select the external OCxREF clear from ETR 1: Select the internal OCxREF clear from comparator Reserved Reserved, the reset value must be maintained C3SEL Channel 3 Selection 0: Select external CH3 (from IOM) signal...
Page 261: Control Register 2 (Timx_Ctrl2)
Bit Field Name Description Direction 0: Up-counting 1: Down-counting Note: this bit is read-only when the counter is configured in center-aligned mode or encoder mode. ONEPM One-pulse mode 0: Disable one-pulse mode, the counter counts are not affected when an update event occurs. 1: Enable one-pulse mode, the counter stops counting when the next update event occurs (clearing TIMx_CTRL1.CNTEN bit) UPRS...
Page 262: Slave Mode Control Register (Timx_Smctrl)
Bit Field Name Description 15:9 Reserved Reserved, the reset value must be maintained ETRSEL External Triggered Selection memory (ETR Selection) 0: Select external ETR (from IOM) signal; 1: Reserved TI1SEL TI1 selection 0: TIMx_CH1 pin connected to TI1 input. 1: TIMx_CH1, TIMx_CH2, and TIMx_CH3 pins are XOR connected to the TI1 input. MMSEL[2:0] Master Mode Selection These 3 bits (TIMx_CTRL2.
Page 263 Bit Field Name Description EXTP External trigger polarity This bit is used to select whether the trigger operation is to use ETR or the inversion of ETR. 0: ETR active at high level or rising edge. 1: ETR active at low level or falling edge. EXCEN External clock enable This bit is used to enable external clock mode 2, and the counter is driven by any active edge on...
Page 264 Bit Field Name Description 1111: f /32, N = 8 SAMPLING MSMD Master/ Slave mode 0: No action 1: Events on the trigger input (TRGI) are delayed to allow a perfect synchronization between the current timer (via TRGO) and its slaves. This is useful when several timers are required to be synchronized to a single external event.
Page 265: Dma/Interrupt Enable Registers (Timx_Dinten)
Bit Field Name Description 111: External clock mode 1. The counter is clocked by the rising edge of the selected trigger input (TRGI). Note: do not use gated mode if TI1F_ED is selected as the trigger input (TIMx_SMCTRL.TSEL=100). This is because TI1F_ED outputs a pulse for each TI1F transition, whereas gated mode checks the level of the triggered input.
Page 266: Status Registers (Timx_Sts)
Bit Field Name Description Reserved Reserved, the reset value must be maintained TIEN Trigger interrupt enable 0: Disable trigger interrupt 1: Enable trigger interrupt Reserved Reserved, the reset value must be maintained CC4IEN Capture/Compare 4 interrupt enable 0: Disable capture/compare 4 interrupt 1: Enable capture/compare 4 interrupt CC3IEN Capture/Compare 3 interrupt enable...
Page 267: Event Generation Registers (Timx_Evtgen)
Bit Field Name Description Reserved Reserved, the reset value must be maintained TITF Trigger interrupt flag This bit is set by hardware when an active edge is detected on the TRGI input when the slave mode controller is in a mode other than gated. This bit is set by hardware when any edge in gated mode is detected.
Page 268: Capture/Compare Mode Register 1 (Timx_Ccmod1)
Reset values: 0 x0000 Bit Field Name Description 15：7 Reserved Reserved, the reset value must be maintained. Trigger generation This bit can generate a trigger event when set by software. And at this time TIMx_STS.TITF = 1, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be generated.
Page 269 Channels can be used for input (capture mode) or output (compare mode), and the direction of the channel is defined by the corresponding CCxSEL bit. The other bits of the register act differently in input and output modes. OCx describes the function of a channel in output mode, ICx describes the function of a channel in input mode. Hence, please note that the same bit can have different meanings for output mode and for input mode.
Page 270 Bit Field Name Description Note 1: In PWM mode 1 or PWM mode 2, the OC1REF level changes only when the comparison result changes or when the output compare mode is switched from frozen mode to PWM mode. OC1PEN Output Compare 1 preload enable 0: Disable preload function of TIMx_CCDAT1 register.
Page 271 Bit Field Name Description CC2SEL[1:0] Capture/Compare 2 selection These bits are used to select the input/output and input mapping of the channel 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 272: Capture/Compare Mode Register 2 (Timx_Ccmod2)
10.4.9 Capture/Compare Mode Register 2 (TIMx_CCMOD2) Offset address: 0x1C Reset value: 0x0000 See the description of the CCMOD1 register above Output comparison mode: Bit Field Name Description OC4CEN Output compare 4 clear enable 14:12 OC4MD[2:0] Output compare 4 mode OC4PEN Output compare 4 preload enable OC4FEN Output compare 4 fast enable...
Page 273: Capture/Compare Enable Registers (Timx_Ccen)
Bit Field Name Description 11:10 IC4PSC[1:0] Input Capture 4 Prescaler CC4SEL[1:0] Capture/Compare 4 selection These bits are used to select the input/output and input mapping of the channel 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 274: Counters (Timx_Cnt)
Bit Field Name Description CC2EN Capture/Compare 2 output enable See TIMx_CCEN.CC1EN description. Reserved Reserved, the reset value must be maintained CC1P Capture/Compare 1 output polarity When the corresponding channel of CC1 is in output mode: 0: OC1 active high 1: OC1 active low When the corresponding channel of CC1 is in input mode: At this time, this bit is used to select whether IC1 or the inverse signal of IC1 is used as the trigger or capture signal.
Page 275: Prescaler (Timx_Psc)
10.4.12 Prescaler (TIMx_PSC) Offset address: 0x28 Reset value: 0x0000 Bit Field Name Description 15:0 PSC[15:0] Prescaler value Counter clock f / (PSC [15:0] +1). CK_CNT CK_PSC Each time an update event occurs, the PSC value is loaded into the active prescaler register. 10.4.13 Auto-Reload Register (TIMx_AR) Offset address: 0x2C Reset values: 0xFFFF...
Page 276: Capture/Compare Register 2 (Timx_Ccdat2)
Bit Field Name Description CCDAT1 contains the counter value transferred by the last input capture 1 event (IC1). When configured as input mode, register CCDAT1 is only readable. When configured as output mode, register CCDAT1 is readable and writable. 10.4.15 Capture/Compare Register 2 (TIMx_CCDAT2) Offset address: 0x38 Reset value: 0x0000 Bit Field...
Page 277: Capture/Compare Register 4 (Timx_Ccdat4)
Bit Field Name Description CCDAT3 contains the counter value transferred by the last input capture 3 event (IC3). When configured as input mode, register CCDAT3 is only readable. When configured as output mode, register CCDAT3 is readable and writable. 10.4.17 Capture/Compare Register 4 (TIMx_CCDAT4) Offset address: 0x40 Reset value: 0x0000 Bit Field...
Page 278: Dma Transfer Buffer Register (Timx_Daddr)
Bit Field Name Description Reserved Reserved, the reset value must be maintained. DBADDR[4:0] DMA Base Address This bit field defines the first address where the DMA accesses the TIMx_DADDR register. When access is done through the TIMx_DADDR first time, this bit-field specifies the address you just access.
Page 279 Bit Field Name Description TIMx_CCDAT4 register; 279 / 526...
Page 280: Basic Timers (Tim6)
11 Basic Timers (TIM6) 11.1 Basic Timers Introduction The basic timer contains a 16-bit auto-reloading counter. 11.2 Main Features Of Basic Timers • 16-bit auto-reload up-counting counters. • 16-bit programmable prescaler. (The prescaler factor can be configured with any value between 1 and 65536) •...
Page 281: Counter Mode
factor between 1 and 65536. Because this controller has a buffer, it can be dynamically changed at runtime.. The new prescaler value will only be adopted during the next update event. Figure 11-2 Counter Timing Diagram With Prescaler Division Change From 1 To 4 CNTEN CK_PSC Timer Clock = CK_CNT...
Page 282: Figure 11-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
prescaler value will remain unchanged). The figures below shows some examples of the counter behavior and the update flags for different division factors in the up-counting mode. Figure 11-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N Internal clock divided by 2 CNTEN...
Page 283: Figure 11-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 11-4 Timing Diagram Of The , Update Event When ARPEN=0/1 Up-Counting ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 284: Clock Selection
11.3.3 Clock Selection • The internal clock of timer: CK_INT 11.3.3.1 Internal clock source (CK_INT) Assuming that the TIMx_CTRL1.CNTEN bit is written as' 1 ' by software, the clock source of the prescaler is provided by the internal clock CK_INT. Figure 11-5 Control Circuit In Normal Mode, Internal Clock Divided By 1 CEN=CNTEN Internal clock...
Page 285: Register Overview
11.4.1 Register Overview Table 11-1 Register Overview Offs Register TIMx_CTRL 000h Reset Value 004h Reserved 008h Reserved TIMx_DINT 00Ch Reset Value TIMx_STS 010h Reset Value TIMx_EVTG 014h Reset Value 018h Reserved 01Ch Reserved 020h Reserved TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC PSC[15:0] 028h...
Page 286: Dma/Interrupt Enable Registers (Timx_Dinten)
Bit Field Name Description 15:8 Reserved Reserved, the reset value must be maintained ARPEN ARPEN: Auto-reload preload enable 0: Shadow register disable for TIMx_AR register 1: Shadow register enable for TIMx_AR register Reserved Reserved, the reset value must be maintained ONEPM One-pulse mode 0: Disable one-pulse mode, the counter counts are not affected when an update event occurs.
Page 287: Status Registers (Timx_Sts)
Bit Field Name Description UDEN Update DMA Request enable 0: Disable update DMA request 1: Enable update DMA request Reserved Reserved, the reset value must be maintained UIEN Update interrupt enable 0: Disable update interrupt 1: Enables update interrupt 11.4.4 Status Registers (TIMx_STS) Offset address: 0x10 Reset value: 0x0000 Bit Field...
Page 288: Counters (Timx_Cnt)
11.4.6 Counters (TIMx_CNT) Offset address: 0x24 Reset value: 0x0000 Bit Field Name Description 15:0 CNT[15:0] Counter value 11.4.7 Prescaler (TIMx_PSC) Offset address: 0x28 Reset value: 0x0000 Bit Field Name Description 15:0 PSC[15:0] Prescaler value PSC register value will be updated to prescaler register at update event. Counter clock frequency is input clock frequency divide PSC + 1.
Page 289: Low Power Timer (Lptim)
12 Low Power Timer (LPTIM) 12.1 Introduction The LPTIM is a 16-bit timer with multiple clock sources, it can keep running in all power modes except for PD mode. LPTIM can run without internal clock source, it can be used as a “pulse counter”. In addition, the LPTIM can wake up the system from low-power modes, to realize “Timeout functions”...
Page 290: Block Diagram
12.3 Block Diagram Figure 12-1 LPTIM Diagram APB Interface LPTIM Up to 6 exti trigger Glitch Software filter trigger 16bit ARR Mux trigger CLK MUX APB clock prescaler 16bit counter COMP1_OUT Count mode 16bit compare Up/down Glitch Encoder Input2 filter Non- Glitch encoder...
Page 291: Prescaler
LPTIM_CFG.CLKSEL and LPTIM_CFG.CNTMEN bits are for the clock source configuration. The active clock edge is configured by LPTIM_CFG.CLKPOL[1:0] bits. When the LPTIM only uses external clock source. It can only select one active clock edge. LPTIM can select both active clock edges only when it is using internal clock source or both external and internal clock sources. Note: when both effective edges for external clock are active, LPTIM needs to use an internal clock to oversample the external clock.
Page 292: Timer Enable
Figure 12-2 Glitch Filter Timing Diagram 2 consecutive samples 2 consecutive samples Filtered Filter out Input CLKMUX Note: if no internal clock is used, the glitch filter needs to be turned off by clearing LPTIM_CFG.CLKFLT[1:0] and LPTIM_CFG.TRIGFLT[1:0] bits. If glitch filter is not used, user can use digital filter in comparator or external analog filter to filter glitches.
Page 293: Operating Mode
RTC alarm B RTC_TAMP1 RTC_TAMP2 COMP_OUT 12.4.6 Operating Mode The LPTIM has two operating modes: • Continuous mode: A trigger event will start the LPTIM and it will continue running until the user switched off the LPTIM. • One-shot mode: A trigger event will start the LPTIM and it will stop when the counter value reached LPTIM_ARR.ARRVAL[15:0].
Page 294: Figure 12-4 Ptim Output Waveform, Single Counting Mode Configuration
LPTIM_CTRL.TSTCM bit to 1 will switch the LPTIM to continuous counting mode. Counter will restart as soon as LPTIM_ARR register value is reached if timer enable. One-shot mode: LPTIM_CTRL.SNGMST bit must be set to enable the one-shot mode. A trigger event will re-start the LPTIM. Hardware will ignore all the trigger events after the internal counter starts and before the counter value equal to LPTIM_ARR.ARRVAL[15:0] value.
Page 295: Waveform Generation
Figure 12-5 LPTIM Output Waveform, Single Counting Mode Configuration And Set-Once Mode Activated LPTIM_ARR Compare Discarded trigger External trigger event In case of software start (LPTIM_CFG.TRGEN[1:0] = ‘00’), the LPTIM_CTRL.SNGMST setting will start the counter for one-shot counting. 12.4.7 Waveform Generation The LPTIM auto-reload register (LPTIM_ARR) and compare register (LPTIM_COMP) are used for generating LPTIM output waveforms.
Page 296: Register Update
Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. The clock prescaler by 2 can only be achieved when LPTIM counter counts the internal clock effectively.(i.e. LPTIM_CFG.CLKSEL = 0, LPTIM_CFG.CLKPOL[1:0] LPTIM_COMP.CMPVAL[15:0] ’d1 (50% duty cycle)/’d2, LPTIM_ARR.ARRVAL[15:0] = ’d2.
Page 297: Counter Mode
The LPTIM INTSTS.ARRUPD flag and the LPTIM INTSTS.CMPUPD flag indicate when the write operation is completed to respectively the LPTIM ARR register and the LPTIM COMP register. After a write to the LPTIM ARR register or the LPTIM COMP register, any successive write before respectively the LPTIM _INTSTS.ARRUPD flag or the LPTIM_INTSTS.CMPUPD flag be set, will lead to unpredictable results.
Page 298 The change of counting direction is updated by LPTIM_INTSTS.DOWN and LPTIM_INTSTS.UP flags. Also, an interrupt can be generated for both direction change events if enabled through the LPTIM_INTEN register. User can enable Encoder mode by setting LPTIM_CFG.ENC bit. And the LPTIM need to be configured in continuous mode first.
Page 299: Non-Quadrature Encoder Mode
Figure 12-7 Encoder Mode Counting Sequence Coutnter Down 12.4.11 Non-Quadrature Encoder Mode This mode allows handling signals from non-quadrature encoders, which is used to detect sub-sequent positive pulses from external interface. Non-Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to 0 depending on the direction).
Page 300: Timeout Function
The following two waveforms, the decoder module can operate properly, when there is no case that both Input1 and Input2 are high. Figure 12-8 Input Waveforms Of Input1 And Input2 When The Decoder Module Is Working Normally Input1 Input1 Input2 Input2 NON-Encoder mode counting up NON-Encoder mode counting down...
Page 301: Lptim Registers
• Auto-reload match (whatever the direction if encoder mode) • External trigger event • Auto-reload register write completed • Compare register write completed • Direction change (encoder mode), programmable(up / down / both). Note: if any bit in the LPTIM_INTEN register (Interrupt Enable Register) is set after that its corresponding flag in the LPTIM_INTSTS register (Status Register) is set, the interrupt is not asserted.
Page 302: Lptim Interrupt And Status Register (Lptim_Intsts)
Offset Register LPTIM_CTRL 010h Reserved Reset Value LPTIM_CMP CMPVAL[15:0] 014h Reserved Reset Value LPTIM_ARR ARRVAL[15:0] 018h Reserved Reset Value LPTIM_CNT CNTVAL[15:0] 01Ch Reserved Reset Value 12.5.2 LPTIM Interrupt And Status Register (LPTIM_INTSTS) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:7...
Page 303: Lptim Interrupt Clear Register (Lptim_Intclr)
Bit Field Name Description Hardware sets EXTRIG to inform application that a valid external trigger edge has occurred. If the trigger is discarded when timer has already started, then this flag is not set. ARRM Auto-reload match. Hardware set this to inform application that LPTIM_CNT register value reached the LPTIM_ARR register's value.
Page 304: Lptim Configuration Register (Lptim_Cfg)
Bit Field Name Description 31:7 Reserved Reserved, the reset value must be maintained. DOWNIE Direction change to down interrupt enable 0: DOWN interrupt disabled 1: DOWN interrupt enabled UPIE Direction change to up interrupt enable 0: UP interrupt disabled 1: UP interrupt enabled ARRUPDIE Auto reload register update succeeded interrupt enable bit.
Page 305 Bit Field Name Description 1: Non-Orthogonal mode enabled Encoder mode enable 0: Encoder mode disabled 1: Encoder mode enabled CNTMEN Counter mode enabled The CNTMEN bit selects clock source for the LPTIM counter: 0: Counter is incremented following each internal clock pulse 1: Counter is incremented following each valid clock pulse on the LPTIM external Input1 RELOAD...
Page 306 Bit Field Name Description 010: RTC alarm B 011: RTC_TAMP1 100: RTC_TAMP2 101: Reserved 110: COMP_OUT 111: Reserved Reserved Reserved, the reset value must be maintained. 11:9 CLKPRE[2:0] Clock division factor bit. 000: / 1 001: / 2 010: / 4 011: / 8 100: / 16 101: / 32...
Page 307: Lptim Control Register (Lptim_Ctrl)
Bit Field Name Description 00: The rising edge is the active edge used for counting 01: The falling edge is the active edge used for counting 10: Both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency.
Page 308: Lptim Compare Register (Lptim_Comp)
Bit Field Name Description starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled.
Page 309 Reset value: 0x0000 0000 Reserved CNTVAL[15:0] Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 CNTVAL[15:0] Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Page 310: Independent Watchdog (Iwdg)
13 Independent Watchdog (IWDG) 13.1 Introduction The N32G030 has embedded independent watchdog (IWDG) and window watchdog (WWDG) timers to solve the problems caused by software errors. The watchdog timer is very flexible to use, which improves the security of the system and the accuracy of timing control.
Page 311: Function Description
13.3 Function Description Figure 13-1 Functional Block Diagram Of The Independent Watchdog Module User Program 30KHz IWDG_KEY.KEYV == 0x5555 IWDG_PREDIV.PD IWDG_STS.PVU 4/8/16/32/64/128/256 Counter == 0 IWDG_RELV.REL 12 Bit IWDG Reset 12-bit reload value Down Counter IWDG_STS.CRVU Reload Enable IWDG_KEY.KEYV To enable IWDG, we need to write 0xCCCC to IWDG_KEY.KEYV[15:0] bits. Counter starts counting down from reset value (0xFFF).
Page 312: User Interface
on DBG_CTRL.IWDG_STOP bit in debug module. If this bit is set to ‘1’, the counter stops. If this bit is set to ‘0’, the counter operate normally. For details, refer to 3.3.2 Peripheral Debugging Support. 13.4 User Interface IWDG module user interface contains 4 registers: key register (IWDG_KEY), pre-scale register (IWDG_PREDIV), reload register (IWDG_RELV) and status register (IWDG_STS).
Page 313: Iwdg Registers
13.5 IWDG Registers 13.5.1 IWDG Register Overview Table 13-2 IWDG Register Overview Offset Register IWDG_KEY KEYV[15:0] 0x00 Reserved Reset value IWDG_PREDIV PD[2:0] 0x04 Reserved Reset value IWDG_RELV REL[11:0] 0x08 Reserved Reset value IWDG_STS 0x0C Reserved Reset value 13.5.2 IWDG Key Register (IWDG_KEY) Address offset: 0x00 Reset value: 0x00000000 Bit Field...
Page 314: Iwdg Reload Register (Iwdg_Relv)
Bit Field Name Description 31:3 Reserved Reserved, the reset value must be maintained. PD[2:0] Prescaler factor Prescaler divider: with write access protection when IWDG_KEY.KEYV[15:0] is not 0x5555. The IWDG_STS.PVU bit must be 0 otherwise PD [2:0] value cannot be changed. Divide number is as follow: 000: divider /4 001: divider /8...
Page 315: Iwdg Status Register (Iwdg_Sts)
13.5.5 IWDG Status Register (IWDG_STS) Address offset: 0x0C Reset value: 0x00000000 Bit Field Name Description 31:2 Reserved Reserved, the reset value must be maintained. CRVU Watchdog reload value update Reload Value Update: this bit indicates an update of reload value is ongoing. Set by hardware and clear by hardware.
Page 316: Function Description
14.3 Function Description If the watchdog is activated (the WWDG_CTRL.ACTB bit), when the 7-bit (WWDG_CTRL.T[6:0]) down-counter reaches 0x3F(WWDG_CTRL.T6 bit is cleared), or the software reloads the counter when the counter value is greater than the value of the window register, a system reset will be generated. In order to avoid system reset, the software must periodically refresh the counter value in the window during normal operation.
Page 317: Timing For Refresh Watchdog And Interrupt Generation
14.4 Timing For Refresh Watchdog And Interrupt Generation Figure 14-2 Refresh Window And Interrupt Timing Of WWDG CNT DownCounter Refresh not allowed Refresh allowed T[6:0] W[6:0] 0x3F Time TIMERB × 4096 × 2 PCLK 0x41 0x40 0x3F WWDG_EWINT EWINTF = 0 Reset T[6] value Watchdog refreshing window is between WWDG_CFG.W[6:0] value (maximum value 0x7F) and 0x3F, refresh...
Page 318: Debug Mode
Table 14-1 Maximum And Minimum Counting Time Of WWDG Min Timeout Value(ΜS) Max Timeout Value(Ms) TIMERB T[5:0] = 0x00 T[5:0] = 0x3f 85.33 5.46 170.67 10.92 341.33 21.85 682.67 43.68 14.5 Debug Mode In debug mode (Cortex ® -M0 core stops), WWDG counter will either continue to operate normally or stops, depending on DBG_CTRL.WWDG_STOP bit in debug module.
Page 319: Wwdg Control Register (Wwdg_Ctrl)
14.7.2 WWDG Control Register (WWDG_CTRL) Address offset : 0x00 Reset value : 0x0000007F Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. ACTB Activation bit When ACTB=1, the watchdog can generate a reset. This bit is set by software and only cleared by hardware after a reset.
Page 320 Reset value : 0x0000 Bit Field Name Description 31:1 Reserved Reserved, the reset value must be maintained. EWINTF Early wake-up interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’.
Page 321: Analog To Digital Conversion (Adc)
15 Analog To Digital Conversion (ADC) 15.1 Introduction The 12-bit ADC is a high-speed analog-to-digital converter using successive approximation. It has 16 channels which can measure 12 external and 4 internal signal sources. The A/D conversion of each channel has four execution modes: single, continuous, scan and discontinuous.
Page 322: Function Description
• Data alignment with embedded data consistency • Both regular conversions and injection conversions can be externally triggered • ADC power requirements: 2.4V to 5.5V • ADC input voltage range: 0≤ V ≤V • ADC injection channel supports software-configurable OPA forward voltage input channel switching 15.3 Function Description 15-1 is a functional block diagram of an ADC.
Page 323: Adc Clock
Table 15-1 ADC Pins Name Signal Types Annotations Input, analog power supply Equivalent to V analog power supply and: 1.8V ≤ V ≤ (5.5V) Input, analog power supply ground Equivalent to V Analog power supply ground Input, analog reference positive Positive voltage reference used by ADC, 2.4V ≤...
Page 324: Adc Switch Control
Figure 15-2 ADC Clock PLL_DIV_CLK ADC_CLK HCLK HCLK ADC_1MCLK 1MCLK 15.3.2 ADC Switch Control You can proceed to the next step only after the power-up process is complete. You can check if the power-up is complete by polling the ADC_CTRL3.RDY bit. You can set the ADC_CTRL2.ON bit to turn on the ADC.
Page 325: Single Conversion Mode
• Internal voltage reference V is connected to channel ADC_IN14 REFP • VDDA pin voltage is connected to channel ADC_IN15 • ADC_IN6 can be connected to internal OPAMP_OUT besides IO Internal channels can be converted by injection or regular channels. Note: V needs to be enabled by configuring ADC_CTRL3.
Page 326: Analog Watchdog
Figure 15-3 Timing Diagram ADC_CLK Set ON to 1 ADC power on Start first conversion Start next conversion Next ADC Conversion ADC Conversion Conversion Time （total conv time） ENDC STAB ENDC is set to 0 by software 15.3.8 Analog Watchdog The analog watchdog can be enabled on the regular channel by setting ADC_CTRL1.AWDGERCH to 1, or the analog watchdog on the injection channel can be enabled by setting ADC_CTRL1.AWDGEJCH to 1.
Page 327: Scan Mode
15.3.9 Scan Mode By configuring ADC_CTRL1.SCAMD to 1, the scan conversion mode can be turned on, and by configuring the four registers ADC_RSEQ1, ADC_RSEQ2, ADC_RSEQ3, ADC_JSEQ, the conversion sequence can be selected, and the ADC will scan and convert all the selected channels. After the conversion is started, the channels will be converted one by one.
Page 328: Discontinuous Mode
Figure 15-4 Injection Conversion Delay ADC clock Injected event Latency Note:for the maximum delay value, please refer to the electrical characteristics section in the data manual. 15.3.11 Discontinuous Mode 15.3.11.1 Regular channels Configure ADC_CTRL1.DREGCH to 1 to enable the discontinuous mode on the regular channel, obtain the regular sequence by configuring ADC_RSEQ1, ADC_RSEQ2, ADC_RSEQ3, and configure ADC_CTRL1.DCTU[2:0] to control the conversion of n channels after each trigger.
Page 329: Data Aligned
automatic injection function and discontinuous mode cannot be set at the same time. 15.4 Data Aligned There are two alignment methods for data memory after conversion: left-aligned and right-aligned. The alignment can be set by the ADC_CTRL2.ALIG bit. ADC_CTRL2.ALIG = 0 is right-aligned, as shown in Table 15-3, ADC_CTRL2.ALIG = 1 is left-aligned, as shown inTable 15-4.
Page 330: Dma Requests
source selection is shown in the table below. If you select EXTI line 0~15 or TIM8_TRGO as the external trigger source, you can set the AFIO _CFG.ADC_ETRR and AFIO _CFG.EXTI_ETRR[3:0] bits to implement; if you select SWSTRRCH as the external trigger source, you can start the regular channel conversion by setting ADC_CTRL2.SWSTRRCH to 1.
Page 331: Temperature Sensor
15.8 Temperature Sensor Set the ADC_CTRL2.TEMPEN bit to 1, enable the temperature sensor, and use the temperature sensor to detect the ambient temperature when the device isoperating. The output voltage sampled by the temperature sensor is converted to a digital value by the ADC_IN12 channel. When the temperature sensor is operating, the recommended sampling time is 17.1us;...
Page 332: Adc Interrupt
Temperature (°C) = {(V ) / Avg_Slope} + 25 SENSE In which: at 25 degrees Celsius SENSE Avg_Slope = temperature and V Average slope of a curve (mV/°C or μV/°C) SENSE Refer to the values of V and Avg_Slope in the electrical characteristics chapter of the datasheet. Note: there is a settling time before the sensor wakes up from the power-off mode to the correct output of VSENSE;...
Page 333: Table 15-8 Opa Channel Selection
Figure 15-6 TIM1 CC4 Triggers OPA Channel Switching ADC Injection Sampling Control OPA signal switching TIM_CC4 control The ADC_OPACTRL.JSQx_OPAEN register and ADC_JSEQ.JLEN [1:0] can be used together to select which of the 4 samples enables the control of the OPA channel. Software can select the OPA channel corresponding to each sample by setting the ADC_OPACTRL.JSQ1_OPASEL, ADC_OPACTRL.JSQ2_OPASEL, ADC_OPACTRL.JSQ3_OPASEL and ADC_OPACTRL.JSQ4_OPASEL.
Page 334 Since the OPA channel needs a certain setup time after switching, the software can configure the ADC_OPACTRL.OPA_SETUP_TIME. After switching the OPA channel, the ADC will wait for the corresponding setup time before starting sampling. The setup time is calculated as follows: T= ADC_OPACTRL.OPA_SETUP_TIME/adc clock frequency.
Page 335: Adc Registers
15.11 ADC Registers 15.11.1 ADC Register Overview Table 15-9 ADC Register Overview Offset Register ADC_STS 000h Reserved Reset Value ADC_CTRL1 DCTU[2:0] AWDGCH[3:0] 004h Reserved Reset Value ADC_CTRL2 008h Reserved Reset Value ADC_SAMPT1 00Ch Reserved Reset Value ADC_SAMPT2 010h Reset Value ADC_SAMPT3 014h Reset Value...
Page 336: Adc Status Register (Adc_Sts)
ADC_JDAT4 JDAT4[15:0] 04Ch Reserved Reset Value ADC_DAT DAT[15:0] 050h Reserved Reset Value ADC_CTRL3 054h Reserved Reset Value ADC_TEST 058h Reserved Reset Value ADC_OPACTRL OPA_SETUP_TIME[9:0] 05Ch Reserved Reset Value 15.11.2 ADC Status Register (ADC_STS) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description...
Page 337: Adc Control Register 1 (Adc_Ctrl1)
Bit Field Name Description 1: Injection sequence channel conversion has started. JENDC Injected channel end of conversion This bit is set by hardware at the end of all injection sequence channel conversions and cleared by software 0: Conversion is not complete. 1: Conversion is complete.
Page 338 Bit Field Name Description receiving an external trigger in intermittent mode 000: 1 channel 001: 2 channels 111: 8 channels DJCH Discontinuous mode on injected channels This bit is set and cleared by the software. It is used to turn on or off discontinuous mode on injected channels.
Page 339 Bit Field Name Description 0: Disable analog watchdog interruption. 1: Enable analog watchdog interruption. ENDCIEN Interrupt enable for any channels This bit is set and cleared by the software to disallow or allow interrupts to occur after the regular channel conversion ends. 0: Disable ENDC interruption.
Page 340 Bit Field Name Description 0: Reset state. 1: Starts converting the regular channel. SWSTRJCH Start conversion of injected channels This bit is set by the software to initiate the conversion and can be cleared by the software or by the hardware as soon as the conversion begins. If SWSTRJCH is selected as the trigger event in the ADC_CTRL2.EXTJSEL[2:0] bit, which is used to initiate a conversion of a set of injected channels 0: Reset state.
Page 341: Adc Sampling Time Register 1 (Adc_Sampt1)
Bit Field Name Description Reserved Reserved,the reset value must be maintained Continuous conversion This bit is set and cleared by the software. If this bit is set, the conversion continues until the bit is cleared. 0: Single conversion mode. 1: Continuous conversion mode. A/D converter ON/OFF This bit is set and cleared by the software.
Page 342: Adc Sampling Time Register 3 (Adc_Sampt3)
Bit Field Name Description bit must remain constant during the sampling period. 0000: 6 cycles 1000: 88 cycles 0001: 8 cycles 1001: 120 cycles 0010: 14 cycles 1010: 182 cycles 0011: 20 cycles 1011: 240 cycles 0100: 29 cycles 1100: 300 cycles 0101: 42 cycles 1101: 400 cycles 0110: 56 cycles...
Page 343: Adc Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1
15.11.8 ADC Injected Channel Data Offset Register X (ADC_JOFFSETx) (x=1…4) Address offset: 0x18-0x24 Reset value: 0x0000 0000 Bit Field Name Description 31:12 Reserved Reserved,the reset value must be maintained 11:0 OFFSETJCHx[11:0] Data offset for injected channel x These bits define the values used to subtract from the original conversion data when the conversion is injected into the channel.
Page 344: Adc Regular Sequence Register 1 (Adc_Rseq1)
Bit Field Name Description 11:0 LTH[11:0] Analog watchdog low threshold These bits define the low thresholds for analog watchdog. 15.11.11 ADC Regular Sequence Register 1 (ADC_RSEQ1) Address offset: 0x30 Reset value: 0x0000 0000 Bit Field Name Description 31:24 Reserved Reserved,the reset value must be maintained 23:20 LEN[3:0] Regular channel sequence length...
Page 345: Adc Regular Sequence Register 3 (Adc_Rseq3)
Bit Field Name Description 31:29 Reserved Reserved,the reset value must be maintained 28:25 SEQ12[3:0] 12th conversion in regular sequence These bits are software-defined as the number (0 to 15) of the 12th conversion channel in the conversion sequence. Reserved Reserved,the reset value must be maintained 23:20 SEQ11[3:0] 11th conversion in regular sequence...
Page 346: Adc Injection Sequence Register (Adc_Jseq)
15.11.14 ADC Injection Sequence Register (ADC_JSEQ) Address offset: 0x3C Reset value: 0x0000 0000 Bit Field Name Description 31:22 Reserved Reserved,the reset value must be maintained 21:20 JLEN[1:0] Injected sequence length These bits are software-defined as the number of channels in the injected channel conversion sequence.
Page 347: Adc Regulars Data Register (Adc_Dat)
Bit Field Name Description 31:16 Reserved Reserved,the reset value must be maintained 15:0 JDATx[15:0] Injected data for conversions These bits are read-only and contain the conversion results of the injected channel. The data is left- aligned or right-aligned 15.11.16 ADC Regulars Data Register (ADC_DAT) Address offset: 0x50 Reset value: 0x0000 0000 Reserved...
Page 348: Adc Test Register (Adc_Test)
Bit Field Name Description Reserved Reserved, the value is forcibly set to 1. PDRDY ADC power ready 0：ADC is powered on 1：ADC is powered down ADC ready 0: Not ready 1: Get ready CKMOD Clock mode 0: Select AHB for synchronization clock 1: Select PLL for asynchronous clock Reserved Reserved,the reset value must be maintained...
Page 349 Reset value: 0x0000 0000 Bit Field Name Description 31:26 Reserved Reserved,the reset value must be maintained 25:16 OPA_SETUP_TIME[9:0] Setup time for OPA mux 0: 0 ADC clock cycles 1: 1 ADC clock cycles 1023: 1023 ADC clock cycles 15:13 JSQ4_OPASEL[2:0] Injected channel 4 for OPA mux selection 12:10 JSQ3_OPASEL [2:0]...
Page 350: Comparator (Comp)
16 Comparator (COMP) The COMP module is used to compare the magnitude of the two input analog voltages, and output high/low levels according to the comparison result. When the "INP" input voltage is higher than the "INM" input voltage, the comparator output is high, and when the "INP"...
Page 351: Comp Configuration Precedure
• Configurable filter window size • Configurable filter threshold size • Configurable sampling frequency for filtering 16.3 COMP Configuration Precedure The complete configuration items are as follows. If the default configuration is used, skip the corresponding configuration items. Configurable hysteresis level COMP_CTRL.HYST[1:0] Configure the output polarity COMP_CTRL.POL Configure input selection, comparator non-inverting input COMP_CTRL.INPSEL[3:0], inverting input COMP_CTRL.
Page 352: Interrupt
INPSEL COMP VREF The comparator INM pins have the following configuration. INMSEL COMP VREF Comparator output TRIG signal has the following interconnection. TRIG COMP 0000 0001 TIM1_BKIN 0010 TIM1_IC1 0011 TIM1_OCrefclear 0100 TIM8_IC1 0101 TIM8_OCrefclear 0110 TIM3_IC1 0111 TIM3_OCrefclear 1000 1001 1010 1011...
Page 353: Comp Register
16.7 COMP Register 16.7.1 COMP Register Overview Table 16-1 COMP Register Overview Offset Register COMP_INTEN 000h Reserved Reset Value COMP_INTSTS 03Ch Reserved Reset Value 008h Reserved COMP_LOCK 00Ch Reserved Reset Value COMP_CTRL BLKING[2:0] OUTTRG[3:0] INPSEL[1:0] INMSEL[1:0] 010h Reserved Reset Value COMP_FILC SAMPWIN[4:0] THRESH[4:0]...
Page 354: Comp Interrupt Register (Comp_Intsts)
Bit Field Name Description 31:1 Reserved Reserved，the reset value must be maintained CMPIEN COMP interrupt enable 0: disable 1: enable 16.7.3 COMP Interrupt Register (COMP_INTSTS) Address offset : 0x04 Reset value : 0x0000 0000 Bit Field Name Description 31:1 Reserved Reserved，the reset value must be maintained CMPIS interrupt status of COMP...
Page 355 Bit Field Name Description 31:21 Reserved Reserved，the reset value must be maintained CLKSEL COMP operating clock selection 0: System clock (SYSCLK) 1: Low-speed working clock, can work in STOP mode or LPRUN mode. PWRMD COMP power select 0: normal mode 1: Low power mode Reserved Reserved，the reset value must be maintained...
Page 356: Comp Filter Control Register (Comp_Filc)
Bit Field Name Description 1100: TIM8_BKIN 1101: LPTIM_ETR 1110: Reserved 1111: Reserved Reserved Reserved, the reset value must be maintained INPSEL[2:0] COMP positive select 00: PA1 01: PA3 10: VREF 11: PA7 Reserved Reserved, the reset value must be maintained INMSEL[2:0] COMP negative input select 00: VREF...
Page 357: Comp Reference Input Compare Voltage Register (Comp_Invref)
Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 CLKPSC[15:0] Low filter sample clock prescale. System clock divider = CLK_PRE_CYCLE + 1, e.g. 0: Every cycle 1: Every 2 cycle 2: Every 3 cycle … 16.7.8 COMP Reference Input Compare Voltage Register (COMP_INVREF) Address offset : 0x40 Reset value : 0x0000 0000...
Page 358: Interface
17 I C Interface 17.1 Introduction The I C(Inter-Integrated Circuit) bus is a widely used bus structure, it has only two bidirectional lines, the data bus SDA and clock bus SCL. All devices compatible with I C bus can communicate directly with each other through I bus with these two lines.
Page 359: Software Communication Process
output of device which is connected to the bus must have open drain or open collector to provide wired-and functionality. The data on I C bus can reach 100 kbit/s in standard mode and 1000 kbit/s in fast mode. Since devices of different processors may be connected to the I C bus, the levels of logic '0' and logic '1' are not fixed and depend on the actual level of VDD.
Page 360: Figure 17-1 I2C Functional Block Diagram
Figure 17-1 I C Functional Block Diagram Data Shift register Data register control GPIO Own address register Comparator calculation Dual address register PEC register Clock Clock Control Register control GPIO Control Register Control SMBALERT logic Status Register Interrupts DMA requests Note: in SMBus mode, SMBALERT is an optional signal.
Page 361: Clock Synchronization
• SDA and SCL are open-drain configurations, and the signal "wire-and" logic is realized through an external pull-up resistor. • SDA and SCL pins will also detect the level on the pin while outputting the signal to check whether the output is consistent with the previous output.
Page 362 software. After the I C slave detects the start bit on the I C bus, it starts to receive the address from the bus, and compares the received address with its own address. Once the two addresses are matched, the I C slave will transmit an acknowledgement (ACK) and respond to subsequent commands on the bus: transmit or receive the requested data.
Page 363: Figure 17-3 Slave Transmitter Transfer Sequence Diagram
Figure 17-3 Slave Transmitter Transfer Sequence Diagram 7-bit address Slave Slave Master Master Slave Master Slave Master Master Master Start Address(R) Data1 Data2 DataN NACK Stop EV1 EV3-1 EV3-2 10-bit address Master Slave Master Slave Master Master Slave Slave Master Slave Master Master...
Page 364: Figure 17-4 Slave Receiver Transfer Sequence Diagram
5. When the slave detects the STOP bit on I C bus, set I2C_STS1.STOPF to 1, and if the I2C_CTRL2.EVTINTEN bit is set, an interrupt will be generated. The software clears the I2C_STS1.STOPF bit by reading the I2C_STS1 register before writing the I2C_CTRL1 register (see EV4 in the following figure). Figure 17-4 Slave Receiver Transfer Sequence Diagram 7-bit address Master...
Page 365 C starts transmitting addresses or address headers to I C bus. In 10-bit address mode, transmitting a header sequence will generate the following events: − I2C_STS1.ADDR10F bit is set by hardware, and if I2C_CTRL2.EVTINTEN bit is set, an interrupt is generated.
Page 366: Figure 17-5 Master Transmitter Transfer Sequence Diagram
Figure 17-5 Master Transmitter Transfer Sequence Diagram 7-bit address Master Master Master Master Slave Slave Master Slave Slave Master Start Address(W) Data1 Data2 DataN Stop EV8-1 EV8-2 10-bit address Master Master Slave Master Slave Master Slave Master Slave Master Start Header(W) Address Data1 DataN...
Page 367 mode. If the I2C_CTRL2.EVTINTEN bit is set to 1, an interrupt will be generated. Then the software reads the I2C_STS1 register and then writes a 7-bits address or a 10-bits address with an address header to the I2C_DAT register, in order to clear the I2C_STS1.STARTBF bit. After the I2C_STS1.STARTBF bit is cleared to 0, I begins to transmit the address or address header to the I C bus.
Page 368: Error Conditions Description
After the last byte is received, the I2C_STS1.RXDATNE bit is set to 1, and the software can read the last byte. Since I2C_CTRL1.ACKEN has been cleared to 0 in the previous step, I C no longer transmits ACK for the last byte, and generates a STOP bit after the last byte is sent.
Page 369: Dma Application
17.3.3.1 Acknowledge Failure(ACKFAIL) The interface have a acknowledge bit is detected that does not match the expectation, it will occurs acknowledge fail error, and the I2C_STS1.ACKFAIL bit is set. An interrupt occurs, when I2C_CTRL2.ERRINTEN bit is set to 1. When transmitter receives a NACK, the communication must be reset: if the device is in slave mode, hardware will release the bus;...
Page 370: Transmit Process
interface, and trigger an interrupt when interrupts are enabled. In the master transmit mode, in the EOT interrupt handler DMA request need to be disbale, and set stop condition after waiting for I2C_STS1.BSF event. In the master receive mode, the data of received is great than or equal to 2, DMA will send a hardware signal EOT_1 in DMA transmission(byte number-1).
Page 371: Packet Error Check(Pec)
When DMA tansfer data is done, DMA need to send EOT/EOT_1 signal to I C indicate this transfer is done, if interrupt is enbale, DMA ocurrs a interrupt. Note: if DMA is used for receiving, do not set I2C_CTRL2.BUFINTEN bit. 17.3.5 Packet Error Check(PEC) Setting the I2C_CTRL1.PECEN bit to 1 enables the PEC function.
Page 372: Device Identification
• The data format is similar. SMBus data format is similar to 7-bit address format of I C(refer toFigure 17-2). • Both are master-slave communication modes, and the master device provides the clock. • Both support multi master Differences between SMBus and I Table 17-1 Comparison Between Smbus And I Smbus Maximum transmission speed 100kHz...
Page 373: Timeout Error
17.3.6.6 Timeout error A kind of feature related to timeout on SMBus: if it has taken too long time during the communication, it automatically resets the device. This is the reason why SMBus has a minimum transmission rate limitation -- to prevent the bus from locking up for a long time after the timeout occurs.
Page 374: Interrupt Request
of DBG_CTRL. I2CxTIMOUT bit in the PWR module, the SMBUS timeout control can either continue normal operation or be halted. Refer to Section 3.3.2 for details. 17.5 Interrupt Request All I C interrupt requests are listed in the following table. Table 17-2 I C Interrupt Request Interrupt Function...
Page 375: I 2 C Control Register 1 (I2C_Ctrl1)
Offset Register I2C_CTRL2 CLKFREQ[5:0] 004h Reserved Reset Value I2C_OADDR1 ADDR[7:1] 008h Reserved Reserved Reset Value I2C_OADDR2 ADDR2[7:1] 00Ch Reserved Reset Value I2C_DAT DATA[7:0] 010h Reserved Reset Value I2C_STS1 014h Reserved Reset Value I2C_STS2 PECVAL[7:0] 018h Reserved Reset Value I2C_CLKCTRL CLKCTRL[11:0] 01Ch Reserved Reset Value...
Page 376 Bit Field Name Description Packet error checking It can be set or cleared by software. It will be cleared by hardware when PEC has been transferred, or by start or stop condition, or when I2C_CTRL1.EN=0. 0: No PEC transfer 1: PEC transfer. Note: when arbitration is lost, the calculation of PEC is invalid.
Page 377: I 2 C Control Register 2 (I2C_Ctrl2)
Bit Field Name Description This bit determines whether to pull SCL low when the data is not ready(I2C_STS1.ADDRF or I2C_STS1.BSF flag is set) in slave mode, and is cleared by software reset 0: Enable Clock stretching. 1: Disable Clock stretching. General call enable GCEN 0：Disable General call.
Page 378: I 2 C Own Address Register 1 (I2C_Oaddr1)
Bit Field Name Description DMAEN DMA requests enable 0: Disable DMA 1: Enable DMA BUFINTEN Buffer interrupt enable 0: When I2C_STS1.TXDATE=1 or I2C_STS1.RXDATNE=1, any interrupt is not generated. 1: If I2C_CTRL2.EVTINTEN= 1,When I2C_STS1.TXDATE=1 or I2C_STS1.RXDATNE= 1, interrupt will be generated. EVTINTEN Event interrupt enable 0：Disable event interrupt；...
Page 379: I 2 C Own Address Register 2 (I2C_Oaddr2)
Bit Field Name Description ADDRMODE Addressing mode (slave mode) 0: 7-bit slave address 1: 10-bit slave address Reserved Must always be kept as' 1' by the software. 13:10 Reserved Reserved, the reset value must be maintained. ADDR[9:8] Interface address 9~8 bits of the address. Note: don't care these bits in 7-bit address mode ADDR[7:1] Interface address...
Page 380: I 2 C Status Register 1 (I2C_Sts1)
Bit Field Name Description DATA[7:0] 8-bit data register Send or receive data buffer. Note: In the slave mode, the address will not be copied into the data register; If I2C_STS1.TXDATE =0, data can still be written into the data register; If the ARLOST event occurs when processing the ACK pulse, the received byte will not be copied into the data register, so it cannot be read.
Page 381 Bit Field Name Description 1: Overrun/Underrun Set by hardware in slave mode when I2C_CTRL1.NOEXTEND=1, and when receiving a new byte in receiving mode, if the data within DAT register has not been read yet, over-run occurs,the new received byte will be lost.When transferring a new byte in transfer mode, but there is not new data that has not been written in DAT register, under-run occurs which leads that the same byte will be send twice.
Page 382 Bit Field Name Description RXDATNE is not set when the ARLOST event occurs. Note: when BSF is set, the RXDATNE bit cannot be cleared when reading data, because the data register is still full. Reserved Reserved, the reset value must be maintained. STOPF Stop detection (slave mode) After the software reads the STS1 register, the operation of writing to the CTRL1 register will...
Page 383: I 2 C Status Register 2 (I2C_Sts2)
Bit Field Name Description Hardware sets this bit to' 1' (when the corresponding setting is enabled) when the received slave address matches the content in the OADDR register, or a general call or SMBus device default address or SMBus host or SMBus alter is recognized. Note: after receiving NACK, the I2C_STS1.ADDRF bit will not be set.
Page 384: I 2 C Clock Control Register (I2C_Clkctrl)
Bit Field Name Description Transmitter/receiver After detecting the stop condition (I2C_STS1.STOPF=1), repeated start condition or bus arbitration loss (I2C_STS1.ARLOST=1), or when I2C_CTRL1.EN=0, the hardware clears it. 0: Data receiving mode 1: Data transmission mode; At the end of the whole address transmission stage, this bit is set according to the R/W bit of the address byte.
Page 385: I 2 C Rise Time Register (I2C_Tmrise)
Bit Field Name Description ◼ If duty cycle = Tlow/Thigh = 1/1: CLKCTRL = f (Hz)/100000/2 PCLK1 Tlow = CLKCTRL × T PCLK1 Thigh = CLKCTRL × T PCLK1 ◼ If duty cycle = Tlow/Thigh = 2/1: CLKCTRL = f (Hz)/100000/3 PCLK1 Tlow = 2 ×...
Page 386: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
18 Universal Synchronous Asynchronous Receiver Transmitter (USART) 18.1 Introduction USART is a full-duplex universal synchronous/asynchronous serial transceiver module. This interface is a highly flexible serial communication device that can perform full-duplex data exchange with external devices. The USART has programmable transmit and receive baud rates and can communicate continuously using DMA. It also supports multiprocessor communication, LIN mode, synchronous mode, single-wire half-duplex communication, Smartcard asynchronous protocol, IrDA SIR ENDEC function and hardware flow control function.
Page 387: Functional Block Diagram
18.3 Functional Block Diagram Figure 18-1 USART Block Diagram CPU/DMA Transmit Data Receive Register(TDR) Data(RDR) IrDA ENDEC Transmit Shift Receive Shift BLOCK SW_RX Register Register Hardware nRTS flow TX control RX control controller nCTS Tx clock Rx clock Buadrate CTRL register PCLK generate BRCF...
Page 388: Usart Frame Format
oversampling technique is used when receiving dat. When the device is acting as a transmitter, it transmits data through the TX pin, and as a receiver, it receives data through the RX pin. When there is no data transmission, the bus is in an idle state. Frame format is: 1 start bit + 8 or 9 data bits (least significant bit first) + 1 parity bit (optional) + 0.5,1,1.5 or 2 stop bit.
Page 389: Transmitter
Figure 18-3 Word Length = 9 Setting 9-bit word length , 1 stop bit Clock Data frame bit8 can be the parity bit Data frame Start Stat Stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 Start Idle frame Start Stop Break frame...
Page 390: Figure 18-4 Configuration Stop Bit
Figure 18-4 Configuration Stop Bit 8-bit Word length (WL bit is reset) CLOCK bit7 can be the parity bit Data frame Start Stat bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Data frame 0.5 Stop bit 0.5Stop bit Data frame bit7 can be the parity bit Data frame Start...
Page 391: Single Byte Communication
Enable the transmitter (USART_CTRL1.TXEN); Transmit each data to be sent to the USART_DAT register through the CPU or DMA, and the write operation to the USART_DAT register will clear USART_STS.TXDE; After writing the last data word in the USART_DAT register, wait for USART_STS.TXC =1, which indicates the end of the transmission of the last data frame.
Page 392: Receiver
Figure 18-5 TXC/TXDE Changes During Transmission set by hardware set by hardware TXDE flag set by hardware cleared by software cleared by software USART enable Write data2 Write data2 Write data1 into USART_DAT into USART_DAT into USART_DAT USART_DAT data1 data2 data3 Because TXDE=1 TXC is set...
Page 393: Figure 18-6 Start Bit Detection
Figure 18-6 Start Bit Detection RX line sample 10 11 12 13 14 15 clock One-bit time Conditions x x x x to validate the start bit Falling edge At least 2 bits At least 2 bits detection out of 3 at 0 out of 3 at 0 18.4.3.2 Stop bit description...
Page 394: Framing Error
2 stop bits: the sampling of the 2 stop bits is completed at the 8th, 9th and 10th sampling points of the first stop position. If a frame error is detected during the first stop bit, the frame error flag is set. During the second stop bit period, receiver does not detect framing error.
Page 395: Generation Of Fractional Baud Rate
error flag USART_STS.FEF will be set by hardware, and the invalid data will be transferred from the shift register to the USART_DAT register. During single-byte communication, no framing error interrupt will be triggered because at this point, the USART_STS.RXDNE bit is set to 1, which will trigger the interrupt. In multi-buffer communication mode, an interrupt will be triggered if the USART_CTRL3.ERRIEN bit is set.
Page 396: Table 18-3 Error Calculation When Setting Baud Rate
fractional parts of the baud rate divider. The baud rate of the transmitter and receiver should be configured to the same value. Be careful not to change the value of the USART_BRCF register during communication, because the baud rate counter will be replaced by the new value of the baud rate register. TX / RX baud rate = ��...
Page 397: Receiver's Tolerance Clock Deviation
937.5 1250 234.375 312.5 19.2 19.2 117.1875 19.2 156.25 57.6 57.6 39.0625 57.623 52.0625 0.04% 115.2 115.384 19.5 0.15% 115.1 26.0625 0.08% 230.4 230.769 9.75 0.16% 230.769 0.16% 460.8 461.538 4.875 0.16% 461.538 0.16% 921.6 923.076 2.4375 0.16% 923.076 3.25 0.16% 2250 2250...
Page 398: Even Parity
3.03% 3.53% 18.4.6 Parity Control Parity can be enabled by configuring the USART_CTRL1.PCEN bit. When the parity bit is enabled for transmission, a parity bit is generated on transmition, and a parity bit is checked on reception. Table 18-6 Frame Format WL Bit PCEN Bit USART Frame...
Page 399: Figure 18-7 Transmission Using Dma
18.4.7.1 DMA transmission Set USART_CTRL3.DMATXEN to enable DMA mode when transmitting. When the USART's transmit shift register is empty (USART_STS.TXDE=1), the DMA will transfer the data from the SRAM to the USART_DAT register of the USART. When using DMA transmission, the process of configuring the DMA channel is as follows: 1.
Page 400: Hardware Flow Control
18.4.7.2 DMA reception Set USART_CTRL3.DMARXEN to enable DMA mode when receiving. When a byte is received (USART_STS.RXDNE=1), the DMA will transfer the data from the USART_DAT register of the USART to the SRAM. When using DMA reception, the process of configuring the DMA channel is as follows: 1.
Page 401: Figure 18-9 Hardware Flow Control Between Two Usart
the data will not be lost. The connection method is shown in the following figure. Figure 18-9 Hardware Flow Control Between Two USART DEVICE 1 DEVICE 2 TX control RX control RX control TX control 18.4.8.1 RTS flow control Set USART_CTRL3.RTSEN to enable RTS. RTS is the output signal used to indicate that the receiver is ready. When data arrives in RDR, pull high nRTS output, notifying the transmiter to stop data transmission at the end of the current frame.
Page 402: Multiprocessor Communication
If the nCTS signal becomes invalid during data transmission, the transmission will stop after sending the data. If you write data to the data register when nCTS is invalid, the data will not be sent until nCTS is valid. If the USART_CTRL3.CTSEN bit is set, the USART_STS.CTSF bit will be set high by hardware when the nCTS input changes state.
Page 403: Figure 18-12 Mute Mode Using Idle Line Detection
When USART_CTRL1.RCVWU is set (which can be automatically controlled by hardware or written by software under certain conditions), USART enters mute mode. In mute mode, the receive status flag is not set, and all receive interrupts are disabled; As shown in the Figure 18-12 below, when an idle frame is detected, USART is woken up, and then USART_CTRL1.RCVWU is cleared by hardware.
Page 404: Synchronous Mode
When the received address matches the address of the USART_CTRL2.ADDR[3:0] bits, the USART is woken up and USART_CTRL1.RCVWU is cleared. The USART_STS.RXDNE bit will be set when this matching address is received. Data can then be transmitted normally. Figure 18-13 Mute Mode Detected Using Address Mark RXDNE=1 RXDNE=1 RXDNE=1...
Page 405: Figure 18-14 Usart Synchronous Transmission Example
activated and data is written to the USART_DAT register. The USART_CTRL2.LBCLK bit controls whether to output the clock pulse corresponding to the last data byte (MSB) sent on the CK pin. This bit needs to be configured when both the transmitter and receiver are disabled. If USART_CTRL2.LBCLK is 1, the clock pulse of the last bit of data will be output from CK.
Page 406: Figure 18-15 Usart Data Clock Timing Example (Wl=0)
Figure 18-15 USART Data Clock Timing Example (WL=0) Clock（CLKPOL=0，CLKPHA=0） Clock（CLKPOL=0，CLKPHA=1） Clock（CLKPOL=1，CLKPHA=0） Clock（CLKPOL=1，CLKPHA=1） Data on TX (from master) MSB Stop Start LSB Data on RX (from slave) 406 / 526...
Page 407: Single-Wire Half-Duplex Mode
Figure 18-16 USART Data Clock Timing Example (WL=1) Clock（CLKPOL=0，CLKPHA=0） Clock（CLKPOL=0，CLKPHA=1） Clock（CLKPOL=1，CLKPHA=0） Clock（CLKPOL=1，CLKPHA=1） Data on TX (from master) MSB Stop Start LSB Data on RX (from slave) Figure 18-17 RX Data Sampling / Holding Time SCLK(capture strobe on SCLK rising edge in this example) Data on RX valid DATA bit (from slave)
Page 408: Serial Irda Infrared Encoding/Decoding Mode
Through the USART_CTRL3.HDMEN bit, you can choose whether to enable half-duplex mode. When using single- wire half-duplex, USART_CTRL2. CLKEN, USART_CTRL2. LINMEN, USART_CTRL3. SCMEN, USART_CTRL3. IRDAMEN, these bits should be kept clear. After the half-duplex mode is turned on, the TX pin and the RX pin are interconnected inside the chip, and the Rx pin is no longer used.
Page 409: Lin Mode
18.4.12.2 IrDA low power mode When USART_CTRL3.IRDALP=1, USART device enters IrDA low power mode. For the transmitter, when in low power mode, the pulse width is 3 times the low power baud rate, which is a minimum of 1.42MHz. Typically this value is 1.8432MHz (1.42 MHz < PSC < 2.12 MHz). For the receiver, the requirement for a valid signal is that the duration of the low level signal must be greater than 2 cycles of the IrDA low power baud rate clock.
Page 410: Lin Reception
bit. Note: when using LIN mode, USART_CTRL2.STPB[1:0], USART_CTRL2.CLKEN, USART_CTRL3.SCMEN, USART_CTRL3.HDMEN, USART_CTRL3. IRDAMEN, these bits should be kept clear. 18.4.13.1 LIN transmitting When data is sent in LIN mode, the length of the data bits sent can only be 8 bits. By setting USART_CTRL1.SDBRK, a 13-bit '0' will be sent as the break frame, and insert a stop bit.
Page 411: Figure 18-20 Break Detection In Lin Mode (11-Bit Break Length-The Linbdl Bit Is Set)
Figure 18-20 Break Detection In LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set) Case 1: break signal not long enough => break discarded, LINBDF is not set Break frame RX line Idle Idle Break frame Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6...
Page 412: Smartcard Mode (Iso7816)
Figure 18-21 Break Detection And Framing Error Detection In LIN Mode In these examples, we suppose that LINBDL=1(11-bit break length),WL=0(8-bit data) Break occurring after an Idle： RX line frame1 Idle frame2 frame3 1 frame time 1 frame time RXDNE/FEF LINBDF Break occurring while a data is being received：...
Page 413: Figure 18-22 Iso7816-3 Asynchronous Protocol
signal(when USART_CTRL3.SCNACK bit is set 1), while a framing error is generated at the transmitter end (with 1.5 stop bits).When the transmitter receives a NACK signal (framing error) from the receiver, it does not detect the NACK as a start bit (according to the ISO protocol, the duration of the received NACK can be 1 or 2 baud clock cycles).
Page 414: Interrupt Request
Figure 18-23 Use 1.5 Stop Bits To Detect Parity Errors 1.5 Stop Bit Parity Bit Bit 7 1 bit time 1.5 bit time sampling at sampling at 16th, 17th, 18th 8th, 9th, 10th 0.5 bit time 1 bit time sampling at sampling at 8th, 9th, 10th 8th, 9th, 10th...
Page 415: Mode Support
Note:(1)This flag bit is used only when DMA is used to receive data(USART_CTRL3.DMARXEN=1). 18.6 Mode Support Table 18-8 USART Mode Setting Communication Mode USART1 USART2 Asynchronous mode Hardware flow control mode DMA communication mode Multiprocessor Synchronous mode Smartcard mode Single-wire half duplex mode IrDA infrared mode Note:(1)Y = support this mode, N = do not support this mode 18.7 USART Register...
Page 416: Usart Status Register (Usart_Sts)
Offset Register STPB USART_CTRL2 ADDR[3:0] [1:0] 010h Reserved Reset Value USART_CTRL3 014h Reserved Reset Value USART_GTP GTV[7:0] PSCV[7:0] 018h Reserved Reset Value 18.7.2 USART Status Register (USART_STS) Address offset : 0x00 Reset value : 0x0000 00C0 Bit Field Name Description 31:10 Reserved Reserved,...
Page 417 Bit Field Name Description This bit is set to 1 after power-on reset. If USART_STS.TXDE is set, this bit is set when the current data transmission is completed. Setting USART_CTRL1.TXCIEN bit will generate an interrupt. This bit is cleared by software. 0: Transmitting did not complete.
Page 418: Usart Data Register (Usart_Dat)
Bit Field Name Description 0: No framing errors were detected. 1: A framing error or a Break Character is detected. Note: this bit will not generate an interrupt because it appears with USART_STS.RXDNE, and the hardware will generate an interrupt when setting the USART_STS.RXDNE flag.
Page 419: Usart Control Register 1 Register (Usart_Ctrl1)
Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:4 DIV_Integer [11:0] Integer part of baud rate divider. DIV_Decimal[3:0] Fractional part of baud rate divider. 18.7.5 USART Control Register 1 Register (USART_CTRL1) Address offset : 0x0C Reset value : 0x0000 0000 Bit Field Name...
Page 420: Usart Control Register 2 Register (Usart_Ctrl2)
Bit Field Name Description If this bit is set to 1, an interrupt is generated when USART_STS.PEF bit is set. 0: Parity error interrupt is disabled. 1: Parity error interrupt is enabled. TXDEIEN TXDE interrupt enable If this bit is set to 1, an interrupt is generated when USART_STS.TXDE bit is set. 0: Transmit buffer empty interrupt is disabled.
Page 421 Reset value : 0x0000 0000 Bit Field Name Description 31:15 Reserved Reserved, the reset value must be maintained LINMEN LIN mode enable 0:LIN mode is disabled 1:LIN mode enabled 13:12 STPB[1:0] STOP bits. 00:1 stop bit. 01:0.5 stop bit. 10:2 stop bit. 11:1.5 stop bit.
Page 422: Usart Control Register 3 Register (Usart_Ctrl3)
Bit Field Name Description Note: LINBDL can be used to control the detection length of Break Characters in LIN mode and other modes, and the detection length is the same as that in LIN mode. Reserved Reserved, the reset value must be maintained ADDR[3:0] USART address.
Page 423: Usart Guard Time And Prescaler Register (Usart_Gtp)
Bit Field Name Description SCMEN Smartcard mode enable. This bit is used to enable Smartcard mode. 0: Smartcard mode is disabled. 1: Smartcard mode is enabled. SCNACK Smartcard NACK enable. This bit is used for Smartcard mode to enable transmitting NACK when parity error occurs.
Page 424 Bit Field Name Description PSCV[7:0] Prescaler value. In IrDA low power consumption mode: these bits are used to set the prescaler coefficient for dividing the peripheral clock (PCLK1/PCLK2) to generate low power consumption frequency. 00000000: reserved-do not write this value. 00000001: divide the source clock by 1.
Page 425: Low Power Universal Asynchronous Receiver Transmitter (Lpuart)
19 Low Power Universal Asynchronous Receiver Transmitter (LPUART) 19.1 Introduction Low power universal asynchronous receiver transmitter (LPUART) is a low power, full duplex, asynchronous serial communication interface. The LPUART can be clocked by HSI, HSE, LSI, LSE, SYSCLK and PCLK1. When 32.768khz LSE is selected as the clock source, the LPUART can operate in STOP low-power mode with a maximum communications up to 9600bps.
Page 426: Functional Block Diagram
− One programmable 4-byte frame 19.3 Functional Block Diagram Figure 19-1 LPUART Block Diagram CPU/DMA Receive data register(RDR) Transmission data register(TDR) Receive buffer Transmission shift register Receive shift register CTRL register Hardware data flow control Wake up Tx control Rx control controller STS register Interrupt control...
Page 427: Lpuart Frame Format
CTS (Clear To Send): When transmitter detects that CTS is valid (low level), the next data is transmitted. RTS (Request To Send): When receiver is ready to receive new data, pull the RTS pin low. LPUART has the following characteristics: •...
Page 428 Each character is preceded by a low level starting bit; and followed by a 1-bit stop bit. Note: you cannot reset the LPUART_CTRL.TXEN bit during data transfer, otherwise the data on the TX pin will be corrupted because the baud rate counter stops counting. The current data being transferred will be lost. The steps for LPUART to transmit data as follows: Configure baud rate, parity check, DMA, flow control, etc.
Page 429: Receiver
Figure 19-3 TXC Changes During Transmission Software Software clears TXC and Write Data0 directly Software clears TXC and enable TXEN writes Data2 in in LPUART_DAT writes Data1 in LPUART_DAT without waiting LPUART_DAT LPUART_DAT Data0 Data1 Data2 TXC flag Set by hardware Set by hardware Set by hardware Send stop bit...
Page 430: Overrun Error
Read the data by reading the LPUART_DAT register. Return to Step 2 and continue receiving data. Note: please be sure to initialize the LPUART module before using the receiver. When receiving a data frame: • The LPUART_STS.FIFO_NE bit is set, and the contents of the shift Register are transferred to the RDR (Receiver Data Register).
Page 431: Fractional Baud Rate Generation
Figure 19-4 Data Sampling For Noise Detection Receiving signal line Sampling clock The length of a bit Table 19-1 Data Sampling For Noise Detection Sampling Values NF State Received Bit Value When noise is detected in a receiving frame, you can do the following: •...
Page 432: Parity Control
Note: after writing LPART_BRCFG1 and LPUART_BRCFG2, the baud rate counter is replaced with the new value of the baud rate register. Therefore, do not change the value of the baud rate register during communication. 19.4.4.1 Configure baud rates through LPUART_BRCFG1 and LPUART_BRRCFG2 For example, baud rate = 4800bps, clock frequency = 32768Hz.
Page 433: Dma Application
Table 19-2 Parity Frame Format PCDIS Bit LPUART Frame | Start bit | 8-bit data | parity | stop bit | | Start bit | 8 bits data | stop bit | Transfer mode: Parity is enabled by resetting the LPUART_CTRL.PCDIS bit. If parity fails, the LPUART_STS.PEF flag is set to '1', and an interrupt will be triggered if LPUART_INTEN.PEIE is set.
Page 434: Figure 19-5 Sending Using Dma
Figure 19-5 Sending Using DMA Data frame 0 Stop bit Data frame 1 Stop bit Stop bit Data frame 2 TX line Transfer is over, DMA Software enable controller ignores this request to send data DMA writes Data0 DMA writes Data1 DMA writes Data2 in LPUART_DAT in LPUART_DAT...
Page 435: Hardware Flow Control
Figure 19-6 Receiving With DMA Data frame 0 Stop bit Data frame 1 Stop bit Stop bit Data frame 2 RX line Cleared by DMA Set by hardware FIFO_NE detection operation DMA reads Data0 DMA reads Data2 DMA reads Data1 in LPUART_DAT in LPUART_DAT in LPUART_DAT...
Page 436: Low Power Wake Up
full, 3/4 full, or full. Below is an example of communication with RTS flow control enabled. Figure 19-8 RTS Flow Control Waiting to read data Read data register register,RTS high end,RTS low RTS line Start Start Stop Stop RX line Data 1 Idle Data 2...
Page 437: Interrupt Request
22 when a specific waking up event occurs. The LPUART waking up event can be generated in the following ways (through the LPUART_CTRL.WUSEL[1:0]) : • A waking up event is generated when a start bit is detected • A waking up event is generated when the receive buffer non-empty flag is set •...
Page 438: Lpuart Status Register (Lpuart_Sts)
Offset Register Reset Value LPUART_DAT DAT[7:0] 010h Reserved Reset Value LPUART_BRCFG2 DECIMAL[7:0] 014h Reserved Reset Value LPUART_WUDAT WUDAT[31:0] 018h Reset Value 19.6.2 LPUART Status Register (LPUART_STS) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:9 Reserved Reserved, the reset value must be maintained. Noise detected flag.
Page 439: Lpuart Interrupt Enable Register (Lpuart_Inten)
Bit Field Name Description TX complete flag. 0: TX is disabled or not complete. 1: TX transmission is complete. Parity check error flag. 0: No parity error detected. 1: Parity error detected 19.6.3 LPUART Interrupt Enable Register (LPUART_INTEN) Address offset: 0x04 Reset value: 0x0000 0000 Bit Field Name...
Page 440 Bit Field Name Description 31:15 Reserved Reserved, the reset value must be maintained. SMPCNT Specify sampling method 0: 3 sample bits, noise detection is allowed (LPUARTDIV should be large enough, such as greater than 10) 1: 1 sample bits, closed noise detection 13:12 WUSEL[1:0] Wake up event selection.
Page 441: Lpuart Baud Rate Configuration Register 1 (Lpuart_Brcfg1)
Bit Field Name Description 1: Enables TX PSEL Odd parity enable 0: Even parity 1: Odd parity 19.6.5 LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1) Address offset: 0x0C Reset value: 0x0000 0174 Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 INTEGER[15:0] Baud rate configuration register 1.
Page 442: Lpuart Wake Up Data Register (Lpuart_Wudat)
Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. DECIMAL[7:0] Baud rate configuration register 2 is used for baud rate error correction at low frequencies.For example, If the baud rate is 4800bps and the clock frequency is 32768Hz. LPUARTDIV = 32768/4800 = 6.8266 LPUART_BRCFG1 = 6.In this case, to correct the baud rate error, you should configure register 2 with baud rate.
Page 443: Serial Peripheral Interface/Inter-Ic Sound (Spi/ I S)
20 Serial Peripheral Interface/Inter-IC Sound (SPI/ I 20.1 SPI AND I S Introductions This module is about SPI/I S. It operates in SPI mode by default and users can choose to use I S by setting the value of registers. Serial peripheral interface (SPI) is able to operate in master or slave mode, supports full-duplex and half-duplex high- speed communication mode, and have hardware CRC calculation and configurable multi-master mode.
Page 444: Spi Function Description
20.3 SPI Function Description 20.3.1 General Description Figure 20-1 SPI Block Diagram address and data bus Read Receive buffer MOSI LSBFF SPI_CTRL2 control bit Shift register SSOEN TDMAEN RDMAEN MISO INTEN INTEN INTEN SPI_STS Send buffer BUSY OVER MODERR UNDER CHSIDE Write Communication circuit...
Page 445: Figure 20-2 Selective Management Of Hardware/Software
The NSS pin is not used in software NSS mode. In this mode the internal NSS signal level is driven by writing the SPI_CTRL1.SSEL bit (master mode SPI_CTRL1.SSEL = 1, slave mode SPI_CTRL1.SSEL = 0). 20.3.1.2 Hardware NSS mode The software slave device management is disabled when SPI_CTRL1.SSMEN = 0. NSS input mode: The NSS output of the master device is disabled (SPI_CTRL1.MSEL = 1, SPI_CTRL2.SSOEN = 0), allowing operation in multi-master mode.
Page 446: Figure 20-3 Master And Slave Applications
Figure 20-3 Master And Slave Applications Slave Master MSBit MSBit LSBit LSBit MISO 8-bit shift register 8-bit shift register MOSI SPI clock generator NSS(1) NSS(1) Not used if NSS is managed by software Note: NSS pin is set as input The master device outputs a synchronous clock signal through the SCK pin, the MOSI pin of the master device is connected to the MOSI pin of the slave device, and the MISO pin of the master device is connected to the MISO pin of the slave device, so that data can be transferred between devices.
Page 447: Data Format
Figure 20-4 Data Clock Timing Diagram CLKPHA=1 CLKPOL=1 CLKPOL=0 MISO （from master） SPI_CTRL1 determines whether the data frame format is 8 or 16 bits MISO （from slave）（to slave） Capture strobe CLKPHA=0 CLKPOL=1 CLKPOL=0 MISO （from master） SPI_CTRL1 determines whether the data frame format is 8 or 16 bits MISO （from slave）...
Page 448: Figure 20-5 Changes Of Te/Rne/Busy When The Host Is Continuously Transmitting In Full Duplex
order and then loaded into the SPI_DAT register in parallel. The software operation process is as follows: Set SPI_CTRL1.SPIEN = 1, enable SPI module. Write the first data to be sent into SPI_DAT register (this operation will clear SPI_STS.TE bit). Wait for SPI_STS.TE bit to be set to '1', and write the second data to be sent into SPI_DAT.
Page 449: Figure 20-6 Changes Of Te/Busy During The Host Transmits Continuously In One-Way Only Mode
to transmit subsequent data; After writing the last data to SPI_DAT, wait for SPI_STS.TE bit to set '1'; then wait for SPI_STS.BUSY bit to be cleared to complete the transmission of all data. The process of data transmitting can also be implemented in the interrupt handler generated by the rising edge of the TE flag.
Page 450 RONLY = 1) Configure：CLKPOL=1.CLKPHA=1,RONLY=1 DATA1=0xAA DATA2=0xBB DATA3=0xCC MISO/MOSI （in） Set by hardware Clear by software RNE flag Rx buffer 0xAA 0xBB 0xCC （read fromSPI_DAT） Wait until RNE=1,read 0xAA from SPI_DAT Wait until RNE=1,read 0XBB from SPI_DAT Wait until RNE=1,read 0xCC from SPI_DAT 20.3.2.4 Master one-wire bidirectional send mode Master one-wire bidirectional send mode (SPI_CTRL1.MSEL = 1, SPI_CTRL1.BIDIRMODE = 1, SPI_CTRL1.BIDIROEN = 1, SPI_CTRL1.RONLY = 0).
Page 451: Figure 20-8 Changes Of Te/Rne/Busy When The Slave Is Continuously Transmitting In Full Duplex
Figure 20-8 Changes Of TE/RNE/BUSY When The Slave Is Continuously Transmitting In Full Duplex Mode Slave mode：CLKPOL=1.CLKPHA=1 DATA1=0x11 DATA2=0x22 DATA3=0x33 MISO/MOSI (out) TE flag Set by hardware Clear by software Tx buffer 0x11 0x22 0x33 （write to SPI_DAT） The flag set/clear by hardware BUSY flag DATA1=0xAA DATA2=0xBB...
Page 452 20.3.2.9 Slave one-wire bidirectional transmit mode Slave one-wire bidirectional transmit mode (SPI_CTRL1.MSEL = 0, SPI_CTRL1.BIDIRMODE = 1 and SPI_CTRL1.BIDIROEN = 1). When the slave device receives the first edge of the clock signal, the transmitting process starts. No data is received in this mode, and the software must ensure that the data to be transmitted has been written in the SPI_DAT register before the SPI master device starts data transmission.
Page 453: Status Flag
In some configurations, when the last data is sent, the BUSY flag (SPI_STS.BUSY) can be used to wait for the end of the data transmitting. 20.3.2.13 Continuous and discontinuous transmission When transmitting data in master mode, if the software is fast enough to detect each TE (SPI_STS.TE) rising edge (or TE interrupt), and the data is written to the SPI_DAT register immediately before the end of the ongoing transmission.
Page 454: Turn Off Spi
ends, the hardware sets the BUSY flag to 0. Only when the device is in the master one-wire bidirectional receive mode, the BUSY flag (SPI_STS.BUSY) will be set to 0 when the communication is in progress. The BUSY flag (SPI_STS.BUSY) will be cleared to 0 in the following cases: •...
Page 455: Spi Communication Using Dma
20.3.5 SPI Communication Using DMA Users can choose DMA for SPI data transfer, the application program can be released, and the system efficiency can be greatly improved. When the transmit buffer DMA is enabled (SPI_CTRL2.TDMAEN = 1), each time the TE flag (SPI_STS.TE) bit is 1, a DMA request will be generated, and the DMA will automatically write the data to the SPI_DAT register, which will clear the TE flag (SPI_STS.TE) bit.
Page 456: Crc Calculation
Figure 20-12 Reception Using DMA CLKPOL=1.CLKPHA=1 DATA1=0xAA DATA2=0xBB DATA3=0xCC MISO/MOSI (in) Clear by DMA RNE flag Set by hardware read Rx buffer 0xAA 0xBB 0xCC （read from SPI_DAT） DMA request DMA read from SPI_DAT DMA flag Set by hardware Clear by software （DMA transfer complete）...
Page 457: Spi Interrupt
• NSS pin hardware management mode, the master device NSS pin is pulled low; • NSS pin software management mode, the SPI_CTRL1.SSEL bit is set to 0. When a master mode failure error occurs, the SPI_STS.MODERR bit is set to 1. An interrupt is generated if the user enables corresponding interrupt(SPI_CTRL2.ERRINTEN=1).
Page 458: I 2 S Function Description
20.4 I S Function Description The block diagram of I S is shown in the figure below: Figure 20-13 I S Block Diagram Address and data bus Tx buffer SPI_STS MODER BUSY OVER UNDER CHSIDE MOSI/SD 16-bit LSBFF control bit Shift register MISO 16-bit...
Page 459: Supported Audio Protocols
Note: F is the sampling frequency of audio signal In master mode, I S uses its own clock generator to generate clock signals for communication, and this clock generator is also the clock source of the master clock output (SPI_I2SPREDIV.MCLKOEN = 1, the master clock output is enabled).
Page 460: Figure 20-14 I 2 S Philips Protocol Waveform (16/32-Bit Full Precision, Clkpol = 0)
Figure 20-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0) Receive Send Left channel (data format 16-bit or 32-bit) Right channel Figure 20-15 I S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0) Recieve Send The remaining 8 bits are forced to 0 24-bit data...
Page 461: Figure 20-16 I
Figure 20-16 I S Philips Protocol Standard Waveform (16-Bit Extended To 32-Bit Packet Frame, CLKPOL = 0) Recieve Send The remaining 16 bits are forced to 0 16-bit data Right channel Left channel 32-bit data If 16-bit data needs to be packed into 32-bit data frame format, the CPU only needs to read or write the SPI_DAT register once for each frame of data transmission.
Page 462: Figure 20-17 The Msb Is Aligned With 16-Bit Or 32-Bit Full Precision, Clkpol = 0
Figure 20-17 The MSB Is Aligned With 16-Bit Or 32-Bit Full Precision, CLKPOL = 0. Send Receive Left channel (16-bit or 32-bit) Right Channel Figure 20-18 MSB Aligns 24-Bit Data, CLKPOL = 0 Send Receive 8-bit remaining 0 forced 24-bit data Right channel Left channel 32-bit Figure 20-19 MSB-Aligned 16-Bit Data Is Extended To 32-Bit Packet Frame, CLKPOL = 0...
Page 463: Figure 20-20 Lsb Alignment 16-Bit Or 32-Bit Full Precision, Clkpol = 0
20.4.1.3 LSB alignment standard In 16-bit or 32-bit full-precision frame format, LSB alignment standard is the same as MSB alignment standard. Figure 20-20 LSB Alignment 16-Bit Or 32-Bit Full Precision, CLKPOL = 0 Send Receive Left channel (16-bit or 32-bit) Right channel Figure 20-21 LSB Aligns 24-Bit Data, CLKPOL = 0 Send...
Page 464: Figure 20-22 Lsb Aligned 16-Bit Data Is Extended To 32-Bit Packet Frame, Clkpol = 0
Figure 20-22 LSB Aligned 16-Bit Data Is Extended To 32-Bit Packet Frame, CLKPOL = 0 Send Receive 16-bit data forced 0 16-bit data Right channel Left channel 32-bit If the 16-bit data needs to be packaged into a 32-bit data frame format, the CPU only needs to read or write the SPI_DAT register once for each frame of data transmission.
Page 465: Clock Generator
Figure 20-23 PCM Standard Waveform (16 Bits) WS short frame WS long frame 13-bit 16-bit Figure 20-24 PCM Standard Waveform (16-Bit Extended To 32-Bit Packet Frame) WS short frame WS long frame 13-bit 16-bit 20.4.2 Clock Generator In the master mode, the linear divider needs to be set correctly in order to obtain the desired audio frequency. 465 / 526...
Page 466: Figure 20-25 I 2 S Clock Generator Structure
Figure 20-25 I S Clock Generator Structure MCLK 8-bit Linear Divider Divider Divider + by 2 by 4 reshaping I2Sx CLK stage MCLKOEN ODD_ MCLK LDIV[7:0] BITS EVEN Note: the clock source of I Sx CLK is HSI, HSE or PLL system clock that drives AHB clock. The bit rate of I S determines the data flow on the I S data line and the frequency of the I...
Page 467: I 2 S Transmit And Receive Sequence
Table 20-2 Use The Standard 8mhz HSE Clock To Get Accurate Audio Frequency. SYSCLK S_LDIV S_ODD_EVEN Target Real F (Hz) Error MCLK (Hz) （Mhz） 16 Bits 32 Bits 16 Bits 32 Bits 16 Bits 32 Bits 16 Bits 32 Bits without 96000 93750...
Page 468 the data of the other channel should be written into SPI_DAT. The channel corresponding to the current data to be transmitted is confirmed by the flag bit CHSIDE (SPI_STS. CHSIDE). The value of CHSIDE (SPI_STS. CHSIDE) is updated when TE (SPI_STS.TE) is set to '1'. A complete data frame includes left and right channels, and only part of the data frame cannot be transmitted.
Page 469: Status Flag
• The data length is 16 bits, the channel length is 32 bits (SPI_I2SCFG.TDATLEN = 00 and SPI_I2SCFG.CHBITS = 1), the MSB alignment standard (SPI_I2SCFG.STDSEL = 01), I S Philips standard (SPI_I2SCFG.STDSEL = 00) or PCM standard (SPI_I2SCFG.STDSEL = 11) Wait for the last RNE flag (SPI_STS.RNE) bit to be set to' 1'.
Page 470: Error Flag
In transmit mode, the flag is updated when the TE flag (SPI_STS.TE) is set; in receive mode, the flag is updated when the RNE flag (SPI_STS.RNE) is set. In the process of transmitting and receiving, if an overflow (SPI_STS.OVER) or underflow (SPI_STS.UNDER) error occurs, this flag is meaningless, and the I S needs to be turned off and then turned on again.
Page 471: Spi Control Register 1 (Spi_Ctrl1)
Offset Register SPI_CTRL2 004h Reserved Reset Value SPI_STS 008h Reserved Reset Value SPI_DAT DAT[15:0] 00Ch Reserved Reset Value SPI_CRCPOLY CRCPOLY[15:0] 010h Reserved Reset Value SPI_CRCRDAT CRCRDAT[15:0] 014h Reserved Reset Value SPI_CRCTDAT CRCTDAT[15:0] 018h Reserved Reset Value MODCFG STDSEL TDATLEN SPI_I2SCFG [1:0] [1:0] [1:0]...
Page 472 Bit Field Name Description CRCEN Hardware CRC check enable 0: Disable CRC calculation. 1: Enable CRC calculation. Note: this bit can only be written when SPI is disabled (SPI_CTRL1.SPIEN = 0), otherwise an error will occur. This bit can only be used in full duplex mode. Note: not used in I S mode.
Page 473: Spi Control Register 2 (Spi_Ctrl2)
Bit Field Name Description 1: Enable the SPI device. Note: not used in I S mode. Note: when turning off the SPI device, please follow paragraph 0 section's procedure operation. BR[2:0] Baud rate control 000: fPCLK/2 001: fPCLK/4 010: fPCLK/8 011: fPCLK/16 100: fPCLK/32 101: fPCLK/64...
Page 474: Spi Status Register (Spi_Sts)
Bit Field Name Description RNEINTEN Receive buffer non-empty interrupt enable 0: Disable RNE interrupt. 1: Enable RNE interrupt, and trigger interrupt request when RNE flag (SPI_STS.RNE) is set to ‘1’. ERRINTEN Error interrupt enable When an error (SPI_STS.CRCERR, SPI_STS.OVER, SPI_STS.UNDER, SPI_STS.MODERR) is generated, this bit controls whether an interrupt is generated 0: Disable error interrupt.
Page 475: Spi Data Register (Spi_Dat)
Bit Field Name Description For more information about software sequences, refer to 20.3.7.2 for details. MODERR Mode error 0: No mode error. 1: A mode error occurred. Note:this bit is set by hardware and cleared according to the sequence of software operations. For more information about software sequences, refer to 20.3.7 for details.
Page 476: Spi Crc Polynomial Register (Spi_Crcpoly) (Not Used In I S Mode)
Bit Field Name Description 15:0 DAT[15:0] Data register Data to be sent or received The data register corresponds to two buffers: one for write (transmit buffer); The other is for read (receive buffer).Write operation writes data to transmit buffer; The read operation will return the data in the receive buffer.
Page 477: Spi_ I 2 S Configuration Register（Spi_I2Scfg
values. Note: not used in I s mode. 20.5.8 SPI TX CRC Register（SPI_CRCTDAT） Address offset: 0x18 Reset value: 0x0000 Bit Field Name Description 15:0 CRCTDAT Send CRC register When CRC calculation is enabled, CRCTDAT[15:0] contains the CRC value calculated by the bytes sent subsequently.
Page 478: Spi_I S Prescaler Register (Spi_I2Sprediv)
Bit Field Name Description MODCFG S mode setting 00: Slave device transmits. 01: Slave device receives. 10: Master device transmits. 11: Master device receives. Note: this bit can only be set when I S is turned off. Note: not used in SPI mode. PCMFSYNC PCM frame synchronization 0: Short frame synchronization.
Page 479 Reset value: 0x0002 Bit Field Name Description 15:10 Reserved Reserved,the reset value must be maintained MCLKOEN Master clock output enable 0: Disable master clock output. 1: Enable master clock output. Note: for correct operation, this bit can only be set when I S is turned off.
Page 480: Real-Time Clock (Rtc)
21 Real-Time Clock (RTC) 21.1 Description • The real-time clock (RTC) is an independent BCD timer/counter. • Daylight saving time compensation supported by software. • A periodic automatic programmable wakeup timer. • Two programmable alarms. • Two 32-bit registers contain the seconds, minutes, hours, days (day of week), days (day of month), months, and years.
Page 481: Main Function
Main Function Description 2 Tamper detection logic are a source of system Wakeup should a Tamper event Tamper happen on one of the input lines. It is also a source of hardware trigger to LP Timer. Time-stamp function for GPIO event saving. It is a source to Wakeup system from low power modes.
Page 482: Gpios Of Rtc
• Tamper event/interrupt • RTC output functions − 256 Hz or 1Hz clock output (LSE frequency is 32.768 kHz). − Alarm clock output (polarity configurable), Alarm A and Alarm B are optional. − Auto wakeup output (polarity configurable). • RTC input functions: −...
Page 483: Rtc Calendar
• A 15-bit synchronous prescaler which is configured by RTC_PRE.DIVS[14:0] bits The formula for f and f are given below: ck_apre ck_spre �� ck_apre ��_��.��[6:0]+1 �� ck_spre = ( ��_��.��[14:0]+1 ) ∗(��_��.��[6:0]+1) The ck_apre clock is used to driven RTC_SUBS sub-second down counter. When it reaches 0, reload RTC_SUBS with the value of RTC_PRE.DIVS[14:0].
Page 484: Calendar Reading
Note: before entering the RTC initialization mode, please ensure that the value of RTC_SUBS.SS[15:0] is not less than 2,and read RTC_DATE register once. 21.3.7 Calendar Reading 1. Reading calendar value when RTC_CTRL.BYPS=0 Calendar value is read from shadow registers if RTC_CTRL.BYPS=0. In order to read RTC calendar registers (RTC_SUBS, RTC_TSH and RTC_DATE) correctly, APB1 clock frequency must be set equal to or greater than 7 times of RTC clock frequency.
Page 485: Programmable Alarms
Note: when the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin (PC13) is automatically configured as output. 21.3.9 Programmable Alarms RTC has 2 programmable alarms: Alarm A and Alarm B. RTC alarm can be enabled or disable by RTC_CTRL.ALxEN bit. If all the alarm value match the calendar values, the RTC_INITSTS.ALxF flag will be set.
Page 486: Wakeup Timer Configuration
− When RTC_CTRL.WKUPSEL [2:0] = 11x, the period is range from 18h to 36h. After RTC_CTRL.WTEN bit is set to 1, the down counter is running and when it reaches 0, RTC_INITSTS.WTF will be set and the device can exit from low power mode when the periodic wakeup interrupt is enabled by setting the RTC_CTRL.WTIEN bit.
Page 487: Daylight Saving Time Function Configuration
detection before enable RTC_TMPCFG.TPxEN bit. When the tamper event is detected after tamper detection is enable, if RTC_TMPCFG.TPxINTEN is set to 1, tamper event can trigger an interrupt and RTC_INITSTS.TAMxF bit will be set 1. When RTC_INITSTS.TAMxF is set to 1, a new tamper event on the same pin cannot be detected. Timestamp on tamper event Any tamper event can cause a timestamp event when RTC_INITSTS.TPTS is set to 1, and RTC_INITSTS.TISF bit and RTC_INITSTS.TISOVF bit will be set as a normal timestamp event.
Page 488: Rtc Digital Clock Precision Calibration
21.3.18 RTC Digital Clock Precision Calibration Digital precision calibration is achieved by adjusting the number of RTC clock pulses in the calibration period. Digital precision calibration resolution is 0.954 PPM with the range from -487.1 PPM to +488.5 PPM. When the input frequency is 32768 Hz, calibration period can be configured as 2 RTCCLK cycles or 32/16/8 seconds.
Page 489: Rtc Low Power Mode
is within 0.954ppm (0.5 RTCCLK cycles within 16 seconds). • The calibration period is 8 seconds. Using an accurate 8-second period to measure the 1Hz calibration output can ensure that the measurement error is within 1.907ppm (0.5 RTCCLK cycles within 8 seconds). Dynamic recalibration When RTC_INITSTS.INITF=0, RTC_CALIB register can update by using following steps: •...
Page 490: Rtc Calendar Time Register (Rtc_Tsh)
Offset Register RTC_ALARMB DTT[1:0] DTU[3:0] HOT[1:0] HOU[3:0] MIT[2:0] MIU[3:0] SET[2:0] SEU[3:0] 020h Reset Value RTC_WRP PKEY[7:0] 024h Reserved Reset Value RTC_SUBS SS[15:0] 028h Reserved Reset Value RTC_SCTRL SUBF[14:0] 02Ch Reserved Reset Value RTC_TST HOT[1:0] HOU[3:0] MIT[2:0] MIU[3:0] SET[2:0] SEU[3:0] 030h Reserved Reset Value RTC_TSD...
Page 491: Rtc Calendar Date Register (Rtc_Date)
Bit Field Name Description Reserved Reserved, the reset value must be maintained. 14:12 MIT [2: 0] Describes the minute tens value in BCD format 11:8 MIU[3:0] Describes the minute units value in BCD format Reserved Reserved, the reset value must be maintained. SCT[2:0] Describes the second tens value in BCD format SCU[3:0]...
Page 492 Bit Field Name Description 31:24 Reserved Reserved, the reset value must be maintained. COEN Calibration output enable This bit controls RTC_CALIB output 0: Disable calibration output 1: Enable calibration output 22:21 OUTSEL[1:0] Output selection These bits are used to select the alarm/wakeup output 00: Disable output 01: Enable Alarm A output 10: Enable Alarm B output...
Page 493 Bit Field Name Description 0: Disable Alarm A interrupt 1: Enable Alarm A interrupt TSEN Timestamp enable 0: Disable timestamp 1: Enable timestamp WTEN Wakeup timer enable 0: Disable wakeup timer 1: Enable wakeup timer ALBEN Alarm B enable 0: Disable Alarm B 1: Enable Alarm B ALAEN Alarm A enable...
Page 494: Rtc Initial Status Register (Rtc_Initsts)
21.4.5 RTC Initial Status Register (RTC_INITSTS) Address offset: 0x0C Reset value: 0x0000 0007 Bit Field Name Description 31:17 Reserved Reserved, the reset value must be maintained. RECPF Recalibration pending flag The RECPF status flag is automatically set to ‘1’ when software writes to the RTC_CALIB register, indicating that the RTC_CALIB register is blocked.
Page 495 Bit Field Name Description ALAF Alarm A flag This flag is set to ‘1’ by hardware when the time/date registers value match the Alarm A register values. This flag can be cleared by software writing 0 INITM Enter initialization mode 0: Free running mode 1: Enter initialization mode and set calendar time value, date value, and prescale value.
Page 496: Rtc Prescaler Register (Rtc_Pre)
Bit Field Name Description 0: Alarm A update is not allowed 1: Alarm A update is allowed 21.4.6 RTC Prescaler Register (RTC_PRE) Address offset: 0x10 Reset value: 0x007F 00FF Bit Field Name Description 31:23 Reserved Reserved, the reset value must be maintained. 22:16 DIVA[6:0] Asynchronous prescaler factor...
Page 497: Rtc Alarm A Register (Rtc_Alarma)
21.4.8 RTC Alarm A Register (RTC_ALARMA) Address offset: 0x1C Reset value: 0x0000 0000 Bit Field Name Description MASK4 Alarm date mask 0: Date/day match 1: Date/day not match WKDSEL Week day selection 0: DTU[3:0] represents the date units 1: DTU[3:0] represents week day only. DTT[1:0] is not considered 29:28 DTT[1:0] Describes the date tens value in BCD format...
Page 498: Rtc Write Protection Register (Rtc_Wrp)
Bit Field Name Description MASK4 Alarm date mask 0: Date/day match 1: Date/day not match WKDSEL Week day selection 0: DTU[3:0] represents the date units 1: DTU[3:0] represents week day only. DTT[1:0] is not considered 29:28 DTT[1:0] Describes the date tens value in BCD format 27:24 DTU[3:0] Describes the date units value in BCD format...
Page 499: Rtc Sub-Second Register (Rtc_Subs)
Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. PKEY[7:0] Write protection key Reading this byte always returns 0x00. For detail on how to unlock RTC register write protection, see chapter RTC register write protection. 21.4.11 RTC Sub-Second Register (RTC_SUBS) Address offset: 0x28 Reset value: 0x0000 0000 Bit Field...
Page 500: Rtc Timestamp Time Register (Rtc_Tst)
Bit Field Name Description 14:0 SUBF[14:0] Subtract a fraction of a second There bits can only be written and read as zero.. Writing to this bit does not have an impact when RTC_INITSTS.SHOPF=1. The value which is written to SUBF is added to the synchronous prescaler counter, and the clock will delay: Delay (seconds) = (SUBF[14:0] + 1) / (DIVS[14:0] + 1) AD1S bit can be used together with the SUBF[14:0]bits:...
Page 501: Rtc Timestamp Sub-Second Register (Rtc_Tsss)
Bit Field Name Description 31:24 Reserved Reserved, the reset value must be maintained. 23:20 YRT[3:0] Describes the year tens value in BCD format 19:16 YRU[3:0] Describes the year units value in BCD format 15:13 WDU[2:0] Describes which Week day 000: Forbidden 001: Monday 111: Sunday Describes the month tens value in BCD format...
Page 502: Rtc Tamper Configuration Register（Rtc_Tmpcfg
Bit Field Name Description 31:16 Reserved Reserved, the reset value must be maintained. Increase frequency of RTC by 488.5 ppm This feature is intended to be used along with CM[8:0]. When RTCCLK frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is ((512 * CP) –...
Page 503 Bit Field Name Description Reserved Reserved, the reset value must be maintained. TP2INTEN Tamper 2 interrupt enable 0: Disable tamper 2 interrupt when TPINTEN = 0. 1: Enabled tamper 2 interrupt TP1MF Tamper 1 mask flag 0: Not mask tamper 1 event. 1: Mask tamper 1 event.
Page 504: Rtc Alarm A Sub-Second Register (Rtc_Alrmass)
Bit Field Name Description if TPFLT[1:0] != 00, tamper detection is in level mode: 0: low level trigger a tamper detection event. 1: high level trigger a tamper detection event. if TPFLT = 00, tamper detection is in edge mode: 0: Rising edge trigger a tamper detection event.
Page 505: Rtc Alarm B Sub-Second Register (Rtc_Alrmbss)
Bit Field Name Description 0x3: Only SSV[2:0] are compared and other bits are not compared. 0xC: Only SSV[11:0] are compared and other bits are not compared. 0xD: Only SSV[12:0] are compared and other bits are not compared. 0xE: Only SSV[13:0] are compared and other bits are not compared. 0xF: SSV[14:0] are compared Synchronization counter RTC_SUBS.SS[15] bit is never compared.
Page 506: Operational Amplifier (Opamp)
22 Operational Amplifier (OPAMP) The OPAMP module can be flexibly configured and can be used as programmable gain amplifier (PGA) and follower mode applications. The input range of OPAMP is 0V to VDDA and the output range is 0.1V to VDDA-0.1V. The output of the OPAMP is internally connected to the input channel of the ADC for analog signal measurement.
Page 507: Opamp Operating Mode
ADC channel 6 OPAMP PB14 22.2 OPAMP Operating Mode 22.2.1 OPAMP Standalone Operational Amplifier Mode In external amplification mode, the amplification factor is determined by the connected resistance and capacitance. When OPAMAP_CS.MOD = 2'b00 or 2'b01, OPAMAP operates in the external gain mode, OPAMAP_CS.VPSSEL or OPAMAP_CS.VPSEL selects non-inverted input, and OPAMAP_CS.VMSSEL or OPAMAP_CS.VMSEL selects inverted input.
Page 508: Opamp Follower Mode
Figure 22-2 Opamp Standalone Operational Amplifier Mode 22.2.2 OPAMP Follower Mode In follower mode, the output voltage is directly following the input voltage. The VMSEL terminal must be configured to connected to the OPAMP output port. When OPAMP_CS.MOD = 2'b11, the OPAMP is in internal follower function. In this mode, OPAMAP_CS.VPSSEL or OPAMAP_CS.VPSEL selects non-inverted input, OPAMAP_CS.VMSSEL or OPAMAP_CS.VMSEL is connected to the output port from inside the chip.
Page 509: Opamp Internal Programmable Gain (Pga) Mode
Figure 22-3 OPAMP Follower Mode 22.2.3 OPAMP Internal Programmable Gain (PGA) Mode Internal amplification mode, namely PGA mode, amplifies the input voltage through the embedded resistance feedback network When OPAMP_CS.MOD = 2 'b10, the OPAMP is in PGA mode, it supports 2/4/8/16/32 magnification factors, OPAMP_CS.VMSSEL or OPAMP_CS.VMSEL pins must be set to float.
Page 510: Opamp Independent Write Protection
Figure 22-4 Internal Programmable Gain Mode 22.2.4 OPAMP Independent Write Protection The write protection of OPAMP can be set independently by configuring the OPAMP_LOCK register. When the write protection is set, the software will not be able to write to the corresponding OPAMP register, and the write protection function can be canceled only after the chip is reset.
Page 511: Opamp Control Status Register (Opamp_Cs)
OPA_LOCK 010h Reserved Reset Value 22.3.2 Opamp Control Status Register (OPAMP_CS) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:20 Reserve Reserved，the reset value must be maintained 19:17 VPSSEL[2:0] OPAMP Non inverted input secondary selection. Same definition as VPSEL Reserve Reserved，the reset value must be maintained 15:14...
Page 512: Opamp Lock Register (Opamp_Lock)
Bit Field Name Description PGAGAN[2:0] OPAMP Programmable amplifier gain value 000: Internal PGA gain 2 001: Internal PGA gain 4 010: Internal PGA gain 8 011: Internal PGA gain 16 100: Internal PGA gain 32 Others: internal PGA gain 2 MOD[1:0] OPAMP PGA mode 0x: External zoom mode...
Page 513: Beeper
23 Beeper 23.1 Introduction The Beeper module supports complementary outputs and can generate periodic signals to drive external passive Beepers. It is used to generate a prompt tone or an alarm sound. 23.2 Function Description The Beeper, as an independent module, is connected to the APB1 bus, with a maximum operating frequency of 48MHz.
Page 514 Bit Field Name Description 1: LPRUN mode. 12:7 FREQ_SEL[5:0] MCU APB frequency selection signal. The corresponding frequency signal is selected according to the APB frequency, so that the output frequency will not be distorted. The value ranges from 1 to 48M, and 0 is also mapped to 48M. 000000:48M 000001: 1M 000010: 2M...
Page 515: Arithmetic Units (Hdiv And Sqrt)
24 Arithmetic Units (HDIV and SQRT) 24.1 Introductions of HDIV and SQRT The divider (HDIV) and square root calculator (SQRT) are mainly used in some scenarios with high requirements for computing energy efficiency, and are used to partially supplement the calculational shortcomings of the microcontroller.
Page 516: Hdiv Control Status Register (Hdiv_Ctrlsts)
24.3.2 HDIV Control Status Register (HDIV_CTRLSTS) Offset address: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:6 Reserved Reserved,the reset value must be maintained HDIVIEN Divider interrupt enable 0: Disable interrupt 1: Enable interrupt HDIVIF The divider interrupt flag bit, which generates an interrupt signal when the interrupt enable is turned on 0: No interrupt is generated 1: The division calculation is completed and an interrupt is generated...
Page 517: Hdiv Divisor Register (Hdiv_Divisor)
Bit Field Name Description 31:0 DIVIDEND 32-bit unsigned integer as dividend 24.3.4 HDIV Divisor Register (HDIV_DIVISOR) Offset address: 0x08 Reset value: 0x0000 0000 Bit Field Name Description 31:0 DIVISOR 32-bit unsigned integer as divisor 24.3.5 HDIV Quotient Register (HDIV_QUOTIENT) Offset address: 0x0C Reset value: 0x0000 0000 Bit Field Name...
Page 518: Sqrt Registers
Reset value: 0x0000 0000 Bit Field Name Description 31:1 Reserved Reserved,the reset value must be maintained DIVBY0 Divisor is 0 flag 0: Divisor is not 0 1: Divisor is 0 24.4 SQRT Registers 24.4.1 SQRT Register Overview Table 24-2 SQRT Register Overview Offset Register SQRT_CTRLSTS...
Page 519: Sqrt Radicand Register (Sqrt_Radicand)
Bit Field Name Description SQRTIF The square root calculator interrupt flag bit, which generates an interrupt signal when the interrupt enable is turned on 0：No interrupt is generated 1：The square root calculation is completed and an interrupt is generated Software writes '1' to clear the status bit SQRTDF The square root calculator computes the complete flag bit.
Page 520 Bit Field Name Description 31:16 Reserved Reserved,the reset value must be maintained 15:0 ROOT 16-bit square root output 520 / 526...
Page 521: Debug Support (Dbg)
25 Debug Support (DBG) 25.1 Overview ® The N32G030 uses Cortex -M0 core, which integrates hardware debugging module. It support instruction breakpoint (stop when fetcheing instructions) and data breakpoint (stops when accessing data). When the core is stopped, the user can view the internal state of the core and the external state of the system. After the user's query operation is completed, the core and peripherals can be restored, and the corresponding program can continue to be executed.
Page 522: Swd Function
Reference: • Cortex ® -M0 Technical Reference Manual (TRM) • ARM debug interface V5 structure specification • ARM CoreSight development tool set (r1p0 version) technical reference manual 25.2 SWD Function The debugging tool can call the debugging function through the above-mentioned SWD debugging interface. 25.2.1 Pin Assignment SWD (serial debug) interface consists of two pins: SWCLK (clock pin) and SWDIO (data input and output pin).
Page 523: Unique Device Serial Number (Uid)
Flash memory, and it can also be used to activate Secure Bootloader with security function. UCID is 128 bits and complies with the definition of the NSING Technologies chip serial number. It contains information about chip production and version.
Page 524 Reserved 4bit Keep it all 1. 524 / 526...
Page 525: Version History
27 Version History Version Date Changes V2.0 2022.7.10 Initial version V2.1 2022.9.13 Section 7.4.11, modify DMA channel sel 36 to 35 Section 9.4.20 and section 10.4.18, modify DMA burst valid address range of TIM, for register after TIMx_DCTRL, DMA burst is invalid Section 3.1.1.1, 3.4.6, 3.3.3, delete 1.0v output in stop mode Section 19.2, Modify LPUART max rate to 1Mbps Section 21.4.12, When AD1S is set to 1, SUBF[14:0] cannot be all 0...
Page 526: Disclaimer
This document is the exclusive property of NSING TECHNOLOGIES PTE. LTD.(Hereinafter referred to as NSING). This document, and the product of NSING described herein (Hereinafter referred to as the Product) are owned by NSING under the laws and treaties of Republic of Singapore and other applicable jurisdictions worldwide. The intellectual properties of the product belong to Nations Technologies Inc.

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