NSING N32G45 Series User Manual

32-bit arm cortex-m4 microcontroller

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N32G45x series

32-bit ARM

Cortex

-M4 microcontroller

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Page 1 N32G45x series ® ® 32-bit ARM Cortex -M4 microcontroller User manual 1 / 816...
Page 2: Table Of Contents
Contents ABBREVIATIONS ................................ 35 ..........................35 IST OF ABBREVIATIONS FOR REGISTERS ..............................35 VAILABLE PERIPHERALS INTERRUPTS AND EVENTS ............................36 ........................36 ESTED VECTORED INTERRUPT CONTROLLER 2.1.1 SysTick calibration value register ........................36 2.1.2 Interrupt and exception vectors ......................... 36 (EXTI) .......................
Page 3 4.2.3 STOP2 mode ............................... 84 4.2.4 STANDBY mode ..............................84 4.2.5 VBAT mode................................. 85 （AWU） ........................85 POWER AUTO WAKEUP MODE ................................86 REGISTERS 4.4.1 PWR register overview ............................86 4.4.2 Power control register (PWR_CTRL)........................86 4.4.3 Power control status register(PWR_CTRLSTS) ....................88 4.4.4 Power control register 2 (PWR_CTRL2) ......................
Page 4 6.3.7 AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN) ................117 6.3.8 APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN) ................119 6.3.9 APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN) ................121 6.3.10 Backup Domain Control Register (RCC_BDCTRL) ................... 124 6.3.11 Clock Control/Status Register (RCC_CTRLSTS) ....................125 6.3.12 AHB Peripheral Reset Register (RCC_AHBPRST) .....................
Page 5 ................................180 LOCK DIAGRAM ..............................180 UNCTION DESCRIPTION 8.4.1 DMA operation ..............................180 8.4.2 Channel priority and arbitration ........................181 8.4.3 DMA channels and number of transfers ......................181 8.4.4 Programmable data bit width ......................... 181 8.4.5 Peripheral/Memory address incrementation ....................183 8.4.6 Channel configuration procedure ........................
Page 6 ADC M ................................212 9.9.1 Independent mode ............................213 9.9.2 Synchronous regular mode ..........................213 9.9.3 Synchronous injection mode ..........................214 9.9.4 Fast alternate mode............................215 9.9.5 Slow alternate mode ............................216 9.9.6 Rotation trigger Mode ............................. 217 9.9.7 Mixed synchronous regular mode + synchronous injection mode ..............218 9.9.8 Mixed synchronous regular mode + rotation trigger mode ................
Page 7 10.3.8 Noise ................................244 10.3.9 Triangular wave generation .......................... 245 ..........................246 DUAL CHANNEL CONVERSION 10.4.1 Independent trigger without waveform generator ..................246 10.4.2 Independent triggers producing the same noise ................... 246 10.4.3 Independent triggers that generate different noises ..................247 10.4.4 Independent triggers that generate the same triangle wave ................
Page 8 11.3.12 Clearing the OCxREF signal on an external event ..................... 284 11.3.13 Complementary outputs with dead-time insertion ..................285 11.3.14 Break function ............................... 287 11.3.15 Debug mode ..............................288 11.3.16 TIMx and external trigger synchronization ...................... 289 11.3.17 Timer synchronization ............................ 292 11.3.18 6-step PWM generation ..........................
Page 9 12.3.7 Forced output mode ............................343 12.3.8 Output compare mode ............................. 343 12.3.9 PWM mode ..............................345 12.3.10 One-pulse mode ............................. 348 12.3.11 Clearing the OCxREF signal on an external event ..................... 349 12.3.12 Debug mode ..............................350 12.3.13 TIMx and external trigger synchronization ...................... 350 12.3.14 Timer synchronization ............................
Page 10 13.4.6 Event Generation registers (TIMx_EVTGEN) ....................387 13.4.7 Counter (TIMx_CNT) ............................388 13.4.8 Prescaler (TIMx_PSC) ............................. 388 13.4.9 Automatic reload register (TIMx_AR) ......................388 REAL-TIME CLOCK (RTC) ............................390 ................................390 ESCRIPTION 14.1.1 Specification ..............................390 ............................391 FUNCTION DESCRIPTION 14.2.1 RTC block diagram ............................
Page 11 14.3.18 RTC Alarm B sub-second register (RTC_ ALRMBSS) ..................412 14.3.19 RTC Option Register (RTC_ OPT) ........................413 CRC CALCULATION UNIT ............................414 ................................414 NTRODUCTION ................................. 414 AIN FEATURES 15.2.1 CRC32................................414 15.2.2 CRC16................................414 .............................. 415 UNCTION DESCRIPTION 15.3.1 CRC32................................
Page 12 WWDG ..............................430 REGISTERS 17.7.1 WWDG register overview ..........................430 17.7.2 WWDG control register (WWDG_CTRL) ......................430 17.7.3 WWDG config register (WWDG_CFG) ......................430 17.7.4 WWDG status register (WWDG_STS) ......................431 SDIO INTERFACE（SDIO） ............................ 432 SDIO ............................432 AIN FEATURES OF SDIO ..............................
Page 13 18.7.13 SDIO interrupt clear register (SDIO_INTCLR)....................480 18.7.14 SDIO interrupt enable register (SDIO_INTEN) ....................481 18.7.15 SDIO FIFO counter register (SDIO_FIFOCOUNT) ................... 484 18.7.16 SDIO data FIFO register (SDIO_DATFIFO) ..................... 484 UNIVERSAL SERIAL BUS FULL-SPEED DEVICE INTERFACE (USB_FS_DEVICE) ............486 ................................
Page 14 20.4.4 Receiving management ..........................520 20.4.5 Identifier filtering ............................521 20.4.6 Message storage ............................524 20.4.7 Bit time characteristic ............................ 525 ................................ 528 INTERRUPT 20.5.1 Error management ............................529 20.5.2 Bus-Off recovery ............................529 CAN C ............................529 ONFIGURATION CAN R ..............................
Page 15 （） 21.5.8 SPI TX CRC register SPI_CRCTDAT ......................588 （） 21.5.9 SPI_ I S configuration register SPI_I2SCFG ..................... 588 21.5.10 SPI_I S prescaler register (SPI_I2SPREDIV) ....................590 C INTERFACE ............................... 591 ................................591 NTRODUCTION ................................. 591 AIN FEATURES ..............................
Page 16 23.4.13 LIN mode ..............................641 23.4.14 Smartcard mode (ISO7816) ......................... 643 ..............................645 NTERRUPT REQUEST ................................ 646 ODE SUPPORT USART ..............................646 REGISTERS 23.7.1 USART register overview ..........................646 23.7.2 USART Status register (USART_STS) ....................... 647 23.7.3 USART Data register (USART_DAT) ........................ 649 23.7.4 USART Baud rate register (USART_BRCF) ......................
Page 17 24.6.22 QSPI DMA Transmit Data Level Register (QSPI_DMATDL_CTRL) ..............677 24.6.23 QSPI DMA Receive Data Level Register (QSPI_DMARDL_CTRL) ..............677 （） 24.6.24 QSPI Data Register QSPI_DATx ......................677 24.6.25 QSPI RX Sample Delay Register (QSPI_RS_DELAY) ..................678 （） 24.6.26 QSPI Enhanced SPI Mode Control 0 Register QSPI_ENH_CTRL0 ............
Page 18 25.5.15 ETH MAC address 0 low register (ETH_MACADDR0LO) ................740 25.5.16 ETH MAC address 1 high register (ETH_MACADDR1HI) ................740 25.5.17 ETH MAC address 1 low register (ETH_MACADDR1LO) ................741 25.5.18 ETH MAC address 2 high register (ETH_MACADDR2HI) ................741 25.5.19 ETH MAC address 2 low register (ETH_MACADDR2LO) ................
Page 19 COMP ..........................773 CONFIGURATION PROCESS COMP ............................. 774 WORKING MODE 26.4.1 Window mode ............................... 774 26.4.2 Independent comparator ..........................774 ..........................774 OMPARATOR INTERCONNECTION ................................775 NTERRUPT COMP ............................... 776 REGISTER 26.7.1 COMP register overview ..........................776 26.7.2 COMP control register (COMPx_CTRL) ......................778 26.7.3 COMP window mode register (COMP_WINMODE) ..................
Page 20 28.3.6 Soft reset................................ 798 28.3.7 Interrupts ............................... 799 28.3.8 Read FIFO data .............................. 799 28.3.9 Notes ................................799 ................................800 REGISTER 28.4.1 DVP register overview ............................ 800 （） 28.4.2 DVP Control Register DVP_CTRL ......................800 （） 28.4.3 DVP Status Register DVP_STS .........................
Page 21 List of Table Table 2-1 Vector table ............................36 Table 2-2 EXTI register review ......................... 43 Table 3-1 List of boot mode ..........................51 Table 3-2 Flash bus address list ......................... 52 Table 3-3 Option byte list ..........................56 Table 3-4 Read protection configuration list ..................... 57 Table 3-5 Flash read-write-erase permission control table ................
Page 22 Table 7-17 TIM8 alternate function remapping ....................145 Table 7-18 CAN1 alternate function remapping ....................145 Table 7-19 CAN2 alternate function remapping ....................145 Table 7-20 DVP alternate function remapping ....................146 Table 7-21 USART1 alternate function remapping ..................146 Table 7-22 USART2 alternate function remapping ..................
Page 23 Table 7-49 ETH ............................... 154 Table 7-50 USB ............................... 154 Table 7-51 Other .............................. 155 Table 7-52 GPIO registers overview........................ 157 Table 7-53 AFIO register overview ......................... 163 Table 8-1 Programmable data width and endian operation (when PINC = MINC = 1) ........181 Table 8-2 Flow control table ..........................
Page 24 Table 13-1 Register overview .......................... 384 Table 14-1 RTC feature support ........................390 Table 14-2 RTC register overview ........................398 Table 15-1 CRC register overview ........................416 Table 16-1 IWDG counting maximum and minimum reset time ..............423 Table 16-2 IWDG register overview........................ 424 Table 17-1 Maximum and minimum counting time of WWDG ..............
Page 25 Table 18-25 R1 response..........................468 Table 18-26 R2 response..........................468 Table 18-27 R3 response..........................468 Table 18-28 R4 response..........................469 Table 18-29 R4b response..........................469 Table 18-30 R5 response..........................469 Table 18-31 R6 response..........................470 Table 18-32 SDIO register overview ....................... 471 Table 18-33 Response Type and SDIO_RESPONSEx Register ..............
Page 26 Table 23-5 when DIV_Decimal != 0. Tolerance of USART receiver .............. 630 Table 23-6 Frame format ..........................630 Table 23-7 USART interrupt request ....................... 645 Table 23-8 USART mode setting ......................... 646 Table 23-9 USART register overview ......................646 Table 24-1 QSPI register overview ........................663 Table 25-1 ETH module pin configuration (alternate) ..................
Page 27 List of Figure Figure 2-1 External interrupt/event controller block diagram ................40 Figure 2-2 External interrupt GPIO mapping ....................42 Figure 3-1 Bus architecture ..........................47 Figure 3-2 Bus address map ..........................49 Figure 4-1 Power supply block diagram ......................76 Figure 4-2 Waveforms of power-on reset and power-down reset ..............
Page 28 Figure 9-13 Rotation triggering: injecting channel groups ................217 Figure 9-14 Rotation trigger: inject channel group in discontinuous mode ............. 218 Figure 9-15 Combination of rotation mode and synchronous regular mode ........... 219 Figure 9-16 Injection trigger occurs during injection transition ..............219 Figure 9-17 Alternate single-channel conversions are interrupted by injection sequences CH3 and CH4 ..
Page 29 Figure 11-18 Output part of channelx (x= 1,2,3, take channel 1 as example) ..........276 Figure 11-19 Output part of channelx (x= 4) ....................276 Figure 11-20 PWM input mode timing ......................278 Figure 11-21 Output compare mode, toggle on OC1 ..................280 Figure 11-22 Center-aligned PWM waveform (AR=8) ...................
Page 30 Figure 12-15 Output part of channelx （x = 1,2,3,4;take channel 4 as an example） ........341 Figure 12-16 PWM input mode timing ......................343 Figure 12-17 Output compare mode, toggle on OC1 ..................345 Figure 12-18 Center-aligned PWM waveform (AR=8) ................... 346 Figure 12-19 Edge-aligned PWM waveform (APR=8) ...................
Page 31 Figure 18-9 SDIO adapter command unit ......................438 Figure 18-10 Command Path State Machine (CPSM) ..................438 Figure 18-11 SDIO command transmission..................... 440 Figure 18-12 Data Channel ..........................441 Figure 18-13 Data Path State Machine (DPSM)....................442 Figure 19-1 USB device block diagram ......................486 Figure 19-2 The user applications on the microcontrollers and the USB modules access Packet Buffer Memory .................................
Page 32 Figure 21-7 Schematic diagram of RNE change when continuous transmission occurs in receive-only mode (BIDIRMODE = 0 and RONLY = 1) ....................... 560 Figure 21-8 Schematic diagram of the change of TE/RNE/BUSY when the slave is continuously transmitting in full duplex mode ............................562 Figure 21-9 Schematic diagram of TE/BUSY change during continuous transmission in slave unidirectional transmit-only mode ..........................
Page 33 Figure 23-4 configuration stop bit ........................624 Figure 23-5 TXC/TXDE changes during transmission ..................625 Figure 23-6 Start bit detection ......................... 626 Figure 23-7 Transmission using DMA ......................632 Figure 23-8 Reception using DMA ......................... 633 Figure 23-9 hardware flow control between two USART ................633 Figure 23-10 RTS flow control ........................
Page 34 Figure 26-2 Comparator3 and comparator4 connection diagram ..............771 Figure 26-3 Comparator5,Comparator6,comparator7 connection diagram ............. 772 Figure 27-1 Block diagram of OPAMP1 and OPAMP2 connection diagram ..........785 Figure 27-2 Block diagram of OPAMP3 and OPAMP4 connection diagram ..........786 Figure 27-3 Simulation module linkage relationship 1 ..................
Page 35: Abbreviations
Abbreviations List of abbreviations for registers The following abbreviations are used in register descriptions: read/write(rw) Software can read and write these bits. read-only(r) Software can only read these bits. write-only(w) Software can only write this bit, and reading this bit will return the reset value. read/clear(rc_w1) Software can read this bit or clear it by writing' 1', and writing' 0' has no effect on this bit.
Page 36: Interrupts And Events
Interrupts and events Nested vectored interrupt controller Features • 86 maskable interrupt channels (excluding 16 interrupt lines of Cortex-M4). • 16 programmable priority levels (4-bit interrupt priority level is used); • Low-latency exception and interrupt handling; • Power management control; •...
Page 37 Type of Position Priority Acronym Description Address priority Settable WWDG Window timer interrupt 0x0000_0040 Power supply voltage detection (PVD) Settable 0x0000_0044 interrupt connected to EXTI line 16 Settable TAMPER Intrusion detection interrupt 0x0000_0048 The real-time clock (RTC) wake-up Settable RTC_WKUP 0x0000_004C interrupt connected to EXTI line 20 Settable...
Page 38: Table 7-47 Sdio
Type of Position Priority Acronym Description Address priority Settable USART1 USART1 global interrupt 0x0000_00D4 Settable USART2 USART2 global interrupt 0x0000_00D8 Settable USART3 USART3 global interrupt 0x0000_00DC Settable EXTI15_10 EXTI line [15:10] interrupt 0x0000_00E0 RTC alarm interrupt connected to EXTI line Settable RTCAlarm 0x0000_00E4...
Page 39: External Interrupt/Event Controller (Exti)
Type of Position Priority Acronym Description Address priority Settable UART7 UART7 global interrupt 0x0000_016C Settable DMA1 channel 8 DMA1 channel 8 global interrupt 0x0000_0170 Settable DMA2 channel 8 DMA2 channel 8 global interrupt 0x0000_0174 Settable DVP global interrupt 0x0000_0178 Settable SAC global interrupt 0x0000_017C Settable...
Page 40: Functional Description
Figure 2-1 External interrupt/event controller block diagram AMBA APB BUS peripheral interface PCLK2 Software Interrupt Falling edge Rising edge Request to interrupt triggers triggers the masking suspend configuration configuration event register register register register register Connect the NVIC interrupt controller Pulse Input Edge detection circuit...
Page 41: Exti Line Mapping
− Configure the mask bits of 21 interrupt lines (EXTI_IMASK); − Configure the trigger configuration bits (EXTI_RT_CFG and EXTI_FT_CFG) of the selected disconnection; − Configure the enable and mask bits that control the NVIC interrupt channel mapped to the External Interrupt Controller so that an interrupt coming from one of the 21 lines can be correctly acknowledged.
Page 42: Figure 2-2 External Interrupt Gpio Mapping
Figure 2-2 External interrupt GPIO mapping EXTI1_CFG[3:0] Control EXTI2_CFG[3:0] Control EXTI3_CFG[3:0] Control EXTI0_CFG[3:0] Control AFIO_EXTI_CFG1 EXTI0 EXTI1 EXTI3 EXTI2 Register EXTI5_CFG[3:0] Control EXTI6_CFG[3:0] Control EXTI7_CFG[3:0] Control EXTI4_CFG[3:0] Control AFIO_EXTI_CFG2 EXTI7 EXTI4 EXTI5 EXTI6 Register EXTI8_CFG[3:0] Control EXTI9_CFG[3:0] Control EXTI10_CFG[3:0] Control EXTI11_CFG[3:0] Control PA10 PA11...
Page 43: Exti Registers
EXTI registers EXTI base address: 0x40010400 2.3.1 EXTI register review Table 2-2 EXTI register review Offset Register EXTI_IMASK IMASK[20:0] 000h Reserved Reset Value EXTI_EMASK EMASK[20:0] 004h Reserved Reset Value EXTI_RT_CFG RT_CFG[20:0] 008h Reserved Reset Value EXTI_FT_CFG FT_CFG[20:0] 00Ch Reserved Reset Value EXTI_SWIE SWIE[20:0] 010h...
Page 44: Rising Trigger Selection Register (Exti_Rt_Cfg)
Reset value: 0x0000 0000 Bit field Name Description 31:21 Reserved Reserved, the reset value must be maintained. 20:0 EMASKx Event mask on line x 0: Event request from line x is masked; 1: Event request from line x is not masked 2.3.4 Rising trigger selection register (EXTI_RT_CFG) Address offset: 0x08 Reset value: 0x0000 0000...
Page 45: Exti Software Interrupt Event Register (Exti_Swie)
Bit field Name Description 1: Falling trigger enabled (interrupts and events) for input line x. 2.3.6 EXTI software interrupt event register (EXTI_SWIE) Address offset: 0x10 Reset value: 0x0000 0000 Bit field Name Description 31:21 Reserved Reserved, the reset value must be maintained. 20:0 SWIEx Software interrupt on line x...
Page 46: Exti Timestamp Trigger Source Selection Register (Exti_Ts_Sel)
2.3.8 EXTI timestamp trigger source selection register (EXTI_TS_SEL) Address offset: 0x18 Reset value: 0x0000 0000 Bit field Name Description 31:4 Reserved Reserved, the reset value must be maintained. TSSEL[3:0] Select external interrupt input as trigger source of timestamp event. 0: Select EXTI0 as the trigger source of timestamp event; 1: Select EXTI1 as the trigger source of timestamp event;...
Page 47: Memory And Bus Architecture
Memory and bus architecture System architecture 3.1.1 Bus architecture Figure 3-1 Bus architecture TPIU Flash SW/JTAG ICode iCache DCode Cortex-M4FP Core SBus Fmax:144MHz SRAM NVIC R-SRAM DMA1 DMA2 QSPI SDIO ADC1/2/3/4 AFIO AFIO TIM2 EXTI EXTI TIM3 GPIOA GPIOA TIM4 AFIO GPIOB GPIOB...
Page 48: Bus Address Mapping
• The DCode bus connects the DCode bus of Cortex™-M4FP core with the data interface of flash memory (constant loading and debugging access). • SBus bus connects the SBus bus (peripheral bus) of Cortex™-M4FP core to the bus matrix, which coordinates the access between the core and DMA.
Page 49: Bit Banding
Figure 3-2 Bus address map Reserved 0x4002_A000 – 0x5FFF_FFFF 0x4002_8000 – 0x4002_9FFF Reserved 0x4002_5000 – 0x4002_7FFF 0x4002_4C00 – 0x4002_4FFF Reserved 0x4002_4800 – 0x4002_4BFF SAC SRAM 512B*2 0x4002_4400 – 0x4002_47FF 0x4002_4000 – 0x4002_43FF Reserved 0x4002_3400 – 0x4002_3FFF 0x4002_3000 – 0x4002_33FF Reserved 0x4002_2400 –...
Page 50: Boot Management
bitband_byte _addr = bitband _base + (byte_offset×32) + (bit_number×4) In which: bitband_byte_addr is the address of the byte in the alias memory area, which is mapped to a certain target bit; bitband_base is the starting address of alias area; byte_offset is the serial number of the byte containing the target bit in the bit-band; bit_number is the position of the target bit (0-7).
Page 51: Memory System
Boot configuration In addition, SRAM can also be accessed through virtual address segment 0x1000_0000, which makes the CPU jump to SRAM to run programs through ICode/DCode after starting from Main Flash or System Memory (note that programs are not started from SRAM and do not belong to startup mode). In addition to the BOOT pin configuration boot program, there are two ways to run the program in SRAM: •...
Page 52: Table 3-2 Flash Bus Address List
configuration area (2KB) and option byte area (2KB). − The System Memory area is 16KB, which contains 8 Page, also known as System Memory, and is used to store and run the BOOT program. − The system configuration area is 2KB, including 1 Page. −...
Page 53 programming/erasing controller. There are two ways to protect flash memory from illegal access (read, write and erase): • Page write protection (WRP) • Read protection (RDP) When the flash memory write operation is executed, any read operation to the flash memory will lock the bus, and the read operation can only be carried out correctly after the write operation is completed.
Page 54 • Select the page to be erased with the FLASH_ADD register; • Set the FLASH_CTRL.START bit to' 1'; • Wait for the FLASH_ STS.BUSY bit to change to' 0'; • Read out the erased page and verify it. Mass Erase Mass Erase process: •...
Page 55: Option Byte
• Set the FLASH_CTRL.OPTER bit to '1'; • Set the FLASH_CTRL.START bit to '1'; • Wait for the FLASH_ STS.BUSY bit to change to '0'; • Read the erased option byte and verify it. Option byte area programming process: • Check the FLASH_ STS.BUSY bit to confirm that there are no other flash operations in progress;...
Page 56: Table 3-3 Option Byte List
byte error flag (FLASH_OB.OBERR) will be generated. When an option byte error occurs, the corresponding option byte is forced to 0xFF. When the option byte and its complement are both 0xFF (the state after erasing), the above verification steps are skipped and verification is not required. Table 3-3 Option byte list [31:24] [23:16]...
Page 57: Write Protect
/ 47; − WRP3: write protection on pages 48-255, bit [0] corresponds to Page48 /49., bit [6] corresponds to Page60 / 61，bit [7] corresponds to Page62 / 255; • Read protection L2 level option byte: RDP2 − Add protection function on the basis of L1, see 3.2.1.9 detailed description of read protection; −...
Page 58: Table 3-5 Flash Read-Write-Erase
− The corresponding ~ (((RDP1 == 0xA5 & nRDP1 == 0x5A) && (RDP2!= 0xCC | nRDP2!= 0x33)) | (RDP2 == 0xCC & nRDP2 == 0x33)); − Only the read operation of the main storage area from the user code is allowed, that is, when the program is started from the main flash memory in non debugging mode, the read operation of the main storage area is allowed;...
Page 59 Access area Before 4KB of flash Read-Write- Read-Write- Read-Write- Read-Write-Erase main memory area Erase Erase Erase After 4KB of flash Read-Write- Read-Write- Read-Write- Read-Write-Erase main memory area Erase Erase Erase Flash main memory Allow Allow Allow Allow area mass erase Change to L1 or L2 is level allowed...
Page 60 Flash option byte area Read-only Read-only Read-only Flash system memory Prohibit Read-write-erase Prohibit area Read and Read and SRAM (All) Read and write write write Boot mode SRAM protect Changing a Protection Perform user level Level JTAG/SWD Main Flash System Memory SRAM Access to areas Before 4KB of flash...
Page 61 Flash system memory Prohibit Prohibit Prohibit Prohibit area Read and Read and Read and SRAM (All) Read and write write write write Before 4KB of flash main memory area After 4KB of flash main memory area Flash main memory No modification is area mass erase allowed.
Page 62: Icache
area Read and Read and Read and SRAM (All) Read and write write write write Before 4KB of flash Prohibit Read-only Read-only Read-only main memory area After 4KB of flash Read-write- Read-write- Prohibit Read-write-erase main memory area erase erase Flash main memory L0 or L2 is allowed.
Page 63: Software Interface
instruction buffer, the CPU can obtain the instruction without delay and realize zero waiting for execution. When the current instruction sequence, instruction prefetch sequence and instruction buffer all miss, Flash will be re-read and the Cache will be backfilled and updated. Accordingly, it is equivalent to storing only the jump header of the program in the Cache.
Page 64: Sram
to 1 to clear the data in the instruction cache. Note: FLASH_AC.ICAHRST bit is a write-only bit, and it returns to 0 when read. 3.2.2.3.3 iCache locking The software controls the FLASH_CAHR register to lock some repeatedly used codes in iCache to improve the efficiency of code execution.
Page 65: Flash Register
a total capacity of 16KB. The bus address of R-SRAM and SRAM are connected continuously. In application, SRAM and R-SRAM can be treated as a piece of SRAM. In the maximum case, the physical address of R-SRAM No.0 corresponds to the bus start address of 0x2002 0000, and the corresponding bus address range is 0x2002 0000~0x2002 3FFF.
Page 66 Offset Register FLASH_CTRL 010h Reset Value FLASH_ADD FADD 014h Reset Value 018h Reserved FLASH_OB 01Ch Reset Value FLASH_WRP WRPT 020h Reset Value FLASH_ECC 024h Reset Value 028h Reserved FLASH_RDN FLASH_RDN1 FLASH_RDN0 02Ch Reserved Reserved Reset Value FLASH_CAH LOCKSTOP LOCKSTRT 030h Reserved Reset Value FLASH control and status register...
Page 67 Bit field Name Description This bit indicates the status of the prefetch buffer 0: The prefetch buffer is closed; 1: The prefetch buffer is open. PRFTBFE Prefetch buffer enable 0: Close the prefetch buffer; 1: Enable prefetch buffer. Reserved Reserved, the reset value must be maintained. LATENCY time delay These bits represent the ratio of SYSCLK (system clock) period to flash memory...
Page 68 Bit field Name Description 31:0 OPTKEY Used to unlock the FLASH_CTRL.OPTWE bit. 3.2.5.2.4 The FLASH status register (FLASH_STS) Address offset: 0x0C Reset value: 0x0000 0000 Bit field Name Description 31:8 Reserved Reserved, the reset value must be maintained. ECCERR ECC error Read FLASH error, hardware set this bit to '1', write '1' to clear this state.
Page 69 Bit field Name Description 31:14 Reserved Reserved, the reset value must be maintained. ECERRITE ECC error interrupt This bit allows an interrupt to be generated when the FLASH_STS.ECCERR bit goes to '1'. 0: Interrupt generation is prohibited; 1: Enable interrupt generation. EOPITE Allow operation completion interrupt.
Page 70 Bit field Name Description You can only write '1'. When this bit is '1', Flash and FLASH_CTRL are locked. After detecting the correct unlocking sequence, hardware clears this bit to '0'. After an unsuccessful unlocking operation, this bit cannot be changed until the next system reset.
Page 71 Reset value: 0x03FF FFFC RDPRT2 Reserved Data1 Data0 nRST_ nRST_ Data0 Not_Used WDG_SW RDPRT1 OBERR STDBY STOP Bit field Name Description RDPRT2 Read protection L2 level protection 0: Read protection L2 level is not enabled; 1: Read protection L2 level is enabled. Note: This bit is read-only.
Page 72 Bit field Name Description 31:0 WRPT Write protect This register contains the write protection option byte loaded by option byte area. 0: write protection takes effect; 1: Write protection is invalid. Note: These bits are read-only. 3.2.5.2.9 ECC register（FLASH_ECC） Address offset: 0x24 Reset value: 0x0000 0000 Bit field Name...
Page 73 Bit field Name Description 15:9 Reserved Reserved, the reset value must be maintained. FLASH_RDN0 The address of Flash redundant block page 0 3.2.5.2.11 CAHR register (FLASH_CAHR) Address offset: 0x30 Reset value: 0x0000 0000 Bit field Name Description 31:8 Reserved Reserved, the reset value must be maintained. LOCKSTOP[3:0] iCache lock stop (see for detailed operation instructions 3.2.2.3.3 iCache locking Chapter).
Page 74: Power Control (Pwr)
Power control (PWR) General description PWR is power management unit to control status of different modules in different power modes. Its major function is to control MCU to enter different power modes and wakeup when events or interrupts happen. MCU supports RUN、SLEEP、STOP0、STOP2、STANDBY and VBAT mode.
Page 75 been powered down at this time. • When reset, SW1 will switch the power supply system to the VDD power supply area. In STOP2, STANDBY and VBAT modes, the internal voltage regulator BKR will power the digital backup area. − During the VDD rising phase or when PDR is detected, the switch between VBAT and VDD remains connected to the VBAT area.
Page 76: Power Supply Supervisor
Figure 4-1 Power supply block diagram VDDA domain (VSSA)VREF- Analog Peripherals (1.8V~VDDA)VREF+ HSE,RC8M PLL (VDD)VDDA POR PDR PVD (VSS)VSSA VDD domain Flash GPIOs SRAM Digital Peripherals VBAT domain BK Register RCC_BDCTRL register VBAT GPIO (PC13,PC14,PC15) R-SRAM IWDG 4.1.2 Power supply supervisor Power on reset (POR) and power down reset (PDR) Power-on reset (POR) and power down reset (PDR) circuits are integrated inside the chip.
Page 77: Figure 4-2 Waveforms Of Power-On Reset And Power-Down Reset
Figure 4-2 Waveforms of power-on reset and power-down reset VDD/VDDA POR(rising edge) 40mV hysteresis PDR(falling edge) Temporization RSTTEMPO RESET Programmable voltage detector (PVD) The PVD can be used to monitor the VDD/VDDA power supply by comparing with the thresholds set by the PWR_CTRL.PRS[2:0] bits of the power supply control register.
Page 78: Brown_Out Reset（Bor
Figure 4-3 PVD threshold waveform VDD/VDDA 100mV PVD threshold hysteresis PVD output Brown_out reset（BOR） BOR is a power-down reset controller built into the device, when the VDD voltage is lower than 1.62V (typ), the device will remain in reset state. Power modes Overall MCU has 6 power modes: RUN,SLEEP,STOP0,STOP2,STANDBY and VBAT.
Page 79 Mode Condition Enter Exit voltage regulators are still running. 1，PWR_CTRL.PDS＝0， external interrupt/event line HSE/HSI/PLL is turned off. 2）PWR_CTRL.LPS=0/1， (NVIC enabled), it can be external LSE/LSI, RTC or other peripherals can be Select the main voltage interrupt or internal peripheral configured to wake up. regulator operating mode 2) If entered by WFE, All SRAM data retention, all IO ports,...
Page 80: Table 4-2 Blocks Running State (1)
1. STOP0 mode, after wake-up, the code can continue running from the stop position. 2. In STOP2 mode, after waking up, the heap and global variables in the R-SRAM area can resume and continue from the stopped position, and the peripherals need to be re-initialized at this time. The running enable conditions of different modules in different power consumption modes are shown in the following table: Table 4-2 Blocks running state...
Page 81 Stop 0 Stop 2 Standby Peripheral Sleep VBAT Wakeup Wakeup Wakeup capability capability capability RTC / Auto wakeup Number of RTC Tamper pins USART1/2/3 UART4/5/6/7 I2C1/2/3/4 SPI1/2/3 CAN1/2 ETH MAC QSPI SDMMC OPAMP COMP Tempsensor TIMx IWDG 81 / 816...
Page 82: Sleep Mode
Stop 0 Stop 2 Standby Peripheral Sleep VBAT Wakeup Wakeup Wakeup capability capability capability WWDG SysTick GPIOs 2pins Note: Y means Yes (enable), O means Option (optional), - means invalid, OFF means close, 2pins represent 2 wakeup IOs, PA0_WKUP and NRST MR can select to work in normal mode or in low power mode FLASH is in sleep (Flash itself) mode.
Page 83: Stop0 Mode
event occurs. Wake-up events can be generated in the following ways: • Enable an interrupt in the peripheral control register instead of NVIC, and enable the SCB_SCR.SEVONPEND. When MCU wakes up by WFE, the peripheral interrupt suspend bit and the peripheral NVIC interrupt channel suspend bit (in NVIC interrupt clear suspend register) must be cleared.
Page 84: Stop2 Mode
mode. Exit STOP0 mode When an interrupt or wake-up event is generated to exit STOP0 mode, the HSI RC oscillator is selected as the system clock. When the voltage regulator is operating in low power mode, there is an additional startup delay when waking up from STOP0 mode.
Page 85: Vbat Mode
If an operation is in progress on FLASH, the time to enter STANDBY mode will be delayed until the memory access is complete. If an access to the APB area is in progress, the time to enter STANDBY mode will be delayed until the APB access is complete.
Page 86: Pwr Registers
external interrupts. The RTC provides a programmable clock reference for timed wake-up from STOP0, STOP2 and STANDBY modes. To do this, two of the three optional RTC clock sources can be selected by software programming RCC_BDCTRL.RTCSEL[1:0] as follows: • 32.768kHz external crystal clock (LSE OSC) This clock source provides an accurate clock reference with very low power consumption.
Page 87 Bit field Name Description 31:10 Reserved Reserved, the reset value must be maintained. 4-bit PVD threshold setting bits. This bit is operational when PWR_CTRL3.EXMODE = 1. Therefore, the PWR_CTRL3.EXMODE bit needs to be configured first. When the MSB bit is 0, the threshold is as follows: register(4bits) Voltage 0000...
Page 88: Power Control Status Register(Pwr_Ctrlsts)
Bit field Name Description descriptions. PVDEN Power supply voltage monitor (PVD) enabled. 0: Disable PVD 1: Enable PVD CSBVBAT Clear STANDBY/VBAT bit. always reads as 0 0: invalid 1: Clear PWR_CTRLSTS.SBF and PWR_CTRLSTS.VBATF standby bits (write) CWKUP Clear wakeup bit. always reads as 0 0: invalid 1: Clear PWR_CTRLSTS.WKUPF wake-up bit after 2 system clock cycles (write)
Page 89: Power Control Register 2 (Pwr_Ctrl2)
Bit field Name Description VBATF VBAT flag bit. This bit is set by hardware and is only cleared by POR or PDR (power-on reset/power- down reset) or set by setting the PWR_CTRL.CSBVBAT bit. 0: The device is not in VBAT mode 1: The device is already in VBAT mode PVDO PVD output.
Page 90: Power Control Register 3 (Pwr_Ctrl3)
Bit field Name Description LSITRIM[4:0] LSI correction value TMPWPEN TAMPER wake-up enable. 0: Disable 1: Enable SR2STBRET R-SRAM holds the enable bit in standby mode. 0: In standby mode, R-SRAM remains disable 1: In standby mode, R-SRAM remains enable SR2VBRET R-SRAM holds the enable bit in VBAT mode.
Page 91: Backup Registers (Bkp)
Backup registers (BKP) Introduction The backup memory is located in the backup domain, and is maintained by VBAT after the power supply VDD is turned off. BKP has a total of 42 16-bit registers that can be used to store and protect user application data. These 84 bytes are not affected by wake-up from system standby mode or system reset.
Page 92: Bkp Registers
BKP registers 5.4.1 BKP register overview The BKP register is a 16-bit addressable register. Table 5-1 BKP Register overview Offset Register 000h Reserved BKP_DAT1 DAT[15:0] 004h Reserved Reset Value BKP_DAT2 DAT[15:0] 008h Reserved Reset Value BKP_DAT3 DAT[15:0] 00Ch Reserved Reset Value BKP_DAT4 DAT[15:0] 010h...
Page 93 Offset Register Reset Value BKP_DAT13 DAT[15:0] 048h Reserved Reset Value BKP_DAT14 DAT[15:0] 04Ch Reserved Reset Value BKP_DAT15 DAT[15:0] 050h Reserved Reset Value BKP_DAT16 DAT[15:0] 054h Reserved Reset Value BKP_DAT17 DAT[15:0] 058h Reserved Reset Value BKP_DAT18 DAT[15:0] 05Ch Reserved Reset Value BKP_DAT19 DAT[15:0] 060h...
Page 94: Backup Data Register X (Bkp_Datx) (X = 1
Offset Register Reset Value BKP_DAT36 DAT[15:0] 0A4h Reserved Reset Value BKP_DAT37 DAT[15:0] 0A8h Reserved Reset Value BKP_DAT38 DAT[15:0] 0ACh Reserved Reset Value BKP_DAT39 DAT[15:0] 0B0h Reserved Reset Value BKP_DAT40 DAT[15:0] 0B4h Reserved Reset Value BKP_DAT41 DAT[15:0] 0B8h Reserved Reset Value BKP_DAT42 DAT[15:0] 0BCh...
Page 95: Backup Control/Status Register (Bkp_Ctrlsts)
Bit field Name Description TP_EN Start tamper detection TAMPER pin 0: Tamper detection TAMPER pin is used as a general IO port 1: Enbale the tamper detection pin for tamper detection Note: It is always safe to set the BKP_CTRL.TP_ALEV and BKP_CTRL.TP_EN bits at the same time. However, clearing both at the same time produces a false tamper event.
Page 96 Bit field Name Description 1: Clear the tamper detection interrupt and TINTF tamper detection interrupt flags CLRTE Clear tamper detection events This bit can only be written, and the read value is 0. 0: invalid 1: Clear the TEF tamper detection event flag (and reset the tamper detector). 96 / 816...
Page 97: Reset And Clock Control (Rcc)
Reset and clock control (RCC) Reset Control Unit Supports the following three types of reset: • Power Reset • System Reset • Backup domain Reset 6.1.1 Power reset A Power reset occurs in the following circumstances: • Power-on reset (POR reset). •...
Page 98: Software Reset
status register. Software reset A software reset can be generated by setting the SYSRESETREQ bit in Cortex™-M4 Application Interrupt and Reset Control Register. Refer to Cortex™-M4 technical reference manual for further information. Low-power management reset Low-power management reset can be generated by using the following methods: •...
Page 99: Clock Control Unit
• Under the premise that both VDD and VBAT are powered off, the backup area will be reset only when VDD or VBAT is powered on. Clock control unit Three different clock sources can be used to drive the system clock (SYSCLK): •...
Page 100: Clock Tree Diagram
6.2.1 Clock Tree Diagram Figure 6-2 Clock Tree FLASH_CLK Clock Tree to Flash programming TRNG 1M Prescaler TRNG_CLK 1M Legend: /2/4/ /32 HSE = High-speed external clock signal TRNG1MSEL HSI = High-speed internal clock signal ADC 1M LSE = Low-speed external clock signal Prescaler ADC1/2/3/4_CLK 1M LSI = Low-speed internal clock signal...
Page 101: External Crystal/Ceramic Resonator (Hse Crystal)
• HSE user external clock To reduce distortion of the clock output and shorten the start-up Stablize time, the crystal/ceramic resonator and load capacitor must be placed as close as possible to the oscillator pins. The load capacitance value must be adjusted according to the chosen oscillator.
Page 102: Pll Clock
The RCC_CTRL.HSIRDF bit flag indicates if the HSI RC oscillator is stable. At startup, the HSI RC output clock is not released until this bit is set by hardware. HSI clock can be switched on and off using the RCC_CTRL.HSIEN bit. If the HSE crystal oscillator fails, the HSI clock is used as a backup clock source.
Page 103: System Clock (Sysclk) Selection
Calibration can be achieved by measuring the LSI clock frequency using the TIM5's input clock (TIM5_CLK). The measurement is guaranteed by the accuracy of the HSE. The software can obtain the accurate RTC clock base by adjusting the 20 bit prescaler of the RTC, and obtain the accurate independent watchdog (IWDG) timeout time by calculation.
Page 104: Watchdog Clock
The LSE clock is in the backup domain, but the HSE and LSI clocks are not. therefore: • If LSE is selected as RTC clock: − As long as VBAT remains powered, the RTC continues to work even though the VDD power supply is cut off.
Page 105: Clock Control Register (Rcc_Ctrl)
Offset Register RCC_CFG MCOPRES[3:0] MCO[2:0] AHBPRES[3:0] 004h Reset Value RCC_CLKINT 008h Reserved Reserved Reset Value RCC_APB2PRST 00Ch Reserved Reset Value RCC_APB1PRST 010h Reset Value RCC_AHBPCLKEN 014h Reserved Reset Value RCC_APB2PCLKEN 018h Reserved Reset Value RCC_APB1PCLKEN 01Ch Reset Value RCC_BDCTRL 020h Reserved Reserved Reserved...
Page 106 Reset value: 0x0000 0083 Bit Field Name Description 31:26 Reserved Reserved, the reset value must be maintained. PLLRDF PLL clock ready flag Set by hardware once PLL is ready. 0: PLL is not ready 1: PLL is ready PLLEN PLL enable Set and cleared by software.
Page 107: Clock Configuration Register (Rcc_Cfg)
Bit Field Name Description These bits are automatically initialized at startup. HSITRIM[4:0] Internal high-speed clock correction value Written by software. The values of these bits will be added to the HSICAL[7:0] bits in order to form the final value for calibrating the frequency of the internal HSI RC oscillator.
Page 108 Bit Field Name Description 1011: Divide PLL clock by 11 as MCO clock 1100: PLL clock divided by 12 as MCO clock 1101: Divide PLL clock by 13 as MCO clock 1110: Divide PLL clock by 14 as MCO clock 1111: Divide PLL clock by 15 as MCO clock Other values: not allowed to set PLLMULFCT[4]...
Page 109 Bit Field Name Description 01100: PLL input clock × 14 01101: PLL input clock × 15 01110: PLL input clock × 16 01111: PLL input clock × 16 10000: PLL input clock × 17 10001: PLL input clock × 18 10010: PLL input clock ×...
Page 110: Clock Interrupt Register (Rcc_Clkint)
Bit Field Name Description 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 AHBPRES[3:0] AHB prescaler Set and cleared by software to configure the division factor of the AHB clock (HCLK).
Page 111 Bit Field Name Description 31:24 Reserved Reserved, the reset value must be maintained. CLKSSICLR Clock security system interrupt clear Set by the software to clear the CLKSSIF flag. 0: No effect 1: Clear the CLKSSIF flag 22:21 Reserved Reserved, the reset value must be maintained. PLLRDICLR PLL ready interrupt clear Set by the software to clear the PLLRDIF flag.
Page 112: Apb2 Peripheral Reset Register (Rcc_Apb2Prst)
Bit Field Name Description LSIRDIEN LSI ready interrupt enable Set and cleared by software to enable and disable LSI ready interrupt. 0: Disable LSI ready interrupt 1: Enable LSI ready interrupt CLKSSIF Clock security system interrupt flag Set by hardware when a failure is detected in the external HSE oscillator. 0: No clock security system interrupt caused by HSE clock failure 1: Clock security system interrupt caused by HSE clock failure Reserved...
Page 113 Bit Field Name Description 31:21 Reserved Reserved, the reset value must be maintained. I2C4RST I2C4 reset Set and cleared by software. 0: Clear the reset 1: Reset I2C4 I2C3RST I2C3 reset Set and cleared by software. 0: Clear the reset 1: Reset I2C3 UART7RST UART7 reset...
Page 114: Apb1 Peripheral Reset Register (Rcc_Apb1Prst)
Bit Field Name Description TIM1RST TIM1 timer reset Set and cleared by software. 0: Clear the reset 1: Reset TIM1 timer 10:9 Reserved Reserved, the reset value must be maintained. IOPGRST GPIO port G reset. Set or cleared by software. 0: Clear the reset 1: Reset GPIO port G IOPFRST...
Page 115 UART5 UART4 USART3 USART2 Reserved DACRST PWRRST BKPRST CAN2RST CAN1RST Reserved USBRST I2C2RST I2C1RST Reserved WWDG SPI3RST SPI2RST Reserved Reserved TIM7RST TIM6RST TIM5RST TIM4RST TIM3RST TIM2RST Bit Field Name Description 31:30 Reserved Reserved, the reset value must be maintained. DACRST DAC interface reset.
Page 116 Bit Field Name Description 0: clear the reset 1: Reset UART5 UART4RST UART4 reset Set and cleared by software. 0: Clear the reset 1: Reset UART4 USART3RST USART3 reset. Set or cleared by software. 0: clear the reset 1: Reset USART3 USART2RST USART2 reset Set and cleared by software.
Page 117: Ahb Peripheral Clock Enable Register (Rcc_Ahbpclken)
Bit Field Name Description 0: Clear the reset 1: Reset TIM4 timer TIM3RST TIM3 timer reset Set and cleared by software. 0: Clear the reset 1: Reset TIM3 timer TIM2RST TIM2 timer reset Set and cleared by software. 0: Clear the reset 1: Reset TIM2 timer 6.3.7 AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN) Address offset: 0x14...
Page 118 Bit Field Name Description Set and cleared by software. 0: ADC2 clock disabled 1: ADC2 clock enabled ADC1EN ADC1 clock enable Set and cleared by software. 0: ADC1 clock disabled 1: ADC1 clock enabled SACEN SAC clock enable Set and cleared by software. 0: SAC clock disabled 1: SAC clock enabled...
Page 119: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Pclken)
Bit Field Name Description disabled 1: DMA2 clock enabled DMA1EN DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled 6.3.8 APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN) Address offset: 0x18 Reset value: 0x0000 0000 Bit Field Name Description...
Page 120 Bit Field Name Description DVPEN clock enable Set and cleared by software. clock disabled clock enabled Reserved Reserved, the reset value must be maintained. USART1EN USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled TIM8EN TIM8 Timer clock enable Set and cleared by...
Page 121: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Pclken)
Bit Field Name Description disabled 1: IO Port D clock enabled IOPCEN IO Port C clock enable Set and cleared by software. 0: IO Port C clock disabled 1: IO Port C clock enabled IOPBEN IO Port B clock enable Set and cleared by software.
Page 122 Bit Field Name Description 0: DAC interface clock disabled 1: DAC interface clock enable PWREN Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable BKPEN Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled CAN2EN...
Page 123 Bit Field Name Description UART4EN UART4 clock enable Set and cleared by software. 0: UART4 clock disabled 1: UART4 clock enabled USART3EN USART2 clock enable Set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled USART2EN USART2 clock enable Set and cleared by software.
Page 124: Backup Domain Control Register (Rcc_Bdctrl)
Bit Field Name Description disabled 1: TIM7 clock enabled TIM6EN TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled TIM5EN TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled TIM4EN...
Page 125: Clock Control/Status Register (Rcc_Ctrlsts)
Bit Field Name Description 0: No effect 1: Reset the entire backup domain RTCEN RTC clock enable Set and cleared by software. 0: Disable RTC clock 1: Enable RTC clock 14:10 Reserved Reserved, the reset value must be maintained. RTCSEL[1:0] RTC clock source selection Set by software to select RTC clock source.
Page 126 Bit Field Name Description LPWRRSTF Low power reset flag Set by hardware when a low-power management reset occurs. Cleared by software by writing to the RMRSTF bit. 0: No low-power management reset occurred 1: A low-power management reset occurred WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs.
Page 127: Ahb Peripheral Reset Register (Rcc_Ahbprst)
Bit Field Name Description 0: No effect 1: Clear the reset flag RAMRSTF RAM reset flag. Set by hardware when a RAM reset occurs and cleared by software by writing to the RMRSTF bit. 0: No RAM reset occurred 1: A RAM reset has occurred Reserved Reserved, the reset value must be maintained.
Page 128 Bit Field Name Description 31:18 Reserved Reserved, the reset value must be maintained. QSPIRST QSPI reset Set and cleared by software. 0: Clear the reset 1: Reset QSPI ETHMACRST ETHMAC reset Set and cleared by software. 0: Clear the reset 1: Reset ETHMAC ADC4RST ADC4 reset...
Page 129: Clock Configuration Register 2 (Rcc_Cfg2)
Bit Field Name Description Reserved Reserved, the reset value must be maintained. RNGCRST RNGC reset Set and cleared by software. 0: Clear the reset 1: Reset RNGC Reserved Reserved, the reset value must be maintained. 6.3.13 Clock Configuration Register 2 (RCC_CFG2) Address offset: 0x2c Reset value: 0x0000 3800 Bit Field...
Page 130: Clock Configuration Register 3 (Rcc_Cfg3)
Bit Field Name Description 11110: ADC 1M clock source divided by 31 11111: ADC 1M clock source divided by 32 Note: ADC clock must be configured to 1M ADC1MSEL ADC 1M clock source selection. Set or cleared by software. 0: Select HSI oscillator clock as the input clock of ADC 1M 1: Select HSE oscillator clock as the input clock of ADC 1M Reserved Reserved, the reset value must be maintained.
Page 131 Bit Field Name Description 31:19 Reserved Reserved, the reset value must be maintained. TRNG1MEN TRNG analog interface clock enable. Set or cleared by software. 0: Disable TRNG analog interface clock 1: Enable TRNG analog interface clock TRNG1MSEL TRNG 1M clock selection. Set or cleared by software.
Page 132: Gpio And Afio
GPIO and AFIO Summary GPIO is general purpose input/output, and AFIO is alternate function input/output. Up to 97 GPIO are supported on the chip, which are divided into 7 groups (GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF/GPIOG ) with 16 ports in each group (10 in group F and 7 in group G). GPIO port and other alternate peripherals share pins, which can be configured by users according to requirements.
Page 133: I/Ofunction Description
Figure 7-1 Basic structure of I/O port Push-pull/Open-drain/Close P-MOS Write Bit set/clear register Output data Output Control register Write/Read N-MOS AFIO output From On-chip peripherals Output driver I/O PIN Diode ON/OFF Read Read Input data register AFIO input Schmitt trigger ON/OFF Enter On-chip perpherals Analog input...
Page 134: Table 7-2 I/O Characteristics Of Different I/O Configurations
Table 7-2 I/O characteristics of different I/O configurations Characteristic GPIO input GPIO output Analog mode Peripheral alternate According to peripheral Output buffer Disable Enable Disable function configuration Disable According to peripheral Schmitt trigger Enable Enable The output value is function configuration forced to 0.
Page 135: Figure 7-2 Input Float/Pull-Up/Pull-Down Configuration
Figure 7-2 Input float/pull-up/pull-down configuration Bit set/clear register Output Driver Write Output data register Write/Read I/0 PIN Diode ON/OFF Input data register Read Schmitt trigger ON/OFF Input float/pull up/pull down Input driver Output mode When I/O port is configured as output mode: •...
Page 136: Figure 7-3 Output Mode Configuration
Figure 7-3 Output mode configuration Alternate function mode When I/O ports are configured for alternate function mode: • Schmidt trigger input is activated. • Weak pull-up and pull-down resistors are disabled. • In the open-drain or push-pull configuration, the output buffer is turned on. •...
Page 137: Analog Mode
Figure 7-4 Alternate function configuration Analog mode When the I/O port is configured in analog mode: • Weak pull-up and pull-down resistors are disabled. • Read access to the input data register gets the value “0”. • Output buffer is disabled. •...
Page 138: Status After Reset
Figure 7-5 High impedance analog mode configuration 7.2.2 Status after reset During and just after the reset, the alternate functions are not active, and the I/O port is configured to be in analog mode (PCFGy[1:0]=00b，PMODEy[1:0]=00b) by default. But there are several exceptional signals: •...
Page 139: Individual Bit Setting And Bit Clearing
− PC13~15 are the three IOs in the backup domain. After the backup domain is powered on for the first time, these three IOs default to analog mode;. • PB2/BOOT1： − PB2/BOOT1 is in the pull-down input state by default; −...
Page 140 output signal of the on-chip peripheral. If the software configures a GPIO pin as output alternate function, but the peripheral is not activated, then its output will be uncertain. Clock output MCO The microcontroller allows the clock signal to be output to the external MCO pin (PA8). PA8 must be configured to push-pull alternate output function mode.
Page 141 PAD mode PC14 and PC15 condition configuration GPIO mode LSE is off, the backup domain is powered by The mode of GPIO VDD, and it can only be used in GPIO mode depends on the when the 1.1V power supply is turned off application.
Page 142: Jtag/Swd Alternate Function Remapping
This function can only be applied to 48-pin and 64-pin packages (there are PD0 and PD1 on 80-pin, 100- pin and 128-pin packages, and there is no need to remap them). Note: The external interrupt/event function has not been remapped. On 48-pin and 64-pin packages, PD0 and PD1 cannot be used to generate external interrupts/events.
Page 143: Table 7-4 Adc1 External Trigger Injection Conversion Alternate Function Remapping
The first cycle: the signal input to the kernel by SWD_JTAG with 1/0 input is connected to 0 or 1(NJTRST /TDI/TMS is connected to 1,JTCK is connected to 0); Second cycle: IOM controls the control signals of SWD_JTAG pin (such as direction, pull-down, schmidt input, etc.). 7.2.5.5.2 Pull-down configuration Since the pins of JTAG are directly connected to the internal debug register (JTCK/SWCLK is directly connected to the clock terminal), it is necessary to ensure that the input pins of JTAG cannot be floating.
Page 144: Table 7-10 Adc4 External Trigger Injection Conversion Alternate Function Remapping
ADC3 external trigger ADC3 external trigger regular conversion is connected ADC3 external trigger regular conversion is rule conversion to EXTI10. connected to TIM5_CH3 Table 7-10 ADC4 external trigger injection conversion alternate function remapping Alternate function ADC4_ETRI = 0 ADC4_ETRI = 1 ADC4 external trigger ADC4 external trigger injection conversion is ADC4 external trigger injection conversion is...
Page 145: Table 7-16 Tim1 Alternate Function Remapping
Table 7-16 TIM1 alternate function remapping Alternate function TIM1_RMP[1:0] = 00 TIM1_RMP[1:0] = 01 TIM1_RMP[1:0] = 10 TIM1_RMP[1:0] = 11 (No remapping) (Partial remapping) (Partial remapping) (Full remapping) TIM1_ETR PA12 PA12 TIM1_CH1 TIM1_CH2 PE11 TIM1_CH3 PA10 PA10 PE13 TIM1_CH4 PA11 PA11 PE14 TEAM1_BKIN...
Page 146: Table 7-20 Dvp Alternate Function Remapping
DVP alternate function remapping The mapping relationship of DVP signals is shown in the following Table. Table 7-20 DVP alternate function remapping Alternate function DVP_RMP[1:0] = 00 DVP_RMP[1:0] = 01 DVP_RMP[1:0] = 11 DVP_HSYNC DVP_VSYNC DVP_PCLK DVP_D0 DVP_D1 DVP_D2 DVP_D3 DVP_D4 PF12 PB10...
Page 147: Table 7-24 Uart4 Alternate Function Remapping
Alternate function USART3_RMP[1:0] = 00 USART3_RMP[1:0] = 01 USART3_RMP[1:0] = 11 USART3_RX PB11 PC11 USART3_CK PB12 PC12 PD10 USART3_CTS PB13 PD11 USART3_RTS PB14 PD12 UARTx alternate function remapping UART4/5/6/7 interfaces have remapping function. See the alternate remapping configuration register (AFIO_RMP_CFG3). 7.2.5.11.1 UART4 pin remapping Table 7-24 UART4 alternate function remapping Alternate function...
Page 148: Table 7-29 I2C2 Pin Remapping
7.2.5.12.2 I2C2 pin remapping See alternate remapping configuration register (AFIO_RMP_CFG3). Table 7-29 I2C2 pin remapping Alternate function I2C2_RMP[1:0] = 00 I2C2_RMP[1:0] = 01 I2C2_RMP[1:0] = 11 I2C2_SCL PB10 I2C2_SDA PB11 I2C2_SMBA PB12 7.2.5.12.3 I2C3 pin remapping See alternate remapping configuration register (AFIO_RMP_CFG3). Table 7-30 I2C3 pin remapping Alternate function I2C3_RMP[1:0] = 00...
Page 149: Table 7-34 Spi3/I2S3 Pin Remapping
7.2.5.13.3 SPI3/I2S3 pin remapping See alternate remapping configuration register (AFIO_RMP_CFG3). Table 7-34 SPI3/I2S3 pin remapping Alternate function SPI3_RMP[1:0] = 00 SPI3_RMP[1:0] = 01 SPI3_RMP[1:0] = 10 SPI3_RMP[1:0] = 11 SPI3_NSS/I2S3_WS PA15 SPI3_SCK/I2S3_CK PC10 SPI3_MISO PC11 PD11 SPI3_MOSI/I2S3_SD PC12 PD12 SDIO alternate function remapping See alternate remapping configuration register (AFIO_RMP_CFG3).
Page 150: I/O Configuration Of Peripherals
Table 7-37 ETH pin remapping Alternate function ETH_RMP[1:0] = 00 ETH_RMP[1:0] = 01 ETH_RMP[1:0] = 10 ETH_RMP[1:0] = 11 ETH_MII_MDC ETH_RMII_MDC ETH_MII_TX2 ETH_MII_TX_CLK ETH_MII_CRS_WKUP ETH_MII_RX_CLK ETH_MII_REF_CLK ETH_MII_MDIO ETH_RMII_MDIO ETH_MII_COL ETH_MII_RX_DV ETH_RMII_CRS_DV ETH_MII_RXD0 ETH_RMII_RXD0 ETH_MII_RXD1 PD10 PD10 ETH_RMII_RXD1 ETH_MII_RXD2 PD11 ETH_RMII_RXD2 ETH_MII_RXD3 PD12 ETH_RMII_RXD3...
Page 151: Table 7-39 Tim1/Tim8
Table 7-39 TIM1/TIM8 TIM1/TIM8 pin Configuration PAD configuration mode Input capture Input floating channel x TIM1/8_CHx Output channel x Push-pull alternate output TIM1/8_CHxN Complementary Push-pull alternate output channel x output TIM1/8_BKIN Brake input Input floating TIM1/8_ETR External trigger Input floating clock input Table 7-40 TIM2/3/4/5 TIM2/3/4/5 pin...
Page 152: Table 7-43 Usart
Table 7-43 USART USART pin Configuration GPIO configuration full duplex Push-pull alternate output transmissions USARTx_TX Half duplex Push-pull alternate output synchronous mode full duplex Input floating or input pull- transmissions USARTx_RX Half duplex Unused, can be used as synchronous mode general I/O.
Page 153: Table 7-46 I2S
SPI pin Description GPIO configuration Hardware master/slave mode Input floating or pull-up input or input pull- down Hardware mode /NSS output Push-pull alternate output (NSS can choose SPIx_NSS enable idle high resistance or idle is 1 when it is the master) Software mode Unused, can be used as general I/O.
Page 154: Table 7-49 Eth
Table 7-49 ETH MAC signal Pin configuration Push-pull alternate output, high ETH_MDC speed (50MHz) ETH_MII_TXD2 Push-pull alternate output ETH_MII_TX_CLK Input floating (reset state) ETH_MII_CRS Input floating (reset state) ETH_MII_RX_CLK Input floating (reset state) ETH_RMII_REF_CLK Push-pull alternate output, high ETH_MDIO speed (50MHz) ETH_MII_COL Input floating (reset state) ETH_MII_RX_DV...
Page 155: Gpio Locking Mechanism
USB pin GPIO configuration connected to the internal USB transceiver. Table 7-51 Other Alternate function GPIO configuration RTC output When configuring BKP_CR and TAMPER-RTC BKP_RTCCR registers, it is forced by Intrusion event input hardware. Clock output Push-pull alternate output EXTI input line External interrupt input Input floating or pull-up input or input pull-down...
Page 156 GPIOB base address: 0x40010C00 GPIOC base address: 0x40011000 GPIOD base address: 0x40011400 GPIOE base address: 0x40011800 GPIOF base address: 0x40011C00 GPIOG base address: 0x40012000 156 / 816...
Page 157: Gpio Port Low Configuration Register (Gpiox_Pl_Cfg)
Table 7-52 GPIO registers overview Offset Register GPIOx_PL_CFG 000h Reset Value x=A,C,D,E,F,G 0 GPIOx_PH_CFG 004h Reset Value x=B,C,D,E,F,G 0 GPIOx_PID 008h Reserved Reset Value GPIOx_POD 00Ch Reserved Reset Value x=C,D,E,F,G GPIOx_PBSC 010h Reset Value GPIOx_PBC 014h Reserved Reset Value GPIOx_PLOCK_CFG 018h Reserved Reset Value...
Page 158: Gpio Port High Configuration Register (Gpiox_Ph_Cfg)
Bit field Name Description 31:30 PCFGy[1:0] Port x configuration bit (y = 0…7) 27:26 PMODE[1:0]=00 input mode: 23:22 00: analog function mode (state after reset) 19:18 01: Input floating mode 15:14 10: input pull-up/ input pull-down mode (note: when configuring the input pull-up/ 11:10 input pull-down mode, you need to set/reset the corresponding GPIOx_POD register) 11: reserved...
Page 159: Gpio Port Input Data Register (Gpiox_Pid)
Bit field Name Description 15:14 10: input pull-up/ input pull-down mode (note: when configuring the input pull-up/ 11:10 input pull-down mode, you need to set/reset the corresponding GPIOx_POD register) 11: reserved When MODE[1:0]>00 output mode: 00: General push-pull output mode 01: General open-drain output mode 10: Alternate function push-pull output mode 11: Open-drain output mode of alternate function...
Page 160: Gpio Port Bit Setting/Clearing Register (Gpiox_Pbsc)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 PODy Port output data (y = 0…15) These bits can only be read or written in the form of 16-bit words. GPIOx_PBSC(x = A…G) can be independently set/cleared for the corresponding POD bit. 7.3.6 GPIO port bit setting/clearing register (GPIOx_PBSC) Address offset: 0x10 Reset value: 0x0000 0000...
Page 161: Gpio Port Lock Configuration Register (Gpiox_Plock_Cfg )
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 PBCy Clear bit y of port GPIOx (y = 0...15) These bits can only be written and operated as words (16 bits). 0: does not affect the corresponding PODy bit 1: Clear the corresponding PODy bit to 0 7.3.8 GPIO port lock configuration register (GPIOx_PLOCK_CFG ) Address offset: 0x18...
Page 162: Gpio Driver Capability Configuration Register (Gpiox_Ds_Cfg )
7.3.9 GPIO driver capability configuration register (GPIOx_DS_CFG ) Address offset: 0x20 Reset value: 0x0000 FFFF（x = A,B,C,D,E）；0x0000 F03F（x=F）；0x0000 023F（x=G） Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 DS_CFGy The drive capability configuration bit y of port GPIOx (y = 0…15) These bits can only be read or written in the form of 16-bit words.
Page 163: Afio Registers
AFIO registers 7.4.1 AFIO register overview AFIO base address: 0x40010000 Table 7-53 AFIO register overview Offset Register AFIO_ECTRL 000h Reserved Reset Value AFIO_RMP_CFG 004h Reserved Reset Value AFIO_EXTI_CFG1 EXTI3_CFG[3:0] EXTI2_CFG[3:0] EXTI1_CFG[3:0] EXTI0_CFG[3:0] 008h Reserved Reset Value AFIO_EXTI_CFG2 EXTI7_CFG[3:0] EXTI6_CFG[3:0] EXTI5_CFG[3:0] EXTI4_CFG[3:0] 00Ch Reserved...
Page 164: Afio Event Control Register (Afio_Ectrl)
7.4.2 AFIO event control register (AFIO_ECTRL) Address offset: 0x00 Reset value: 0x0000 0000 Bit field Name Description 31:8 Reserved Reserved, the reset value must be maintained. Event output enable bit. When this bit is set, the Cortex event output signal will be connected to the I/O port selected by PORT_SEL[2:0] and PIN_SEL[3:0].
Page 165 Bit field Name Description 31:27 Reserved Reserved, the reset value must be maintained. 26:24 SW_JTAG_CFG[2:0] Serial wire JTAG configuration These bits can only be written by software (reading these bits will return an undefined value) and are used to configure the I/O ports of the SWD-JTAG alternate function.
Page 166 Bit field Name Description This bit can be set to '1' or set to '0' by software. It controls the internal image of TIM5_CH4. 0: TIM5_CH4 is connected to PA3 1: LSI internal oscillator is connected to TIM5_CH4, the purpose is to calibrate the LSI PD01_RMP PD0/PD1 mapping on OSC_IN/OSC_OUT (PD0/PD1 mapping on...
Page 167 Bit field Name Description 00: no remapping (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3); 01: Partial image (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3); 10: Partial image (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11); 11: Complete image (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11). TIM1_RMP[1:0] Remapping of Timer 1 These bits can be set to '1' or set to '0' by software to control timer 1 channels 1 to 4, 1N to 3N, external trigger (ETR) and brake input (BKIN) The image on the GPIO port.
Page 168: Afio External Interrupt Configuration Register 1(Afio_Exti_Cfg1)
Bit field Name Description This bit can be set to '1' or set to '0' by software and used in conjunction with SPI1_RMP_1 to form SPI1_RMP[1:0] to control the image of SPI1's NSS, SCK, MISO and MOSI alternate functions on the GPIO port. 00: No remapping (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7);...
Page 169: Afio External Interrupt Configuration Register 2(Afio_Exti_Cfg2)
7.4.5 AFIO external interrupt configuration register 2(AFIO_EXTI_CFG2) Address offset: 0x0C Reset value: 0x0000 0000 Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 EXTIx_CFG[3:0] EXTIx configuration (x = 4… 7) These bits can be read and written by software and used to select the input source of the EXTIx external interrupt.
Page 170: Afio External Interrupt Configuration Register 4(Afio_Exti_Cfg4)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 EXTIx_CFG[3:0] EXTIx configuration (x = 8… 11) These bits can be read and written by software and used to select the input source of the EXTIx external interrupt. EXTI8 configuration：...
Page 171: Afio Alternate Remapping Configuration Register 3(Afio_Rmp_Cfg3)
Bit field Name Description 0011: PD13 pin 0100: PE13 pin 0101: PF13 pin 0110: Reserved EXTI14 configuration： 0000: PA14 pin 0001: PB14 pin 0011: PC14 pin 0011: PD14 pin 0100: PE14 pin 0101: PF14 pin 0110: Reserved EXTI15 configuration： 0000: PA15 pin 0001: PB15 pin 0011: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: Reserved 7.4.8 AFIO alternate remapping configuration register 3(AFIO_RMP_CFG3)
Page 172 Bit field Name Description These bits can be set to '1' or set to '0' by software to control the image of the TX and RX alternate functions of UART6 on the GPIO port. 00: No remapping (TX/PE2, RX/PE3); 01: Unused combination; 10: Remapping (TX/PC0, RX/PC1);...
Page 173 Bit field Name Description RXD3/PD12, PPS_OUT/PB5, TXD3/PB8); 10: Remapping (RX_DV/CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1, PPS_OUT/PB6, TXD3/PB7); 11: Remapping (RX_DV/CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PB0, RXD3/PB1, PPS_OUT/PB6, TXD3/PB7). 15:14 SPI3_RMP[1:0] Remapping of SPI3 This bit can be set to '1' or set to '0' by software to control the image of the NSS, SCK, MISO and MOSI alternate functions of SPI3 on the GPIO port.
Page 174: Afio Alternate Remap Configuration Register 4 (Afio_ Rmp_Cfg4 )
Bit field Name Description 00: No remapping (NSS/PA4, SCK/PA5, IO0/PA6, IO1/PA7, IO2/PC4, IO3/PC5); 01: Unused combination; 10: Remapping (NSS/PF0, SCK/PF1, IO0/PF2, IO1/PF3, IO2/PF4, IO3/PF5); 11: Remapping (NSS/PC10, SCK/PC11, IO0/PC12, IO1/PD0, IO2/PD1, IO3/PD2). Reserved Reserved, the reset value must be maintained. CAN2_RMP[1:0] CAN2 remapping This bit can be set to '1' or set to '0' by software to control the image of the...
Page 175 Bit field Name Description 1: NSS is 1 when idle 21:20 DVP_RMP[1:0] Remapping of DVP This bit can be set to '1' or '0' by software. 00: No remapping (HSYNC/PA1, VSYNC/PA2, CLK/PA3, D0/PA4, D1/PA5, D2/PA6, D3/PA7, D4/PC4, D5/PC5, D6/PB0, D7/PB1) ； 01: Remapping (HSYNC/PE2, VSYNC/PE3, CLK/PE4, D0/PE5, D1/PE6, D2/PC0, D3/PB2, D4/PF12, D5/PF13, D6/PF14, D7/PF15);...
Page 176: Afio Alternate Remapping Configuration Register 5(Afio_Rmp_Cfg5)
Bit field Name Description 10: Unused combination; 11: Remapping (COMP6_OUT/PB7). COMP5_RMP[1:0] Remapping of COMP5_OUT This bit can be set to '1' or '0' by software. 00: No remapping (COMP5_OUT/PB0); 01: Remapping (COMP5_OUT/PB11); 10: Remapping (COMP5_OUT/PB6); 11: Remapping (COMP5_OUT/PA11). COMP4_RMP[1:0] Remapping of COMP4_OUT This bit can be set to '1' or '0' by software.
Page 177 Bit field Name Description 31:24 Reserved Reserved, the reset value must be maintained. EGB4_DET_EN EMC GB4 detection enable bit (ground bounce detection). 0: Disable 1: Enable EGB3_DET_EN EMC GB3 detection enable bit. 0: Disable 1: Enable EGB2_DET_EN EMC GB2 detection enable bit. 0: Disable 1: Enable EGB1_DET_EN...
Page 178 Bit field Name Description EGB2_RST_EN When EMC GB2 detects it, the system resets the enable bit. 0: Disable 1: Enable EGB1_RST_EN When EMC GB1 detects it, the system resets the enable bit. 0: Disable 1: Enable EGBN4_RST_EN When EMC GBN4 detects it, the system resets the enable bit. 0: Disable 1: Enable EGBN3_RST_EN...
Page 179: Dma Controller
DMA controller Introduction The DMA controller can access totally 8 AHB slaves: Flash, SRAM, ADC, SDIO, QSPI, ETH, ABP1 and APB2. DMA Controller is controlled by CPU to perform fast data movement from source to destination. After configuration, data can be transferred without CPU intervention. Thus, CPU can be released for other computation/control tasks or save overall system power consumption.
Page 180: Block Diagram
Block diagram Figure 8-1 DMA block diagram ICode Flash Flash Interface controller DCode Cortex-M4F System SRAM DMA1 Bridge 1 Bridge 2 SDIO USART1 I2C1 SPI1 QSPI I2C2 Arbiter TIM1 USART2 TIM8 AHB slave USART3 UART6 device UART4 UART7 DMA requests UART5 DMA2 I2C3...
Page 181: Channel Priority And Arbitration
• Data access: determine the source address (DMA_PADDRx or DMA_MADDRx) according to the transfer direction and read data from the source address. • Data storage: determine the destination address (DMA_PADDRx or DMA_MADDRx) according to the transfer direction and store the read data into the destination address space. •...
Page 182 Destina- Number Source tion Source: Transfer operations Destination: width width transfer Address / data (R: Read,W: Write) Address / data (bit) (bit) (bit) 0x1 / B1 2: R B1 [7:0] @0x1, W 00B1 [15:0] @0x2 0x2 / 00B1 0x2 / B2 3: R B2 [7:0] @0x2, W 00B2 [15:0] @0x4 0x4 / 00B2 0x3 / B3...
Page 183: Peripheral/Memory Address Incrementation
• When source size is larger or equal to destination size and smaller than 32 bits, DMA duplicates source data to 32 bits data. E.g., source data is 8 bits data 0x1F, HWDATA[31:0] =0x1F1F_1F1F. if source data is 16 bits data 0x2345, then HWDATA[31:0] = 0x2345_2345.
Page 184: Flow Control
If the interrupt is transfer complete interrupt, software can configure the next transfer, or report to user this channel transformation is done. 8.4.7 Flow control Three major flow controls are supported: • Memory to memory • Memory to peripheral • Peripheral to memory Flow control is controlled by two register bits in each DMA channel configuration register.
Page 185: Dma Request Mapping
its dedicated interrupt, interrupt mask control and interrupt status bit. interrupt status bit is cleared when interrupt flag clear bit is set. • Half transfer interrupt: An interrupt is generated when half of the channel data is transferred. Interrupt is a level signal. Each channel has its dedicated interrupt, interrupt mask control and interrupt status bit.
Page 186: Table 8-4 Dma1 Request Mapping Table For Each Channel
Figure 8-2 DMA1 request mapping Peripheral request signal Fixed hardware priority ADC1 High priority UART5_TX Hardware request 1 I2C3_TX TIM2_CH3 Channel 1 TIM4_CH1 Software trigger (MEM2MEM bit) Channel 1 enable bit SPI1_RX USART3_TX Hardware request 2 I2C3_RX TIM1_CH1 Channel 2 TIM2_UP Software trigger (MEM2MEM bit) TIM3_CH3...
Page 187: Figure 8-3 Dma2 Request Mapping
Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 TIM2_CH4 TIM3_CH4 TIM3_CH1 TIM3 TIM3_CH3 TIM3_UP TIM3_TRIG TIM4 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP DMA2 controller The DMA2 request mapping is shown in the following figure. By configuring the registers of the corresponding peripherals, the DMA requests of each peripheral can be turned on or off independently, and according to the channel priority, only one request is valid at the same time.
Page 188: Dma Registers
Table 8-5 DMA2 request mapping table for each channel Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 ADC3 ADC4 SPI/I2S SPI3/I2S3_RX SPI3/I2S3_TX QSPI_RX QSPI_TX I2C4 I2C4_TX I2C4_RX UART UART6_RX UART6_TX UART4_RX UART4_TX UART7_RX UART7_TX SDIO SDIO...
Page 189 Offset Register Reset Value DMA_MADDR2 ADDR[31:0] 028h Reset Value DMA_CHSEL2 CH_SEL[5:0] 02Ch Reserved Reset Value DMA_CHCFG3 030h Reserved Reset Value DMA_TXNUM3 NDTX[15:0] 034h Reserved Reset Value DMA_PADDR3 ADDR[31:0] 038h Reset Value DMA_MADDR3 ADDR[31:0] 03Ch Reset Value DMA_CHSEL3 CH_SEL[5:0] 040h Reserved Reset Value DMA_CHCFG4 044h...
Page 190: Dma Interrupt Status Register (Dma_Intsts)
Offset Register Reset Value DMA_TXNUM8 NDTX[15:0] 098h Reserved Reset Value DMA_PADDR8 ADDR[31:0] 09Ch Reset Value DMA_MADDR8 ADDR[31:0] 0A0h Reset Value DMA_CHSEL8 CH_SEL[5:0] 0A4h Reserved Reset Value DMA_CHMAPEN 0A8h Reserved Reset Value 8.5.2 DMA interrupt status register (DMA_INTSTS) Address offset: 0x00 Reset value: 0x0000 0000 Bit field Name...
Page 191: Dma Channel X Configuration Register (Dma_Chcfgx)
Reset value: 0x0000 0000 Bit field Name Description 31/27/23/19/15/11/7/3 CERRFx Clear transfer error flag for channel x (x=1…8). Software can set this bit to clear ERRF of corresponding channel. 0: No action. 1: Reset DMA_INTSTS.ERRF bit of corresponding channel. 30/26/22/18/14/10/6/2 CHTXFx Clear half transfer flag for channel x (x=1…8).
Page 192 Bit field Name Description 1: Channel set to memory to memory transfer. 13:12 PRIOLVL[1:0] Channel priority. Software can program channel priority when channel is not enable 00: Low 01: Medium 10: High 11: Very high 11:10 MSIZE[1:0] Memory data size. Software can configure data size read/write from/to memory address 00: 8-bits 01: 16-bits...
Page 193: Dma Channel X Transfer Number Register (Dma_Txnumx)
Bit field Name Description TXCIE Transfer complete interrupt enable. Software can enable/disable transfer complete interrupt. 0: Disable transfer complete interrupt of channel x 1: Enable transfer complete interrupt of channel x. CHEN Channel enable. Software can set/reset this bit 0: Disable channel. 1: Enable channel.
Page 194: Dma Channel X Memory Address Register (Dma_Maddrx)
Bit field Name Description 31:0 ADDR Peripheral address. Peripheral starting address for DMA to read/write from/to. Increment of address will be decided by DMA_CHCFGx.PSIZE. With DMA_CHCFGx.PSIZE equal to 01, DMA ignores bit 0 of PADDR and if DMA_CHCFGx.PSIZE equal to 10 DMA will ignore bit [1:0] of PADDR. 8.5.7 DMA channel x memory address register (DMA_MADDRx) The x is channel number, x = 1…8 Address offset: 0x14+20 * (x–1)
Page 195 channels of DMA1 will only respond to the DMA request of ADC1. Bit field Name Description 31:6 Reserved Reserved, the reset value must be maintained. CH_SEL[5:0] DMA1 channel request selection 40：UART5_RX 39：ADC2 38：I2C1_RX 37：TIM4_UP 36：TIM2_CH4 35：TIM2_CH2 34：USART2_TX 33：I2C1_TX 32：TIM3_TRIG 31：TIM3_CH1 30：TIM1_CH3 29：USART2_RX 28：I2C2_RX...
Page 196: Dma2 Channel X Channel Request Select Register (Dma2_Chselx)
Bit field Name Description 7：TIM1_CH1 6：I2C3_RX 5：USART3_TX 4：TIM4_CH1 3：TIM2_CH3 2：I2C3_TX 1：UART5_TX 0：ADC1 8.5.9 DMA2 channel x channel request select register (DMA2_CHSELx) The x is channel number, x = 1…8 Address offset: 0x18+20 * (x–1) Reset value: 0x0000 0000 Writing to this register is only valid when the channel MAP is enabled (DMA_CHMAPEN.MAP_EN=1). This register is used to manage the DMA2 channel mapped by the DMA2 peripheral request.
Page 197: Dma Channel Map Enable Register (Dma_Chmapen)
Bit field Name Description 19：TIM7_UP 18：SDIO 17：TIM5_CH2 16：DAC1 15：TIM6_UP 14：UART4_RX 13：TIM8_CH1 12：UART6_TX 11：SPI3/I2S3_TX 10：TIM5_UP 9：TIM5_CH3 8：TIM8_COM 7：TIM8_TRIG 6：TIM8_CH4 5：UART6_RX 4：SPI3/I2S3_RX 3：TIM8_UP 2：TIM8_CH3 1：TIM5_TRIG 0：TIM5_CH4 8.5.10 DMA channel MAP enable register (DMA_CHMAPEN) Address offset: 0xA8 Reset value: 0x0000 0000 Note: After the MAP is enabled, DMA will respond to the DMA request according to the configuration of the selection register.
Page 198: Analog To Digital Conversion (Adc)
Analog to digital conversion (ADC) Introduction The 12-bit ADC is a high-speed analog-to-digital converter using successive approximation. It has multiple channels. The A/D conversion of each channel has four execution modes: single, continuous, scan or discontinuous. ADC measurements are stored (left-aligned/ right-aligned) in 16-bit data registers. The application can detect that the input voltage is within user-defined high/low thresholds by analog watchdog and the maximum frequency of the input clock to the ADC is 80MHz.
Page 199: Function Description
• Support DMA. • Interrupt generation. − At the end of conversion. − At the end of injection conversion. − Analog watchdog event. • Data alignment with embedded data consistency. • Both regular conversions and injection conversions have external triggering options. •...
Page 200: Adc Clock
Table 9-1 ADC pins Name Types Description Input, analog power supply Equivalent to V analog power supply and: 1.8V ≤ V ≤ (3.6V) Input, analog power supply ground Equivalent to V analog power supply ground Input, analog reference positive Positive reference voltage used by ADC, 1.8V ≤ V ≤...
Page 201: Adc Switch Control
Figure 9-2 ADC clock PLL_DIV_CLK ADC_CLK HCLK HCLK ADC_1MCLK 1MCLK 9.3.2 ADC switch control You can proceed to the next step only after the power-up process is complete. You can check if the power-up is complete by polling the ADC_CTRL3.RDY bit. You can set the ADC_CTRL2.ON bit to turn on the ADC.
Page 202 Regular sequence consists of multiple conversions, up to a maximum of 16. The ADC_RSEQx registers specify the regular channels and the conversion order of the regular channels. The ADC_RSEQ1.LEN[3:0] bits specified regular channel sequence length. Note: During conversion, changes to the ADC_RSEQx or ADC_JSEQ registers are prohibited; the ADC_RSEQx or ADC_JSEQ registers can only be changed when the ADC is idle.
Page 203: Figure 9-3 Adc1 And Adc2 Channel Pin Connections
Figure 9-3 ADC1 and ADC2 channel pin connections ADC1 Channel Selection Fast Channel VREF+ VREF- Fast Channel ADC1_IN1 Fast Channel ADC1_IN2 Fast Channel ADC1_IN3 Fast Channel ADC1_IN4 Fast Channel ADC1_IN5 Slow Channel REF+ ADC12_IN6 Slow Channel ADC12_IN7 Slow Channel ADC12_IN8 ADC1 Slow Channel ADC12_IN9...
Page 204: Figure 9-4 Adc3 And Adc4 Channel Pin Connections
Figure 9-4 ADC3 and ADC4 channel pin connections ADC3 Channel Selection Fast Channel VREF+ VREF- Fast Channel ADC3_IN1 Fast Channel ADC3_IN2 Fast Channel ADC3_IN3 Fast Channel ADC3_IN4 Fast Channel ADC3_IN5 Slow Channel REF+ ADC34_IN6 Slow Channel ADC34_IN7 Slow Channel ADC3 ADC34_IN8 Slow Channel ADC34_IN9...
Page 205: Internal Channel
9.3.4 Internal channel • The temperature sensor is connected to channel ADC1_IN16. • is connected to channel ADC1_IN17. BAT/2 • Internal reference voltage VREFINT is connected to ADCx_IN18. • output is connected to channel ADC1_IN3. OP1OUT • output is connected to channel ADC2_IN3. OP2OUT •...
Page 206: Timing Diagram
9.3.7 Timing diagram When ADC_CTRL2.ON is set to 1 for the first time, the ADC is powered on. After the ADC is powered on, the ADC needs a certain time(t ) to ensure its stability. After the ADC is stable, write 1 to ADC_CTRL2.ON again, the STAB ADC starts to convert, and the conversion end flag will be set to 1 after the conversion is completed.
Page 207: Scanning Mode
All injection channels All regular channels All injection and regular channels A single injection channel A single regulars of the channel A single injection or regular channels 9.3.9 Scanning mode By configuring ADC_CTRL1.SCAMD to 1, the scan conversion mode can be turned on, and by configuring the four registers ADC_RSEQ1, ADC_RSEQ2, ADC_RSEQ3, ADC_JSEQ, the conversion sequence can be selected, and the ADC will scan and convert all the regular or Injected channels.
Page 208: Adc Clock
Figure 9-6 Injection conversion delay ADC clock Injected event Latency Note:For the maximum delay value, please refer to the electrical characteristics section in the data manual. 9.3.11 Discontinuous mode Regular channels Configure ADC_CTRL1.DREGCH to 1 to enable the discontinuous mode on the regular channel, obtain the regular sequence by configuring ADC_RSEQ1, ADC_RSEQ2, ADC_RSEQ3, and configure ADC_CTRL1.DCTU[2:0] to control the conversion of n channels each time a trigger signal is generated.
Page 209: Calibration
signal occurs ,the conversion starts from the first channel of the injection sequence again. Only one of injection conversion and regular conversion can be set to discontinuous mode at the same time, and the automatic injection function and discontinuous mode cannot be set at the same time. Calibration In order to reduce the error, the ADC will have a built-in self-calibration mechanism.
Page 210: Programmable Channel Sampling Time
SYM SYM SYM The regular sequence (12bit resolution) Table 9-4 Left-aligne data Injection sequence (12bit resolution) The regular sequence (12bit resolution) Note: When the conversion digits are 10, 8, and 6, refer to the alignment with 12 conversion digits Programmable channel sampling time Specify the number of sampling cycles of ADC in ADC_SAMPTx.SAMPx[2:0], and then the ADC samples the input voltage in the specified sampling cycle.
Page 211: Table 9-5 External Trigger For Regular Channels Of Adc1 And Adc2
Table 9-5 External trigger for regular channels of ADC1 and ADC2 EXTRSEL[2:0] Trigger source Type TIM1_CC1 event TIM1_CC2 event TIM1_CC3 event Internal signal from the on-chip timer TIM2_CC2 event TIM3_TRGO event TIM4_CC4 event EXTI line11/TIM8_TRGO event External pin/internal signal from on-chip timer SWSTRRCH Software control bit Table 9-6 External trigger for regular channels of ADC3 and ADC4...
Page 212: Dma Requests
Table 9-8 External trigger for injection channel of ADC3 and ADC4 EXTJSEL[2:0] Trigger source Type TIM1_TRGO event TIM1_CC4 event TIM4_CC3 event TIM8_CC2 event Internal signal from the on-chip timer TIM8_CC4 event TIM5_TRGO event EXTI line14/TIM5_CC4 event SWSTRJCH Software control bit Note: Injection triggers can interrupt conversion of the regular sequence.
Page 213: Independent Mode
(2) . When working in dual ADC mode, even if DMA is not used to transfer data, DMA needs to be enabled, and the converted data from the ADC can be read through the data register of the main ADC. Figure 9-8 Dual ADC Block Diagram Data bus Data register...
Page 214: Synchronous Injection Mode
may start to convert again when the longer sequence is not completed. Figure 9-9 Schematic diagram of synchronous regular mode conversion of 16 channels Sampling Conversion ADC1 CH16 ADC2 CH16 CH14 CH13 CH12 Trigger ENDC 9.9.3 Synchronous injection mode Converting an injection sequence in this mode, the external trigger comes from the multiplexer of ADC1, determined by ADC_CTRL2.EXTJSEL[2:0], ADC2 will be triggered synchronously.
Page 215: Fast Alternate Mode
Figure 9-10 Schematic diagram of synchronous injection mode conversion of 4 channels Sampling Conversion ADC1 ADC2 Trigger JENDC 9.9.4 Fast alternate mode This mode is for regular sequences (usually one channel). The external trigger comes from the multiplexer of ADC1, which is determined by ADC_CTRL2.EXTRSEL[2:0].
Page 216: Slow Alternate Mode
Figure 9-11 Schematic diagram of fast alternate mode conversion for continuous conversion of 1 channel Sampling 7 ADCCLKs Conversion ADC1 ADC2 CH16 Trigger ENDC(ADC1) ENDC(ADC2) 9.9.5 Slow alternate mode This mode is for regular sequences (usually one channel). The external trigger comes from the multiplexer of ADC1, which is determined by ADC_CTRL2.EXTRSEL[2:0].
Page 217: Rotation Trigger Mode
Figure 9-12 Schematic diagram of slow alternate mode conversion for 1 channel Sampling 14 ADCCLKs 14 ADCCLKs Conversion ADC1 ADC2 CH16 Trigger ENDC(ADC1) ENDC(ADC2) 9.9.6 Rotation trigger Mode This mode is suitable for injection sequences. The external trigger comes from the multiplexer of ADC1, which is determined by ADC_CTRL2.EXTJSEL[2:0].
Page 218: Mixed Synchronous Regular Mode + Synchronous Injection Mode
If the injection discontinuous mode is used on ADC1 and ADC2 at the same time, when the first trigger is generated, the first group of injection channels of ADC1 is converted; when the second trigger is generated, the first group of injection channels of ADC2 is converted;...
Page 219: Mixed Synchronous Injection Mode + Alternate Mode
convert again when the longer sequence is not completed. Figure 9-15 Combination of rotation mode and synchronous regular mode ADC1 regular channel ADC1 injection CH13 channel ADC2 regular CH10 channel ADC2 injection CH14 channel Trigger If another injection trigger occurs during the injection transition, this trigger will be ignored. As shown below: Figure 9-16 Injection trigger occurs during injection transition ADC1 regular channel...
Page 220: Temperature Sensor
Figure 9-17 Alternate single-channel conversions are interrupted by injection sequences CH3 and CH4 Sampling Conversion ADC1 ADC2 ADC1 ADC2 Trigger Temperature sensor Set the ADC_CTRL2.TEMPEN bit to 1, enable the temperature sensor and V and use the temperature sensor REFINT, to detect the ambient temperature when the device is working.
Page 221: Temperature Sensor Using Flow
Figure 9-18 Temperature sensor and VREFINT diagram of the channel TEMPERATURE ADC1_IN16 SENSOR INTERNAL POWER ADCx_IN18 BLOCK(V REFINT 9.10.1 Temperature sensor using flow Configure the channel (ADC_IN16) and sampling time of the channel to be 17.1 us Set ADC_CTRL2.TEMPEN bit to 1 to enable temperature sensor and V REFINT Set ADC_CTRL2.ON bit to 1 to start ADC conversion (or through external trigger) Read the temperature data in the ADC data register, and calculate the temperature value by the following formula:...
Page 222: Adc Registers
Note: ADC1 and ADC2 share one interrupt entry, while ADC3 and ADC4 share one interrupt entry. Table 9-9 ADC interrupt Interrupt event Event flags Enable control bit Regular sequence or injection conversion is complete ENDC ENDCIEN Injection sequence conversion is complete JENDC JENDCIEN Analog watchdog status bit is set...
Page 223: Adc Status Register (Adc_Sts)
Offset Register ADC_JSEQ JSEQ4[4:0] JSEQ3[4:0] JSEQ2[4:0] JSEQ1[4:0] 038h Reserved Reset Value ADC_JDAT1 JDAT1[15:0] 03Ch Reserved Reset Value ADC_JDAT2 JDAT2[15:0] 040h Reserved Reset Value ADC_JDAT3 JDAT3[15:0] 044h Reserved Reset Value ADC_JDAT4 JDAT4[15:0] 048h Reserved Reset Value ADC_DAT DAT[15:0] 04Ch Reserved Reset Value ADC_DIFSEL DIFSEL[18:0] 050h...
Page 224: Adc Control Register 1 (Adc_Ctrl1)
Bit field Name Description Regular channel start flag This bit is set by hardware at the start of regular channel conversion and cleared by software. 0: Regular channel conversion has not started. 1: Regular channel conversion has started. JSTR Injected channel start flag This bit is set by hardware at the start of the injection channel conversion and cleared by software.
Page 225 Bit field Name Description 0: Disables analog watchdog on injection channel. 1: Use analog watchdog on the injection channel. 21:20 Reserved Reserved, the reset value must be maintained 19:16 DUSEL[3:0] Dual mode selection Software uses these bits to select modes of operation. 0000: independent mode;...
Page 226: Adc Control Register 2 (Adc_Ctrl2)
Bit field Name Description 0: Use watchdog on all channels. 1: Use watchdog on single channel. SCANMD Scan mode This bit is set and cleared by the software to enable or disable scan mode. In scan mode, the conversion is made by ADC_RSEQx or the selected channel of the ADC_JSEQ register. 0: Disable scan mode.
Page 227 Bit field Name Description 31:24 Reserved Reserved, the reset value must be maintained TEMPEN Temperature sensor and V Enable REFINT This bit is set and cleared by the software to enable or disable the temperature sensor and Channel. REFINT 0: Disables the temperature sensor and V REFINT 1: Enable the temperature sensor and V REFINT...
Page 228 Bit field Name Description Reserved Reserved, the reset value must be maintained EXTJTRIG External trigger conversion mode for injected channels This bit is set and cleared by software to enable or disable external triggering events that can start injection sequence conversion. 0: Start conversion without external events.
Page 229: Adc Sampling Time Register 1 (Adc_Sampt1)
Bit field Name Description 0: Close ADC conversion/calibration and enter power-down mode. 1: Start ADC and start conversion. Note: If there are other bits changed in this register along with ON, the conversion will not be triggered. This is to prevent the wrong conversion from being triggered. 9.12.5 ADC sampling time register 1 (ADC_SAMPT1) Address offset: 0x0C Reset value: 0x0000 0000...
Page 230: Adc Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1
Bit field Name Description 31:30 Reserved Reserved, the reset value must be maintained 29:0 SAMPx[2:0] Channel x sample time selection These bits are used to independently select the sampling time for each channel. The channel selection bit must remain constant during the sampling period. ADC_SAMPT3.SAMPSEL = 0, the sampling time is set as follows: 000: 1.5 cycles 100: 41.5 cycles...
Page 231: Adc Watchdog Low Threshold Register (Adc_Wdglow)
Bit field Name Description 31:12 Reserved Reserved, the reset value must be maintained 11:0 HTH[11:0] Analog watchdog high threshold These bits define the high thresholds for analog watchdog. 9.12.9 ADC watchdog low threshold register (ADC_WDGLOW) Address offset: 0x28 Reset value: 0x0000 0000 Bit field Name Description...
Page 232: Adc Regular Sequence Register 2 (Adc_Rseq2)
Bit field Name Description SEQ13[4:0] 13th conversion in regular sequence 9.12.11 ADC regular sequence register 2 (ADC_RSEQ2) Address offset: 0x30 Reset value: 0x0000 0000 Bit field Name Description 31:30 Reserved Reserved, the reset value must be maintained 29:25 SEQ12[4:0] 12th conversion in regular sequence These bits are software-defined as the number (0 to 18) of the 12th conversion channel in the conversion sequence.
Page 233: Adc Injection Sequence Register (Adc_Jseq)
Bit field Name Description SEQ1[4:0] 1st conversion in regular sequence 9.12.13 ADC Injection sequence register (ADC_JSEQ) Address offset: 0x38 Reset value: 0x0000 0000 Bit field Name Description 31:22 Reserved Reserved, the reset value must be maintained 21:20 JLEN[1:0] Injected sequence length These bits are software-defined as the number of channels in the injected channel conversion sequence.
Page 234: Adc Regulars Data Register (Adc_Dat)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 JDAT[15:0] Injected data for conversions These bits are read-only and contain the conversion results of the injected channel. The data is left- aligned or right-aligned 9.12.15 ADC regulars data register (ADC_DAT) Address offset: 0x4C Reset value: 0x0000 0000 Bit field...
Page 235: Adc Calibration Factor (Adc_Calfact)
Bit field Name Description Reserved Reserved, the reset value must be maintained 9.12.17 ADC calibration factor (ADC_CALFACT) Address offset: 0x54 Reset value: 0x0000 0000 Bit field Name Description 31:23 Reserved Reserved, the reset value must be maintained 22:16 CALFACTD[6:0] Calibration factors in differential mode This bit can be written by hardware or software After the differential input calibration is complete, the hardware will update it according to the calibration coefficient.
Page 236 Bit field Name Description 31:12 Reserved Reserved, the reset value must be maintained VBATMEN Vbat monitor enable 0: Disable 1: Enable DPWMOD Deep power mode 0: When the ADC is disabled, the ADC enters low power mode 1: When the ADC is disabled, the ADC enters deep sleep mode JENDCAIEN Interrupt enable for any injected channels This bit is set and cleared by the software to enable/disable the injection channel conversion end...
Page 237: Adc Sampling Time Register 3 (Adc_Sampt3)
Bit field Name Description RES[1:0] Data resolution This bit is set and cleared by the software to select the resolution of the conversion 00: 6-bits 01: 8-bits 10: 10-bits 11: 12-bits 9.12.19 ADC sampling time register 3 (ADC_SAMPT3) Address offset: 0x5C Reset value: 0x0000 0000 Bit field Name...
Page 238: Digital To Analog Conversion (Dac)
Digital to analog conversion (DAC) Introduction DAC is a digital/analog converter, mainly digital input, voltage output.DAC data can be 8-bit or 12-bit and supports DMA functionality.When the DAC is configured in 12-bit mode, the DAC data can be right-aligned or left- aligned.When the DAC is configured in 8-bit mode, the DAC data can be right-aligned.The DAC output channel has 2, with independent converter.
Page 239: Table 10-1 Dac Pins
Figure 10-1 Block diagram of a DAC channel EXTI_9 DAC CTRL register Trigger source Control logic DMA request DAC alignment data holding DATO register register VREF+ VDDA VSSA Table 10-1 DAC pins Name Description Type The positive reference voltage used by the Input, positive analog reference voltage REF+ DAC,2.4V≤...
Page 240: Dac Function Description And Operation Description
DAC function description and operation description 10.3.1 DAC enable Powering on the DAC can be done by configuring DAC_CTRL. CHxEN = 1. It takes some time for t to open WAKEUP the DAC. 10.3.2 DAC output buffer. By configuring DAC_CTRL.BxEN to disable or enable the output buffer of DAC, if the output buffer is enable, the output impedance is reduced, the driving ability is enhanced, and the external load can be driven without the external operational amplifier.
Page 241: Figure 10-2 Data Format When Dac Independent Output
Figure 10-2 Data format when DAC independent output 8-bit right aligned 12-bit left aligned 12-bit right aligned When the DAC outputs synchronously, there are 3 cases: • When the configuration data is written to the DAC_DR12DCH register, the DAC1 data is written to DAC_DR12DCH [11:0] (Actually stored in the register DACCH1D [11:0] bits, DACCH1D is the internal data storage register), the DAC2 data is written to DAC_DR12DCH [27:16] (Actually stored in the register DACCH2D [11:0] bits, DACCH2D is the internal data storage register).
Page 242: Dac Trigger
Figure 10-3 Data format for DAC sync output 8-bit right aligned 12-bit left aligned 12-bit right aligned Master ADC Slave ADC 10.3.4 DAC trigger Configure DAC_CTRL. TEN = 1 enables the external trigger of the DAC, and DAC_CTRL.TxSEL [2:0] is configured to select an external triggering event as the external triggering source for the DAC.
Page 243: Dac Conversion
data of the aligned data hold register will be transmitted to the DAC_DATOx register. Note: 1. Do not change the DAC_CTRL.TxSEL[2:0] bit when the DAC is enabled. 2. It takes 1 APB1 clock cycle for the data of the aligned data holding register to be transferred to the DAC_DATOx register when triggered by software..
Page 244: Noise
with the data hold register is then transferred to the DAC_DATOx register. When the dual DAC mode is turned on, only one DMA is needed to transmit data, so only one DAC is used to turn on the DMA function, and two DMA requests will appear when two DACs are turned on. Note: DMA requests for DAC have no accumulative function, and when the second external trigger occurs before the response to the first external trigger, the second DMA request cannot be processed and there is no error reporting mechanism.
Page 245: Triangular Wave Generation
Figure 10-6 DAC conversion with LFSR waveform generation (enable software trigger) APB1_CLK SWTRIG 0x00 DACCHxD DATOx 0xD55 0xAAA Note: The DAC is configured to trigger to generate noise. 10.3.9 Triangular wave generation The DAC can generate a triangle wave. The triangle wave function can be turned on by configuring DAC_CTRL.WxEN[1:0] as "10", and the amplitude of the triangle wave can be selected by configuring DAC_CTRL.MAxSEL[3:0].
Page 246: Dac Dual-Channel Conversion
Figure 10-8 DAC conversion with trigonometry generation (enable software trigger) APB1_CLK SWTRIG 0xABE DACCHxD DATOx 0xABF 0xABE 0xAC0 Note: 1. Only when the DAC is configured to trigger can the triangle wave be generated 2. DAC_CTRL.MAxSEL[3:0] cannot be set after DAC is enabled. DAC dual-channel conversion The two channels of the DAC can work independently or at the same time.
Page 247: Independent Triggers That Generate Different Noises
• Configure DAC_CTRL.T1SEL[2:0] and DAC_CTRL.T2SEL[2:0] as different values to select different trigger sources. • Configure DAC_CTRL.W1EN[1:0] and DAC_CTRL.W2EN[1:0] as “01” to select noise generation enable. • Configure DAC_CTRL.MA1SEL3:0] and DAC_CTRL.MA2SEL3:0] to the same value to get the same LFSR register mask bit. •...
Page 248: Independent Trigger To Generate Different Triangle Waves
wave amplitude. • Put the data to be converted into the corresponding alignment data holding register. When the DAC1 trigger event occurs, the triangular wave amplitude value of DAC1 is added to the corresponding data holding register value. The added value is transferred to the register DAC_DATO1 after a delay of 3 APB1 clock cycles, and the counter value of the triangular wave of DAC1 will be updated at this time.
Page 249: Synchronous Trigger Without Waveform Generator
10.4.7 Synchronous trigger without waveform generator The configuration process is as follows: • Configure DAC_CTRL.T1EN and DAC_CTRL.T2EN to enable trigger enable of DAC1 and DAC2. • Configure DAC_CTRL.T1SEL[2:0] and DAC_CTRL.T2SEL[2:0] to be the same value to select the same trigger source. •...
Page 250: Synchronous Trigger To Generate The Same Triangle Wave
holding register. The added value is transferred to register DAC_DATO1 after a delay of 3 APB1 clock cycles, and the counter value of LFSR register 1 will be updated at this time; LFSR The counter value of register 2 is added to the value of the corresponding data holding register.
Page 251: Dac Register
DAC register 10.5.1 DAC registers overview Table 10-3 DAC registers overvie Offset Register DAC_CTRL 000h Reserved Reserved Reset Value DAC_SOTTR 004h Reserved Reset Value DAC_DR12CH1 DACCH1D[11:0] 008h Reserved Reset Value DAC_DL12CH1 DACCH1D[11:0] 00Ch Reserved Reserved Reset Value DAC_DR8CH1 DACCH1D[7:0] 010h Reserved Reset Value DAC_DR12CH2...
Page 252 Bit field Name Description The bit is set to 1 and cleared by the software. 0: Disable DMA for the DAC2; 1: Enable the DMA function of the DAC2. 27:24 MA2SEL[3:0] DAC2 shield/amplitude selector. These bits are configured by software to set the LFSR shielding bits for the noise function and the amplitude of the triangular wave.
Page 253 Bit field Name Description This bit is set to 1 and cleared by the software to enable/disable the DAC2. 0: Disable the DAC2; 1: Enable the DAC2. 15:13 Reserved Reserved, the reset value must be maintained. DMA1EN The DMA function of the DAC1 is enabled The bit is set to 1 and cleared by the software.
Page 254: Dac Software Trigger Register (Dac_Sottr)
Bit field Name Description This bit is set to 1 and cleared by the software to enable/disable the DAC1's output buffer. 0: Disable the DAC1 output buffer; 1: Enable the DAC1 output buffer. CH1EN DAC1 on This bit is set to 1 and cleared by the software to enable/disable the DAC2. 0: Disable the DAC1;...
Page 255: Bit Left Aligned Data Hold Register For Dac1 (Dac_Dl12Ch1)
Bit field Name Description 31:12 Reserved Reserved, the reset value must be maintained. 11:0 DACCH1D[11:0] 12-bit right- aligned data for DAC1 The bits are configured by the software and the DAC1 converts the data. 10.5.5 12 bit left aligned data hold register for DAC1 (DAC_DL12CH1) Offset address: 0x0c Reset value: 0x0000 0000 Bit field...
Page 256: Bit Right Aligned Data Hold Register For Dac2 (Dac_Dr12Ch2)
10.5.7 12 bit right aligned data hold register for DAC2 (DAC_DR12CH2) Offset address: 0x14 Reset value: 0x0000 0000 Bit field Name Description 31:12 Reserved Reserved, the reset value must be maintained. 11:0 DACCH2D[11:0] 12-bit right- aligned data for DAC2 The bits are configured by the software and the DAC2 converts the data. 10.5.8 12 bit left aligned data hold register for DAC2 (DAC_DL12CH2) Offset address: 0x18 Reset value: 0x0000 0000...
Page 257: Bit Right Aligned Data Hold Register For Dual Dac (Dac_Dr12Dch)
Bit field Name Description 31:8 Reserved Retained, the reset value must be maintained. DACCH2D[7:0] 8-bit right- aligned data for DAC2 The bits are configured by the software and the DAC2 converts the data. 10.5.10 12 bit right aligned data hold register for dual DAC (DAC_DR12DCH) Offset address: 0x20 Reset value: 0x0000 0000 Bit field...
Page 258: Bit Right Aligned Data Hold Register For Dual Dac (Dac_Dr8Dch)
10.5.12 8 bit right aligned data hold register for dual DAC (DAC_DR8DCH) Offset address: 0x28 Reset value: 0x0000 0000 Bit field Name Description 31:16 Reserved Retained, the reset value must be maintained. 15:8 DACCH2D[7:0] 8-bit right- aligned data for DAC2 The bits are configured by the software and the DAC2 converts the data.
Page 259 Reserved Reserved DACCHDO[11:0] Bit field Name Description 31:12 Reserved Retained, the reset value must be maintained. 11:0 DACCH2DO[11:0] DAC2 data output. These bits are read-only and represent the output data of the DAC2. 259 / 816...
Page 260: Advanced-Control Timers (Tim1 And Tim8)
Advanced-control timers (TIM1 and TIM8) TIM1 and TIM8 introduction The advanced control timers (TIM1 and TIM8) is mainly used in the following occasions: counting the input signal, measuring the pulse width of the input signal and generating the output waveform, etc. Advanced timers have complementary output function with dead-time insertion and break function.
Page 261: Tim1 And Tim8 Function Description
Figure 11-1 Block diagram of TIM1 and TIM8 Polarity TIMx_BKIN selection Clock failure event From clock controller CSS(Clock Security System) PVD abnormal (Power supply voltage detection) LOOKUP(Core Hardfault) Comparator polarity CK_TIM18 from RCC Internal clock(CK_INT) To another timer, ADC, Polarity selection ETRF TRGO Edge detector...
Page 262: Prescaler Description
Prescaler description The TIMx_PSC register consists of a 16-bit counter that can be used to divide the counter clock frequency by any factor between 1 and 65536. It can be changed on the fly as it is buffered. The prescaler value is only taken into account at the next update event.
Page 263: Figure 11-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
To avoid updating the shadow registers when new values are written to the preload registers, you can disable the update by setting TIMx_CTRL1.UPDIS=1. When an update event occurs, the counter will still be cleared and the prescaler counter will also be set to 0 (but the prescaler value will remain unchanged).
Page 264: Figure 11-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 11-4 Timing diagram of the , update event when ARPEN=0/1 up-counting ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 265: Down-Counting Mode
Down-counting mode In down-counting mode, the counter will decrement from the value of the register TIMx_AR to 0, then restart from the auto-reload value and generate a counter underflow event. The process of configuring update events and updating registers in down-counting mode is the same as in up-counting mode, see 11.3.2.1.
Page 266: Figure 11-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N
or using a slave mode controller). In this case, the counter restarts from 0, as does the prescaler's counter. Please note: if the update source is a counter overflow, auto-reload update before reloading the counter. Figure 11-6 Timing diagram of the Center-aligned, internal clock divided factor =2/N Internal clock CK_PSC divided by 2...
Page 267: Counter Underflow
Counter underflow CNTEN CK_PSC Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Write a new value in TIMx_AR Auto-reload active register Counter CNTEN overflow...
Page 268: Figure 11-8 Repeat Count Sequence Diagram In Down-Counting Mode
The repetition counter is decremented: • In the up-counting mode, each time the counter reaches the maximum value, an overflow occurs. • In down-counting mode, each time the counter decrements to the minimum value, an underflow occurs. • In center-aligned mode, each time the counter overflows or underflows. Its repetition rate is defined by the value of the TIMx_REPCNT register.
Page 269: Figure 11-9 Repeat Count Sequence Diagram In Up-Counting Mode
Figure 11-9 Repeat count sequence diagram in up-counting mode CK_PSC CNTEN Timer clock = CK_CNT 01 ... 35 00 01 ... 35 36 00 01 ... 35 00 01 ... 35 36 00 01 ... 35 36 CNT_REG 36 00 00 01 Underflow Overflow...
Page 270: Clock Selection
11.3.4 Clock selection • The internal clock of Advanced-control timers ：CK_INT • Two kinds of external clock mode : − external input pin − external trigger input ETR • Internal trigger input (ITRx): one timer is used as a prescaler for another timer. Internal clock source (CK_INT) When the TIMx_SMCTRL.SMSEL is equal to “000”, the slave mode controller is disabled.
Page 271: Figure 11-12 Ti2 External Clock Connection Example
External clock source mode 1 Figure 11-12 TI2 external clock connection example Filter (TIMx_CCMOD1.ICF[3:0]) Edge Detector TIMx_SMCTRL. CK_INT rising TSEL[2:0] Internal clock mode Polarity Selection （ TIMx_CCEN.CC2P ） ITRx TRGI rising TI1_ED External clock mode 1 TI1FP1 TI2FP2 CK_PSC ETRF ETRF rising External clock mode 2 TI2F rising or falling...
Page 272: Figure 11-13 Control Circuit In External Clock Mode 1
Figure 11-13 Control circuit in external clock mode 1 CNTEN Timer clock = CK_CNT=CK_PSC Counter register TITF Write TITF=0 External clock source mode 2 This mode is selected by TIMx_SMCTRL .EXCEN equal to 1. The counter can count on every rising or falling edge of the external trigger input ETR.
Page 273: Capture/Compare Channels
• External clock mode 2 is selected by setting TIMx_SMCTRL .EXCEN equal to ‘1’ • Turn on the counter by setting TIMx_CTRL1. CNTEN equal to ‘1’ The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to the counter is due to a resynchronization circuit on the ETRP signal.
Page 274: Figure 11-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
Figure 11-16 Capture/compare channel (example: channel 1 input stage) From slave mode controller TI2FP1 Divider /1,/2,/4,/8 TI2F_Rising From channel 2 IC1PSC TI1FP1 TI2F_Falling TIMx_CCMOD1. Polarity Selection IC1PSC[1:0] TIMx_CCMOD1.CC1SEL[3:0] TIMx_CCEN.CC2P TIMx_CCEN.CC1EN Filter Down counter TIMx_CCMOD1.IC1F[ Edge Detector 3:0] TI1F_Rising TI1F To the slave TI1F_Falling mode controller Polarity Selection...
Page 275: Figure 11-17 Capture/Compare Channel 1 Main Circuit
Figure 11-17 Capture/compare channel 1 main circuit CC1SEL[1] CC1SEL[0] Input IC1PSC CC1EN mode Read CCDAT1H TIM1_EVTGEN.CC1GN Read CCDAT1L Read in APB Bus progress MCU Peripheral interface 16 bit High 8-bits Capture/ Capture/ transfer compare compare Counter preload register shadow register Low 8-bits Output Comparator...
Page 276: Input Capture Mode
Figure 11-18 Output part of channelx (x= 1,2,3, take channel 1 as example) To the master mode controller Output enable Output enable circuit circuit Polarity Seletion TIM1_CCEN.CC1NEN ETRF Ocref_clr_int TIM1_CCEN. TIM1_CCEN.CC1EN TIM1_CCEN.CC1NEN CC1P TIM1_CCEN.CC1EN TIM1_BKDT.MOEN TIM1_BKDT.MOEN CNT=CCR1 TIM1_BKDT.OSSI TIM1_BKDT.OSSI OC1REFC TIM1_BKDT.OSSR TIM1_BKDT.OSSR CNT>CCR1...
Page 277: Pwm Input Mode
the TIMx_CCDATx register. The overcapture flag TIMx_STS.CCxOCF is set equal to 1 when the counter value is captured in the TIMx_CCDATx register and TIMx_STS.CC1ITF is already pulled high. Unlike the former, TIMx_STS.CCxOCF is cleared by writing 0 to it. To achieve a rising edge of the TI1 input to capture the counter value into the TIMx_CCDAT1 register, the configuration flow is as follows: •...
Page 278: Forced Output Mode
• Configure TIMx_SMCTRL.TSEL=101 to select Filtered timer input 1 (TI1FP1) as valid trigger input. • Configure TIMx_SMCTRL.SMSEL=100 to configure the slave mode controller to reset mode. • Configure TIMx_CCEN. CC1EN=1 and TIMx_CCEN.CC2EN=1 to enable capture. Figure 11-20 PWM input mode timing TIMx_CNT 0004 0000...
Page 279 are as follow: • TIMx_CCMODx.OCxMD is for output compare mode, and TIMx_CCEN.CCxP is for output polarity. When the compare matches, if set TIMx_CCMODx.OCxMD=000, the output pin will keep its level;if set TIMx_CCMODx.OCxMD=001, the output pin will be set active;if set TIMx_CCMODx.OCxMD=010, the output pin will be set inactive;if set TIMx_CCMODx.OCxMD=011, the output pin will be set to toggle.
Page 280: Pwm Mode
Figure 11-21 Output compare mode, toggle on OC1 TIM1_CNT 0069 006A 006B 8801 8800 TIM1_CCDAT1 006A 8801 Write 8801h in CCDAT1 register OC1REF=OC1 Match detected on CCDAT1 Interrupt generated if enabled 11.3.10 PWM mode User can use PWM mode to generate a signal whose duty cycle is determined by the value of the TIMx_CCDATx register and whose frequency is determined by the value of the TIMx_AR register.
Page 281: Figure 11-22 Center-Aligned Pwm Waveform (Ar=8)
mode 1, the compare flag is set when the counter counts down corresponding to TIMx_CTRL1. CAMSEL=01. Figure 11-22 Center-aligned PWM waveform (AR=8) Counter register OCXREF CCDATx=0 CAMSEL=01 CCxITF CAMSEL=10 CAMSEL=11 OCXREF CCDATx=4 CAMSEL=01 CAMSEL=10 CCxITF CAMSEL=11 OCXREF CCDATx=7 CAMSEL=10或11 CCxITF OCXREF CAMSEL=01 CCDATx=8...
Page 282: Figure 11-23 Edge-Aligned Pwm Waveform (Apr=8)
before starting the counter, and not writing the counter while it is running. PWM edge-aligned mode There are two kinds of configuration in edge-aligned mode, up-counting and down-counting. • Up-counting User can set TIMx_CTRL1.DIR=0 to make counter counts up. Here is an example for PWM mode1. When TIMx_CNT <...
Page 283: One-Pulse Mode
counter = CCDATx shadow register = 0 and OCxREF = '0', no compare event will be generated. 11.3.11 One-pulse mode In the one-pulse mode (ONEPM), a trigger signal is received, and a pulse t with a controllable pulse width is PULSE generated after a controllable delay t .
Page 284: Clearing The Ocxref Signal On An External Event
select PWM2 mode; 6. Wait for an external trigger event on TI2, and a one pulse waveform will be output on OC1; Special case: OCx fast enable: In one-pulse mode, an edge is detected through the TIx input, and triggers the start of the counter to count to the comparison value and then output a pulse.
Page 285: Complementary Outputs With Dead-Time Insertion
Figure 11-24 Clearing the OCxREF of TIMx ETRF (CCDATx) Counter(CNT) OCxREF (OCxCEN=＇0＇) OCxREF (OCxCEN=＇１＇) still ETRF becomes ETRF high high 11.3.13 Complementary outputs with dead-time insertion Advanced-control timer can output two complementary signals, and manage the switching-off and switching-on of outputs.
Page 286: Figure 11-25 Complementary Output With Dead-Time Insertion
Figure 11-25 Complementary output with dead-time insertion OCxREF Complementary output with dead-time insertion Delay OCxN Delay Dead-time waveform with delay greater OCxREF than the negative pulse Delay OCxN Dead-time waveform OCxREF with delay larger than the positive pulse OCxN Delay User can set TIMx_BKDT.DTGN to programme the dead-time delay for each of the channels.
Page 287: Break Function
11.3.14 Break function The output enable signals and inactive levels will be modified when setting the corresponding control bits when using the break function. However, the output of OCx and OCxN cannot at the active level at the same time no matter when, that is, (CCxP^OIx) ^(CCxNP^OIxN)!=0.
Page 288: Debug Mode
will remain high. If it was low, it will become high when TIMx_CCEN.CCxEN or TIMx_CCEN.CCxNEN is high. • If TIMx_DINTEN.BIEN=1, when TIMx_STS.BITF=1, an interrupt will be generated. • If user set TIMx_BKDT.AOEN, the TIMx_BKDT.MOEN will be set automatically when the next UEV happened.
Page 289: Timx And External Trigger Synchronization
see 29.4.3. 11.3.16 TIMx and external trigger synchronization TIMx timers can be synchronized by a trigger in slave modes (reset, trigger and gated). Slave mode: Reset mode In reset mode, the trigger event can reset the counter and the prescaler updates the preload registers TIMx_AR, TIMx_CCDATx, and generates the update event UEV (TIMx_CTRL1.UPRS=0).
Page 290: Slave Mode: Gated Mode
TIMx_CCEN.CC2P=0); 2. Select from mode to trigger mode (TIMx_SMCTRL.SMSEL=110), select TI2 for trigger input (TIMx_SMCTRL.TSEL=110); When TI2 detects a rising edge, the counter starts counting, and the trigger flag is set (TIMx_STS.TITF=1); The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
Page 291: Figure 11-29 Control Circuit In Gated Mode
Figure 11-29 Control circuit in Gated mode Counter clock=CK_CNT=CK_PSC Counter register 30 31 32 33 36 37 38 CNTEN TITF Clear TITF Slave mode: Trigger Mode + External Clock Mode 2 In reset mode, trigger mode and gate control mode, the counter clock can be selected as external clock mode 2, and the ETR signal is used as the external clock source input.
Page 292: Timer Synchronization
Figure 11-30 Control circuit in Trigger Mode + External Clock Mode2 Counter clock=CK_CNT=CK_PSC Counter register CNTEN TITF 11.3.17 Timer synchronization All TIM timers are internally connected for timer synchronization or chaining. For more details, see 12.3.14. 11.3.18 6-step PWM generation In order to modify the configuration of all channels at the same time, the configuration of the next step can be set in advance (the preloaded bits are OCxMD, CCxEN and CCxNEN).
Page 293: Encoder Interface Mode
Figure 11-31 6-step PWM generation, COM example (OSSR=1) (CCRx) Counter (CNT) OCxREF write COM=1 COM event CCxEN=1 write OCxMD=100 CCxEN=1 CCxNEN=0 CCxNEN=0 OCxMD=100(forced inactive) OCxMD=100 OCxN write CCxNEN=0 CCxEN=1 和OCxMD=100 CCxNEN=0 CCxEN=1 OCxMD=100(forced inactive) CCxNEN=0 OCxMD=100 OCxN write CCxNEN=1 CCxEN=1 和OCxMD=101 CCxEN=0 CCxNEN=0...
Page 294: Figure 11-32 Example Of Counter Operation In Encoder Interface Mode
Active edge (TI1FP1 forTI2, Rising Falling Rising Falling TI2FP2 for TI1) Counting only at TI1 High Counting down Counting up Don't count Don't count Counting up Counting down Don't count Don't count Counting only at TI2 High Don't count Don't count Counting up Counting down Don't count...
Page 295: Figure 11-33 Encoder Interface Mode Example With Ic1Fp1 Polarity Inverted
Figure 11-33 Encoder interface mode example with IC1FP1 polarity inverted forward jitter backward jitter Counter down 295 / 816...
Page 296: Interfacing With Hall Sensor
11.3.20 Interfacing with Hall sensor Connect the Hall sensor to the three input pins (CC1, CC2 and CC3) of the timer, and then select the XOR function to pass the inputs of TIMx_CH1, TIMx_CH2 and TIMx_CH3 through the XOR gate as the output of TI1 to channel 1 for capture signal.
Page 297: Advanced-Control
Figure 11-34 Example of Hall sensor interface Interfacing timer Counter(CNT) (CCDAT2) CCDAT1 TRGO=OC2REF Advanced-control timers(TIM1&TIM8) OC1N OC2N OC3N Write CCxEN、CCxNEN and OCxMD for next step 297 / 816...
Page 298: Timx Register (X=1, 8)
TIMx register (x=1, 8) For abbreviations used in registers, see section 1.1. These peripheral registers can be operated as half word (16-bits) or one word (32-bits). 11.4.1 Register Overview Table 11-2 Register map and reset value Offset Register TIMx_CTRL1 000h Reset Value TIMx_CTRL2 004h...
Page 299: Control Register 1 (Timx_Ctrl1)
TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC PSC[15:0] 028h Reserved Reset Value TIMx_AR AR[15:0] 02Ch Reserved Reset Value TIMx_REPCNT REPCNT[7:0] 030h Reserved Reset Value TIMx_CCDAT1 CCDAT1[15:0] 034h Reserved Reset Value TIMx_CCDAT2 CCDAT2[15:0] 038h Reserved Reset Value TIMx_CCDAT3 CCDAT3[15:0] 03Ch Reserved Reset Value TIMx_CCDAT4 CCDAT4[15:0]...
Page 300 Bit field Name Description 31:18 Reserved Reserved, the reset value must be maintained PBKPEN PVD as BKP enable 0: Disable 1: Enable Note:Before operating this bit, the extended mode of the chip must be turned on (set PWR_CTRL3.EXMODE) LBKPEN LockUp as BKP enable 0: Disable 1: Enable Note:Before operating this bit, the extended mode of the chip must be turned on (set...
Page 301: Control Register 2 (Timx_Ctrl2)
Bit field Name Description 11: Center-aligned mode 3. The counter counts in center-aligned mode, and the output compare interrupt flag bit is set to 1 when up-counting or down-counting. Note: Switching from edge-aligned mode to center-aligned mode is not allowed when the counter is still enabled (TIMx_CTRL1.CNTEN = 1).
Page 302 Bit field Name Description 31:19 Reserved Reserved, the reset value must be maintained Output idle state 6 (OC6 output). See TIMx_CTRL2.OI1 bit. Reserved Reserved, the reset value must be maintained Output idle state 5 (OC5 output). See TIMx_CTRL2.OI1 bit. Reserved Reserved, the reset value must be maintained Output idle state 4 (OC4 output).
Page 303: Slave Mode Control Register (Timx_Smctrl)
Bit field Name Description 011: Compare pulse - Triggers the output to send a positive pulse (TRGO) when the TIMx_STS.CC1ITF is to be set (even if it is already high), when a capture or a comparison succeeds. 100: Compare - OC1REF signal is used as the trigger output (TRGO). 101: Compare - OC2REF signal is used as the trigger output (TRGO).
Page 304 Bit field Name Description Note 1: When external clock mode 1 and external clock mode 2 are enabled at the same time, the input of the external clock is ETRF. Note 2: The following slave modes can be used simultaneously with external clock mode 2: reset mode, gated mode and trigger mode;...
Page 305: Dma/Interrupt Enable Registers (Timx_Dinten)
Bit field Name Description TSEL[2:0] Trigger selection These 3 bits are used to select the trigger input of the synchronous counter. 000: Internal trigger 0 (ITR0) 100: TI1 edge detector (TI1F_ED) 001: Internal trigger 1 (ITR1) 101: Filtered timer input 1(TI1FP1) 010: Internal trigger 2 (ITR2) 110: Filtered timer input 2 (TI2FP2) 011: Internal trigger 3 (ITR3) 111: External triggered Input (ETRF) For more details on ITRx, see Table 11-3 below.
Page 306 Reset value: 0x0000 Bit field Name Description Reserved Reserved, the reset value must be maintained TDEN Trigger DMA request enable 0: Disable trigger DMA request 1: Enable trigger DMA request COMDEN COM DMA request enable 0: Disable COM DMA request 1: Enable COM DMA request CC4DEN Capture/Compare 4 DMA request enable...
Page 307: Status Registers (Timx_Sts)
Bit field Name Description CC2IEN Capture/Compare 2 interrupt enable 0: Disable capture/compare 2 interrupt 1: Enables capture/compare 2 interrupts CC1IEN Capture/Compare 1 interrupt enable 0: Disable capture/compare 1 interrupt 1: Enables capture/comparing 1 interrupt UIEN Update interrupt enable 0: Disable update interrupt 1: Enables update interrupt 11.4.6 Status registers (TIMx_STS) Offset address: 0x10...
Page 308 Bit field Name Description BITF Break interrupt flag This bit is set by hardware once the brake input is active. This bit is cleared by software when the brake input becomes inactive. 0: No break event occurred 1: An active level has been detected TITF Trigger interrupt flag This bit is set by hardware when an active edge is detected on the TRGI input when the slave mode...
Page 309: Event Generation Registers (Timx_Evtgen)
Bit field Name Description – When TIMx_CTRL1.UPRS = 0, TIMx_CTRL1.UPDIS = 0, and set the TIMx_EVTGEN.UDGN bit by software to reinitialize the CNT. – When TIMx_CTRL1.UPRS = 0, TIMx_CTRL1.UPDIS = 0, and the counter CNT is reinitialized by the trigger event. (See TIMx_SMCTRL Register description) This bit is cleared by software.
Page 310: Capture/Compare Mode Register 1 (Timx_Ccmod1)
Bit field Name Description CC1GN Capture/Compare 1 generation This bit can generate a capture/compare event when set by software. This bit is automatically cleared by hardware. When the corresponding channel of CC1 is in output mode: The TIMx_STS.CC1ITF flag will be pulled high, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be generated.
Page 311 Bit field Name Description CC2SEL[1:0] Capture/compare 2 selection These bits are used to select the input/output and input mapping of the channel 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 312 Bit field Name Description OC1FEN Output Compare 1 fast enable This bit is used to speed up the response of the CC output to the trigger input event. 0: CC1 behaves normally depending on the counter and CCDAT1 values, even if the trigger is ON.
Page 313: Capture/Compare Mode Register 2 (Timx_Ccmod2)
Bit field Name Description 0101: f /2, N = 8 SAMPLING 0110: f /4, N = 6 SAMPLING 0111: f /4, N = 8 SAMPLING 1000: f /8, N = 6 SAMPLING 1001: f /8, N = 8 SAMPLING 1010: f /16, N = 5 SAMPLING 1011: f...
Page 314 Bit field Name Description CC4SEL[1:0] Capture/Compare 4 selection These bits are used to select the input/output and input mapping of the channel 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 315: Capture/Compare Enable Registers (Timx_Ccen)
Bit field Name Description CC3SEL[1:0] Capture/compare 3 selection These bits are used to select the input/output and input mapping of the channel 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped to TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped to TRC.
Page 316 Bit field Name Description See TIMx_CCEN.CC1P description. CC3EN Capture/Compare 3 output enable See TIMx_CCEN.CC1EN description. CC2NP Capture/Compare 2 complementary output polarity See TIMx_CCEN.CC1NP description. CC2NEN Capture/Compare 2 complementary output enable See TIMx_CCEN.CC1NEN description. CC2P Capture/Compare 2 output polarity See TIMx_CCEN.CC1P description. CC2EN Capture/Compare 2 output enable See TIMx_CCEN.CC1EN description.
Page 317: Table 11-4 Output Control Bits Of Complementary Ocx And Ocxn Channels With Break Function
Bit field Name Description 0: Disable capture 1: Enable capture Table 11-4 Output control bits of complementary OCx and OCxN channels with break function Control bits Output state MOEN OSSI OSSR CCxEN CCxNEN OCx Output state OCxN Output state Output disabled（not driven by timer） Output disabled（not driven by timer）...
Page 318: Counters (Timx_Cnt)
11.4.11 Counters (TIMx_CNT) Offset address: 0x24 Reset value: 0x0000 Bit field Name Description 15:0 CNT[15:0] Counter value 11.4.12 Prescaler (TIMx_PSC) Offset address: 0x28 Reset value: 0x0000 Bit field Name Description 15:0 PSC[15:0] Prescaler value Counter clock f / (PSC [15:0] +1). CK_CNT CK_PSC Each time an update event occurs, the PSC value is loaded into the active prescaler register.
Page 319: Capture/Compare Register 1 (Timx_Ccdat1)
Reset value: 0x0000 Bit field Name Description 15:8 Reserved Reserved, the reset value must be maintained REPCNT[7:0] Repetition counter value Repetition counter is used to generate the update event or update the timer registers only after a given number (N+1) cycles of the counter, where N is the value of TIMx_REPCNT.REPCNT . The repetition counter is decremented at each counter overflow in up-counting mode, at each counter underflow in down-counting mode or at each counter overflow and at each counter underflow in center-aligned mode.
Page 320: Capture/Compare Register 3 (Timx_Ccdat3)
Bit field Name Description 15:0 CCDAT2[15:0] Capture/Compare 2 values ◼ CC2 channel is configured as output: CCDAT2 contains the value to be compared to the counter TIMx_CNT, signaling on the OC2 output. If the preload feature is not selected in TIMx_CCMOD1.OC2PEN bit, the written value is immediately transferred to the active register.
Page 321: Break And Dead-Time Registers (Timx_Bkdt)
Bit field Name Description 15:0 CCDAT4[15:0] Capture/Compare 4 value ◼ CC4 channel is configured as output: CCDAT4 contains the value to be compared to the counter TIMx_CNT, signaling on the OC4 output. If the preload feature is not selected in TIMx_CCMOD2.OC4PEN bit, the written value is immediately transferred to the active register.
Page 322 Bit field Name Description Note: Any write to this bit requires an APB clock delay to take effect. BKEN Break enable 0: Disable brake input (BRK and CCS clock failure events) 1: Enable brake input (BRK and CCS clock failure events) Note: Any write to this bit requires an APB clock delay to take effect.
Page 323: Dma Control Register (Timx_Dctrl)
Bit field Name Description DTGN [7:0] Dead-time Generator These bits define the dead-time duration between inserted complementary outputs. The relationship between the DTGN value and the dead time is as follows: DTGN[7:5] = 0xx: dead time = DTGN[7:0] × (t DTGN[7:5] = 10x: dead time =(64+DTGN[5:0]) ×...
Page 324: Dma Transfer Buffer Register (Timx_Daddr)
Bit field Name Description 10010：TIMx_DCTRL 11.4.21 DMA transfer buffer register (TIMx_DADDR) Offset address: 0x4C Reset value: 0x0000 Bit field Name Description 15:0 BURST[15:0] DMA access buffer. When a read or write operation is assigned to this register, the register located at the address range (DMA base address + DMA burst length ×...
Page 325: Capture/Compare Register 5 (Timx_Ccdat5)
Bit field Name Description OC6CEN Output compare 6 clear enable 14:12 OC6MD[2:0] Output compare 6 mode OC6PEN Output compare 6 preload enable OC6FEN Output compare 6 fast enable Reserved Reserved, the reset value must be maintained OC5CEN Output compare 5 clear enable OC5MD[2:0] Output compare 5 mode OC5PEN...
Page 326 Bit field Name Description 15:0 CCDAT6[15:0] Capture/Compare 6 value • CC6 channel can only configured as output: CCDAT6 contains the value to be compared to the counter TIMx_CNT, signaling on the OC6 output. If the preload feature is not selected in TIMx_CCMOD3.OC6PEN bit, the written value is immediately transferred to the active register.
Page 327: General-Purpose Timers (Tim2, Tim3, Tim4 And Tim5)
General-purpose timers (TIM2, TIM3, TIM4 and TIM5) General-purpose timers introduction The general-purpose timers (TIM2, TIM3, TIM4 and TIM5) is mainly used in the following occasions: counting the input signal, measuring the pulse width of the input signal and generating the output waveform, etc. Main features of General-purpose timers •...
Page 328: General-Purpose Timers Description
Figure 12-1 Block diagram of TIMx（x=2, 3 ,4 and 5） TIMxCLK from RCC Internal clock(CK_INT) To another timer, ADC, Polarity selection ETRF TRGO Edge detector Trigger controller TIMx_ETR pin Prescaler Input filter Reset, enable, COMP_TIM_ up/down, count OCREFCLR Slave mode controller TRGI TI1F_ED...
Page 329: Counter Mode
factor between 1 and 65536. It can be changed on the fly as it is buffered. The prescaler value is only taken into account at the next update event. Figure 12-2 Counter timing diagram with prescaler division change from 1 to 4 CNTEN CK_PSC Timer Clock = CK_CNT...
Page 330: Figure 12-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
prescaler value will remain unchanged). The figure below shows some examples of the counter behavior and the update flags for different division factors in the up-counting mode. Figure 12-3 Timing diagram of up-counting. The internal clock divider factor = 2/N Internal clock divided by 2 CNTEN...
Page 331: Figure 12-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 12-4 Timing diagram of the up-counting, update event when ARPEN=0/1 ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 332: Figure 12-5 Timing Diagram Of The Down-Counting, Internal Clock Divided Factor = 2/N
Down-counting mode In down-counting mode, the counter will decrement from the value of the register TIMx_AR to 0, then restart from the auto-reload value and generate a counter underflow event. The process of configuring update events and updating registers in down-counting mode is the same as in up-counting mode, see 12.3.2.1.
Page 333: Figure 12-6 Timing Diagram Of The Center-Aligned, Internal Clock Divided Factor =2/N
or using a slave mode controller). In this case, the counter restarts from 0, as does the prescaler's counter. Please note: if the update source is a counter overflow, auto-reload update before reloading the counter. Figure 12-6 Timing diagram of the Center-aligned, internal clock divided factor =2/N Internal clock CK_PSC divided by 2...
Page 334: Clock Selection
Figure 12-7 A center-aligned sequence diagram that includes counter overflows and underflows (ARPEN = 1) Counter underflow CNTEN CK_PSC Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Write a new value in TIMx_AR...
Page 335: Figure 12-8 Control Circuit In Normal Mode, Internal Clock Divided By 1
− external trigger input ETR • Internal trigger input (ITRx): one timer is used as a prescaler for another timer. Internal clock source (CK_INT) When the TIMx_SMCTRL.SMSEL is equal to “000”, the slave mode controller is disabled. The three control bits (TIMx_CTRL1.CNTEN、TIMx_CTRL1.
Page 336: Figure 12-9 Ti2 External Clock Connection Example
External clock source mode 1 Figure 12-9 TI2 external clock connection example Filter (TIMx_CCMOD1.ICF[3:0]) Edge Detector TIMx_SMCTRL. CK_INT rising TSEL[2:0] Internal clock mode Polarity Selection （ TIMx_CCEN.CC2P ） ITRx TRGI rising TI1_ED External clock mode 1 TI1FP1 TI2FP2 CK_PSC ETRF ETRF rising External clock mode 2 TI2F rising or falling...
Page 337: Figure 12-10 Control Circuit In External Clock Mode 1
Figure 12-10 Control circuit in external clock mode 1 CNTEN Timer clock = CK_CNT=CK_PSC Counter register TITF Write TITF=0 External clock source mode 2 This mode is selected by TIMx_SMCTRL .EXCEN equal to 1. The counter can count on every rising or falling edge of the external trigger input ETR.
Page 338: Capture/Compare Channels
The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to the counter is due to a resynchronization circuit on the ETRP signal. Figure 12-12 Control circuit in external clock mode 2 CNTEN ETRP ETRF...
Page 339: Figure 12-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
Figure 12-13 Capture/compare channel (example: channel 1 input stage) From slave mode controller TI2FP1 Divider /1,/2,/4,/8 TI2F_Rising From channel 2 IC1PSC TI1FP1 TI2F_Falling TIMx_CCMOD1. Polarity Selection IC1PSC[1:0] TIMx_CCMOD1.CC1SEL[3:0] TIMx_CCEN.CC2P TIMx_CCEN.CC1EN Filter Down counter TIMx_CCMOD1.IC1F[ Edge Detector 3:0] TI1F_Rising TI1F To the slave TI1F_Falling mode controller Polarity Selection...
Page 340: Figure 12-14 Capture/Compare Channel 1 Main Circuit
Figure 12-14 Capture/compare channel 1 main circuit CC1SEL[1] CC1SEL[0] Input IC1PSC CC1EN mode Read CCDAT1H TIM1_EVTGEN.CC1GN Read CCDAT1L Read in APB Bus progress MCU Peripheral interface 16 bit High 8-bits Capture/ Capture/ transfer compare compare Counter preload register shadow register Low 8-bits Output Comparator...
Page 341: Input Capture Mode
Figure 12-15 Output part of channelx （x = 1,2,3,4;take channel 4 as an example） To the master mode controller Output enable Output enable Polarity circuit circuit selection TIM1_CCEN. CC4P Ocref_clr ETRF TIM1_CCEN.CC4EN OC4 REF CNT=CCDAT4 CNT>CCDAT4 Output mode controller TIM1_CCMOD2.OC2M D[2:0] Reads and writes always access preloaded registers when capturing/comparing.
Page 342: Pwm Input Mode
filter duration longer than these 5 clock cycles. When 8 consecutive samples (sampled at f frequency) with the new level are detected, we can validate the transition on TI1. Then configure TIMx_CCMOD1. IC1F to ‘0011’. • By configuring TIMx_CCEN .CC1P=0, select the rising edge as the valid transition polarity on the TI1 channel. •...
Page 343: Forced Output Mode
Figure 12-16 PWM input mode timing TIMx_CNT 0004 0000 0001 0002 0003 0004 0000 TIMx_CCDAT1 0004 0002 TIMx_CCDAT2 IC1 capture IC2 capture IC1 capture IC2 capture Pulse width Period Reset counter measurement measurement Because of only filter timer input 1 (TI1FP1) and filter timer input 2 (TI2FP2) are connected to the slave mode controller, the PWM input mode can only be used with the TIMx_CH1/TIMx_CH2 signals.
Page 344 TIMx_CCMODx.OCxMD=001, the output pin will be set active;if set TIMx_CCMODx.OCxMD=010, the output pin will be set inactive;if set TIMx_CCMODx.OCxMD=011, the output pin will be set to toggle. • Set TIMx_STS.CCxITF. • If user set TIMx_DINTEN.CCxIEN, a corresponding interrupt will be generated. •...
Page 345: Pwm Mode
Figure 12-17 Output compare mode, toggle on OC1 TIM1_CNT 0069 006A 006B 8801 8800 TIM1_CCDAT1 006A 8801 Write 8801h in CCDAT1 register OC1REF=OC1 Match detected on CCDAT1 Interrupt generated if enabled 12.3.9 PWM mode User can use PWM mode to generate a signal whose duty cycle is determined by the value of the TIMx_CCDATx register and whose frequency is determined by the value of the TIMx_AR register.
Page 346: Figure 12-18 Center-Aligned Pwm Waveform (Ar=8)
Figure 12-18 Center-aligned PWM waveform (AR=8) Counter register OCXREF CCDATx=0 CAMSEL=01 CCxITF CAMSEL=10 CAMSEL=11 OCXREF CCDATx=4 CAMSEL=01 CAMSEL=10 CCxITF CAMSEL=11 OCXREF CCDATx=7 CAMSEL=10或11 CCxITF OCXREF CAMSEL=01 CCDATx=8 CAMSEL=10 CCxITF CAMSEL=11 OCXREF CCDATx>8 CAMSEL=01 CCxITF CAMSEL=10 CAMSEL=11 Notes that user should know when using center-aligned mode are as follow: •...
Page 347: Figure 12-19 Edge-Aligned Pwm Waveform (Apr=8)
• Up-counting User can set TIMx_CTRL1.DIR=0 to make counter counts up. Here is an example for PWM mode1. When TIMx_CNT < TIMx_CCDATx, the reference PWM signal OCxREF is high. Otherwise it will be low. If the compare value in TIMx_CCDATx is greater than the auto-reload value, the OCxREF will remains 1. Conversely, if the compare value is 0, the OCxREF will remains 0.
Page 348: One-Pulse Mode
12.3.10 One-pulse mode In the one-pulse mode (ONEPM), a trigger signal is received, and a pulse t with a controllable pulse width is PULSE generated after a controllable delay t . The output mode needs to be configured as output compare mode or PWM DELAY mode.
Page 349: Clearing The Ocxref Signal On An External Event
Special case: OCx fast enable: In one-pulse mode, an edge is detected through the TIx input, and triggers the start of the counter to count to the comparison value and then output a pulse. These operations limit the minimum delay t that can be achieved.
Page 350: Debug Mode
12.3.12 Debug mode When the microcontroller is in debug mode (the Cortex-M4 core halted), depending on the DBG_CTRL.TIMx_STOP configuration in the DBG module, the TIMx counter can either continue to work normally or stop. For more details, see 29.4.3. 12.3.13 TIMx and external trigger synchronization Same as advanced timer.
Page 351: Figure 12-23 Tim2 Gated By Oc1Ref Of Tim1
• Configure TIM2_SMCTRL.SMSEL = ‘111’, the slave mode controller will be configured in external clock mode 1. • Start TIM2 by setting TIM2_CTRL1. CNTEN = ‘1’. • Start TIM1 by setting TIM1_CTRL1. CNTEN = ‘1’. Note: If user select OCx as the trigger output of TIM1 by configuring MMSEL = ‘1xx’, OCx rising edge will be used to drive timer2.
Page 352: Figure 12-24 Tim2 Gated By Enable Signal Of Tim1
counts on the divided internal clock only when TIM1 is enable. Both counters are clocked based on CK_INT via a prescaler divide by 3 is performed (f /3). CK_CNT CK_INT The configuration steps are shown as below • Setting TIM1_CTRL2.MMSEL=’ 001’ to use the enable signal of TIM1 as trigger output •...
Page 353: Figure 12-25 Trigger Tim2 With An Update Of Tim1
Figure 12-25 Trigger TIM2 with an update of TIM1 TIM1 CK_INT TIM2 CNTEN TITF Clear TITF Start 2 timers synchronously using an external trigger In this example, TIM1 is enabled when TIM1's TI1 input rises, and TIM2 is enabled when TIM1 is enabled. To ensure the alignment of counters, TIM1 must be configured in master/slave mode.
Page 354: Encoder Interface Mode
Figure 12-26 Triggers timers 1 and 2 using the TI1 input of TIM1 TIM1 CK_INT CNTEN CK_PSC 02 03 04 05 06 07 08 09 TITF TIM2 CNTEN CK_PSC 01 02 03 04 05 06 07 08 09 TITF 12.3.15 Encoder interface mode The encoder uses two inputs TI1 and TI2 as an interface and the counter counts on every edge change on TI1FP1 or TI2FP2.
Page 355: Figure 12-27 Example Of Counter Operation In Encoder Interface Mode
Active edge (TI1FP1 forTI2, Rising Falling Rising Falling TI2FP2 for TI1) Counting only at TI1 High Counting down Counting up Don't count Don't count Counting up Counting down Don't count Don't count Counting only at TI2 High Don't count Don't count Counting up Counting down Don't count...
Page 356: Interfacing With Hall Sensor
Figure 12-28 Encoder interface mode example with IC1FP1 polarity inverted forward jitter backward jitter Counter down 12.3.16 Interfacing with Hall sensor Please refer to 11.3.20 TIMx register description(x=2, 3 ,4 and 5) For abbreviations used in registers, see section 1.1. These peripheral registers can be operated as half word (16-bits) or one word (32-bits).
Page 357 Offset Register Reset Value TIMx_STS 010h Reset Value TIMx_EVTGEN 014h Reset Value TIMx_CCMOD1 Reset Value 018h TIMx_CCMOD1 Reset Value TIMx_CCMOD2 01Ch Reset Value TIMx_CCMOD2 01Ch Reset Value TIMx_CCEN 020h Reset Value TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC PSC[15:0] 028h Reserved Reset Value TIMx_AR...
Page 358: Control Register 1 (Timx_Ctrl1)
12.4.2 Control register 1 (TIMx_CTRL1) Offset address: 0x00 Reset value: 0x0000 0000 Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained CLRSEL OCxREF clear selection 0: Select the external OCxREF clear from ETR 1: Select the internal OCxREF clear from comparator Note: For TIM5, setting to 1 is invalid Before operating this bit, the extended mode of the chip must be turned on (set PWR_CTRL3.EXMODE)
Page 359 Bit field Name Description CLKD[1:0] Clock division CLKD[1:0] indicates the division ratio between CK_INT (timer clock) and t (clock used for dead-time generator and digital filters (ETR, TIx)) 00: t CK_INT 01: t = 2 × t CK_INT 10: t = 4 ×...
Page 360: Control Register 2 (Timx_Ctrl2)
Bit field Name Description UPDIS Update disable This bit is used to enable/disable the Update event (UEV) events generation by software. 0: Enable UEV. And UEV will be generated if one of following condition been fulfilled: – Counter overflow/underflow – The TIMx_EVTGEN.UDGN bit is set –...
Page 361: Slave Mode Control Register (Timx_Smctrl)
Bit field Name Description MMSEL[2:0] Master Mode Selection These 3 bits (TIMx_CTRL2. MMSEL [2:0]) are used to select the synchronization information (TRGO) sent to the slave timer in the master mode. Possible combinations are as follows: 000: Reset –When the TIMx_EVTGEN.UDGN is set or a reset is generated by the slave mode controller, a TRGO pulse occurs.
Page 362 Bit field Name Description 0: External clock mode 2 disable. 1: External clock mode 2 enable. Note 1: When external clock mode 1 and external clock mode 2 are enabled at the same time, the input of the external clock is ETRF. Note 2: The following slave modes can be used simultaneously with external clock mode 2: reset mode, gated mode and trigger mode;...
Page 363: Table 12-3 Timx Internal Trigger Connection
Bit field Name Description TSEL[2:0] Trigger selection These 3 bits are used to select the trigger input of the synchronous counter. 000: Internal trigger 0 (ITR0) 100: TI1 edge detector (TI1F_ED) 001: Internal trigger 1 (ITR1) 101: Filtered timer input 1 (TI1FP1) 010: Internal trigger 2 (ITR2) 110: Filtered timer input 2 (TI2FP2) 011: Internal trigger 3 (ITR3) 111: External triggered Input (ETRF) For more details on ITRx, see Table 12-3 below.
Page 364: Dma/Interrupt Enable Registers (Timx_Dinten)
12.4.5 DMA/Interrupt enable registers (TIMx_DINTEN) Offset address: 0x0C Reset value: 0x0000 Bit field Name Description Reserved Reserved, the reset value must be maintained TDEN Trigger DMA request enable 0: Disable trigger DMA request 1: Enable trigger DMA request Reserved Reserved, the reset value must be maintained CC4DEN Capture/Compare 4 DMA request enable 0: Disable capture/compare 4 DMA request...
Page 365: Status Registers (Timx_Sts)
Bit field Name Description 1: Enables capture/compare 2 interrupts CC1IEN Capture/Compare 1 interrupt enable 0: Disable capture/compare 1 interrupt 1: Enables capture/comparing 1 interrupt UIEN Update interrupt enable 0: Disable update interrupt 1: Enables update interrupt 12.4.6 Status registers (TIMx_STS) Offset address: 0x10 Reset value: 0x0000 Bit field...
Page 366: Event Generation Registers (Timx_Evtgen)
Bit field Name Description CC3ITF Capture/Compare 3 interrupt flag See TIMx_STS.CC1ITF description. CC2ITF Capture/Compare 2 interrupt flag See TIMx_STS.CC1ITF description. CC1ITF Capture/Compare 1 interrupt flag When the corresponding channel of CC1 is in output mode: Except in center-aligned mode, this bit is set by hardware when the counter value is the same as the compare value (see TIMx_CTRL1.CAMSEL bit description).
Page 367: Capture/Compare Mode Register 1 (Timx_Ccmod1)
Bit field Name Description Trigger generation This bit can generate a trigger event when set by software. And at this time TIMx_STS.TITF = 1, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be generated. This bit is automatically cleared by hardware. 0: No action 1: Generated a trigger event Reserved...
Page 368 Output compare mode: Bit field Name Description OC2CEN Output Compare 2 clear enable 14:12 OC2MD[2:0] Output Compare 2 mode OC2PEN Output Compare 2 preload enable OC2FEN Output Compare 2 fast enable CC2SEL[1:0] Capture/compare 2 selection These bits are used to select the input/output and input mapping of the channel 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 369 Bit field Name Description OC1PEN Output Compare 1 preload enable 0: Disable preload function of TIMx_CCDAT1 register. Supports write operations to TIMx_CCDAT1 register at any time, and the written value is effective immediately. 1: Enable preload function of TIMx_CCDAT1 register. Only read and write operations to preload registers.
Page 370: Capture/Compare Mode Register 2 (Timx_Ccmod2)
Bit field Name Description IC1F[3:0] Input Capture 1 filter These bits are used to define sampling frequency of TI1 input and the length of digital filter. The digital filter is an event counter that generates an output transition after N events are recorded. 0000: No filter, sampling at f frequency 0001: f...
Page 371 Bit field Name Description OC4CEN Output compare 4 clear enable 14:12 OC4MD[2:0] Output compare 4 mode OC4PEN Output compare 4 preload enable OC4FEN Output compare 4 fast enable CC4SEL[1:0] Capture/Compare 4 selection These bits are used to select the input/output and input mapping of the channel 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 372: Capture/Compare Enable Registers (Timx_Ccen)
Bit field Name Description CC4SEL[1:0] Capture/Compare 4 selection These bits are used to select the input/output and input mapping of the channel 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 373: Counters (Timx_Cnt)
Bit field Name Description CC2P Capture/Compare 2 output polarity See TIMx_CCEN.CC1P description. CC2EN Capture/Compare 2 output enable See TIMx_CCEN.CC1EN description. Reserved Reserved, the reset value must be maintained CC1P Capture/Compare 1 output polarity When the corresponding channel of CC1 is in output mode: 0: OC1 active high 1: OC1 active low When the corresponding channel of CC1 is in input mode:...
Page 374: Prescaler (Timx_Psc)
Bit field Name Description 15:0 CNT[15:0] Counter value 12.4.12 Prescaler (TIMx_PSC) Offset address: 0x28 Reset value: 0x0000 Bit field Name Description 15:0 PSC[15:0] Prescaler value Counter clock f / (PSC [15:0] +1). CK_CNT CK_PSC Each time an update event occurs, the PSC value is loaded into the active prescaler register. 12.4.13 Auto-reload register (TIMx_AR) Offset address: 0x2C Reset values: 0xFFFF...
Page 375: Capture/Compare Register 2 (Timx_Ccdat2)
Bit field Name Description 15:0 CCDAT1[15:0] Capture/Compare 1 value • CC1 channel is configured as output: CCDAT1 contains the value to be compared to the counter TIMx_CNT, signaling on the OC1 output. If the preload feature is not selected in TIMx_CCMOD1.OC1PEN bit, the written value is immediately transferred to the active register.
Page 376: Capture/Compare Register 4 (Timx_Ccdat4)
Bit field Name Description 15:0 CCDAT3[15:0] Capture/Compare 3 value • CC3 channel is configured as output: CCDAT3 contains the value to be compared to the counter TIMx_CNT, signaling on the OC3 output. If the preload feature is not selected in TIMx_CCMOD2.OC3PEN bit, the written value is immediately transferred to the active register.
Page 377: Dma Control Register (Timx_Dctrl)
12.4.18 DMA Control register (TIMx_DCTRL) Offset address: 0x48 Reset value: 0x0000 Bit field Name Description 15:13 Reserved Reserved, the reset value must be maintained 12:8 DBLEN[4:0] DMA Burst Length This bit field defines the number DMA will accesses (write/read) TIMx_DADDR register. 00000:1 time transfer 00001: 2 times transfers 00010: 3 times transfers...
Page 378 Bit field Name Description 15:0 BURST[15:0] DMA access buffer. When a read or write operation is assigned to this register, the register located at the address range (DMA base address + DMA burst length × 4) will be accessed. DMA base address = The address of TIM_CTRL1 + TIMx_DCTRL. DBADDR * 4； DMA burst len = TIMx_DCTRL.DBLEN + 1.
Page 379: Basic Timers (Tim6 And Tim7)
Basic timers (TIM6 and TIM7) Introduction Basic timers TIM6 and TIM7 each contain a 16-bit auto-reload counter. These two timers are independent of each other and do not share any resources. The basic timer can provide a time reference for general purpose timers. The basic timer is directly connected to the DAC inside the chip and drives the DAC directly through the trigger output.
Page 380: Counter Mode
Depending on the setting of the auto-reload preload enable bit (TIMx_CTRL1.ARPEN), the value of the preload register is transferred to the shadow register immediately or at each update event UEV. An update event is generated when the counter reaches the overflow condition and it can be generated by software when TIMx_CTRL1.UPDIS=0. The counter CK_CNT is valid only when the TIMx_CTRL1.CNTEN bit is set.
Page 381: Figure 13-3 Timing Diagram Of Up-Counting. The Internal Clock Divider Factor = 2/N
TIMx_STS.UDITF is set, all registers are updated: • Update auto-reload shadow registers with preload value(TIMx_AR), when TIMx_CTRL1.ARPEN = 1. • The prescaler shadow register is reloaded with the preload value(TIMx_PSC) To avoid updating the shadow registers when new values are written to the preload registers, you can disable the update by setting TIMx_CTRL1.UPDIS=1.
Page 382: Figure 13-4 Timing Diagram Of The Up-Counting, Update Event When Arpen=0/1
Figure 13-4 Timing diagram of the , update event when ARPEN=0/1 up-counting ARPEN = 0 CNTEN CK_PSC Timer clock = CK_CNT 33 34 35 36 00 01 02 03 04 05 06 07 Counter register Counter overflow Update event（UEV） Update interrupt flag(UDITF) Auto-reload preload register Change AR value Write a new value in TIMx_AR...
Page 383: Clock Selection
13.3.3 Clock selection • The internal clock of timers ：CK_INT Internal clock source (CK_INT) It is provided that the TIMx_CTRL1.CNTEN bit is written as' 1 ' by software, the clock source of the prescaler is provided by the internal clock CK_INT. Figure 13-5 Control circuit in normal mode, internal clock divided by 1 CEN=CNTEN Internal clock...
Page 384: Register Overview
13.4.1 Register overview Table 13-1 Register overview Offset Register TIMx_CTRL1 000h Reset Value TIMx_CTRL2 004h Reset Value 008h Reserved TIMx_DINTEN 00Ch Reset Value TIMx_STS 010h Reset Value TIMx_EVTGEN 014h Reset Value 018h Reserved 01Ch Reserved 020h Reserved TIMx_CNT CNT[15:0] 024h Reserved Reset Value TIMx_PSC...
Page 385: Control Register 2 (Timx_Ctrl2)
Bit field Name Description ARPEN ARPEN: Auto-reload preload enable 0: Shadow register disable for TIMx_AR register 1: Shadow register enable for TIMx_AR register Reserved Reserved, the reset value must be maintained ONEPM One-pulse mode 0: Disable one-pulse mode, the counter counts are not affected when an update event occurs. 1: Enable one-pulse mode, the counter stops counting when the next update event occurs (clearing TIMx_CTRL1.CNTEN bit) UPRS...
Page 386: Dma/Interrupt Enable Registers (Timx_Dinten)
Bit field Name Description 15:7 Reserved Reserved, the reset value must be maintained MMSEL[2:0] Master Mode Selection These 3 bits (TIMx_CTRL2. MMSEL [2:0]) are used to select the synchronization information (TRGO) sent to the slave timer in the master mode. Possible combinations are as follows: 000: Reset –When the TIMx_EVTGEN.UDGN is set or a reset is generated by the slave mode controller, a TRGO pulse occurs.
Page 387: Status Registers (Timx_Sts)
Bit field Name Description UIEN Update interrupt enable 0: Disable update interrupt 1: Enable update interrupt 13.4.5 Status Registers (TIMx_STS) Offset address: 0x10 Reset value: 0x0000 Bit field Name Description 15:1 Reserved Reserved, the reset value must be maintained UDITF Update interrupt flag This bit is set by hardware when an update event occurs under the following conditions: –...
Page 388: Counter (Timx_Cnt)
Bit field Name Description Software can set this bit to update configuration register value and hardware will clear it automatically. 0: No effect. 1: Timer counter will restart and all shadow register will be updated. It will restart prescaler counter also. 13.4.7 Counter (TIMx_CNT) Offset address: 0x24 Reset value: 0x0000...
Page 389 Bit field Name Description 15:0 AR[15:0] Auto-reload value These bits define the value that will be loaded into the actual auto-reload register. See 13.3.1 for more details. When the TIMx_AR.AR [15:0] value is null, the counter does not work. 389 / 816...
Page 390: Real-Time Clock (Rtc)
Real-time clock (RTC) Description • The real-time clock (RTC) is an independent BCD timer/counter. • Daylight saving time compensation supported by software. • A periodic automatic programmable wakeup timer. • Two 32-bit registers contain the seconds, minutes, hours, day (day of week), date (day of month), month, and year.
Page 391: Rtc Function Description
Main function Description Programmable alarm clock and interrupt function. The alarm can be triggered by any combination of the calendar fields. When the alarm event occurs the alarm flag can be sent to GPIO through Alarm “RTC_OUT”, and it also can be used to wake up the CPU or exit from the low power status such as SLEEP, STOP0, STOP2 and STANDBY modes.
Page 392: Gpios Of Rtc
− Auto wakeup output (polarity configurable). • RTC input functions: − Timestamp event detection • Control PC13 by configuring output register: − Set RTC_OPT.TYPE bit to configure open-drain/push-pull output of PC13 14.2.2 GPIOs of RTC Timestamp input come from IOM (mapped to PC13) or EXTI module, if EXTI module is needed to start, please refer to the timestamp trigger source selection register (EXTI_TS_SEL) for details.
Page 393: Rtc Calendar
The ck_apre clock is used to driven RTC_SUBS sub-second down counter. When it reaches 0, reload RTC_SUBS with the value of RTC_PRE.DIVS[14:0]. 14.2.5 RTC calendar There are three shadow registers, they are RTC_DATE, RTC_TSH and RTC_SUBS. The RTC time and date registers can be accessed through the shadow registers.
Page 394: Calibration Clock Output
to read calendar value. • Read the data of RTC_SUBS, RTC_TSH and RTC_DATE twice. • Compare the data read twice, if they are equal, the read data can be considered correct; if they are not equal, read the data for the third time. •...
Page 395: Alarm Configuration
Alarm output: Alarm A or Alarm B can be mapped to RTC_ALxRM output when RTC_CTRL.OUTSEL[1:0] is selected, and output polarity can be configured by RTC_CTRL.OPOL bit. Note: If the seconds field is selected (RTC_ALARMx.MASK1 bit reset), RTC_PRE.DIVS[14:0] must be larger than 3 to ensure correct operation.
Page 396: Wakeup Timer Configuration
is selected, the RTC_OUT pin(PC13) is automatically configured as output, and output polarity can be configured by RTC_CTRL.OPOL bit. 14.2.13 Wakeup timer configuration The wakeup timer automatic reload value should be configured in the following below: • Disable wakeup timer by clearing RTC_CTRL.WTEN bit, then wait for RTC_INITSTS.WTWF flag to be set 1. •...
Page 397: Rtc Digital Clock Precision Calibration
Note: Before starting a shift operation, user must check RTC_SUBS.SS[15] bit is 0. Whenever write RTC_SCTRL register, the RTC_INITSTS.SHOPF flag will be set by hardware, which indicate a shift operation is pending. Once this shift operation is complete, the bit is cleared by hardware. 14.2.17 RTC digital clock precision calibration Digital precision calibration is achieved by adjusting the number of RTC clock pulses in the calibration period.
Page 398: Rtc Low Power Mode
• The calibration period is 16 seconds. Using an accurate 16-second period to measure the 1Hz calibration output can ensure that the measurement error is within 0.954ppm (0.5 RTCCLK cycles within 16 seconds). • The calibration period is 8 seconds. Using an accurate 8-second period to measure the 1Hz calibration output can ensure that the measurement error is within 1.907ppm (0.5 RTCCLK cycles within 8 seconds).
Page 399: Rtc Calendar Time Register (Rtc_Tsh)
Offset Register RTC_INITSTS 00Ch Reserved Reset Value RTC_PRE DIVA[6:0] DIVS[14:0] 010h Reserved Reset Value RTC_WKUPT WKUPT[15:0] 014h Reserved Reset Value RTC_ALARMA DTT[1:0] DTU[3:0] HOT[1:0] HOU[3:0] MIT[2:0] MIU[3:0] SET[2:0] SEU[3:0] 01Ch Reset Value RTC_ALARMB DTT[1:0] DTU[3:0] HOT[1:0] HOU[3:0] MIT[2:0] MIU[3:0] SET[2:0] SEU[3:0] 020h Reset Value...
Page 400: Rtc Calendar Date Register (Rtc_Date)
Bit field Name Description 31:23 Reserved Reserved, the reset value must be maintained AM/PM format. 0:AM format or 24-hour format 1:PM format 21:20 HOT[1:0] Describes the hour tens value in BCD format 19:16 HOU[3:0] Describes the hour units value in BCD format Reserved Reserved, the reset value must be maintained 14:12...
Page 401: Rtc Control Register (Rtc_Ctrl)
Bit field Name Description DAT[1:0] Describes the date tens value in BCD format DAU[3:0] Describes the date units value in BCD format 14.3.4 RTC Control Register (RTC_CTRL) Address offset: 0x08 Reset value: 0x0000 0000 Bit field Name Description 31:24 Reserved Reserved, the reset value must be maintained COEN Calibration output enable...
Page 402 Bit field Name Description 1: Subtracts 1 hour to the current time. AD1H Add 1 hour (summer time change) When this bit is set, 1 hour can be added to the calendar time. This bit is always read as. 0: No effect. 1: Adds 1 hour to the current time.
Page 403: Rtc Initial Status Register (Rtc_Initsts)
Bit field Name Description WKUPSEL[2:0] Wakeup clock selection 000: RTC clock is divided by 16 001: RTC clock is divided by 8 010: RTC clock is divided by 4 011: RTC clock is divided by 2 10x: ck_spre (usually 1Hz) clock is selected 14.3.5 RTC Initial Status Register (RTC_INITSTS) Address offset: 0x0C Reset value: 0x0000 0007...
Page 404 Bit field Name Description ALAF Alarm A flag This flag is set to ‘1’ by hardware when the time/date registers value match the Alarm A register values. This flag can be cleared by software writing 0 INITM Enter Initialization mode 0: Free running mode 1: Enter initialization mode and set calendar time value, date value, and prescale value.
Page 405: Rtc Prescaler Register (Rtc_Pre)
Bit field Name Description 0: Alarm A update is not allowed 1: Alarm A update is allowed 14.3.6 RTC Prescaler Register (RTC_PRE) Address offset: 0x10 Reset value: 0x007F 00FF Bit field Name Description 31:23 Reserved Reserved, the reset value must be maintained 22:16 DIVA[6:0] Asynchronous prescaler factor...
Page 406: Rtc Alarm A Register (Rtc_Alarma)
Bit field Name Description In particular, when RTC_CTRL.WKUPSEL[2:0] is set to 010, the modified setting does not take effect immediately, but will take effect after wake up in the next cycle. 14.3.8 RTC Alarm A Register (RTC_ALARMA) Address offset: 0x1C Reset value: 0x0000 0000 Bit field Name...
Page 407: Rtc Alarm B Register (Rtc_ Alarmb)
14.3.9 RTC Alarm B Register (RTC_ ALARMB) Address offset: 0x20 Reset value: 0x0000 0000 Bit field Name Description MASK4 Alarm date mask 0: Date/day match 1: Date/day not match WKDSEL Week day selection 0: DTU[3:0] represents the date units 1: DTU[3:0] represents week day only. DTT[1:0] is not considered 29:28 DTT[1:0] Describes the date tens value in BCD format...
Page 408: Rtc Sub-Second Register (Rtc_Subs)
Bit field Name Description 31:8 Reserved Reserved, the reset value must be maintained PKEY[7:0] Write protection key Reading this byte always returns 0x00. For detail on how to unlock RTC register write protection, see chapter RTC write protection register. 14.3.11 RTC Sub-second Register (RTC_SUBS) Address offset: 0x28 Reset value: 0x0000 0000 Bit field...
Page 409: Rtc Timestamp Time Register (Rtc_Tst)
Bit field Name Description SUB1S Add one second 0: No impact. 1: Subtract one second to the clock/calendar This bit can only be written and read as zero. Writing to this bit does not have an impact when RTC_INITSTS.SHOPF=1. 30:15 Reserved Reserved, the reset value must be maintained 14:0...
Page 410: Rtc Timestamp Date Register (Rtc_Tsd)
Bit field Name Description 11:8 MIU[3:0] Describes the minute units value in BCD format Reserved Reserved, the reset value must be maintained SET[2:0] Describes the second tens value in BCD format SEU[3:0] Describes the second units value in BCD format 14.3.14 RTC Timestamp Date Register (RTC_TSD) Address offset: 0x34 Reset value: 0x0000 0000...
Page 411: Rtc Calibration Register (Rtc_Calib)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 SSE[15:0] Sub second value SSE[15:0] is the value in the synchronous prescaler counter. The fraction of a second is provided by the formula below: Second fraction = (RTC_PRE.DIVS[14:0] – SSE[15:0]) / (RTC_PRE.DIVS[14:0] + Note: SSE[15:0] can be larger than RTC_PRE.DIVS[14:0] only after a shift operation.
Page 412: Rtc Alarm A Sub-Second Register (Rtc_ Alrmass)
14.3.17 RTC Alarm A sub-second register (RTC_ ALRMASS) Address offset: 0x44 Reset value: 0x0000 0000 Bit field Name Description 31:28 Reserved Reserved, the reset value must be maintained 27:24 MASKSSB[3:0] Mask the most significant bit from this bits. 0x0: No comparison on sub seconds for Alarm. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
Page 413: Rtc Option Register (Rtc_ Opt)
Bit field Name Description 27:24 MASKSSB[3:0] Mask the most significant bit from this bits. 0x0: No comparison on sub seconds for Alarm. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x1: Only SSV[0] is compared and other bits are not compared.
Page 414: Crc Calculation Unit
CRC calculation unit Introduction This module integrates the functions of CRC32 and CRC16, and the cyclic redundancy check (CRC) calculation unit obtains any CRC calculation result according to a fixed generator polynomial. In other applications, CRC technology is mainly used to verify the correctness and integrity of data transmission or data storage. EN/IEC 60335-1 provides a method to verify the integrity of flash memory.
Page 415: Function Description
Figure 15-1 CRC calculation unit block diagram CRC32 CRC16 Ctrl&Data Regs AHBInf Function description 15.3.1 CRC32 CRC unit contains one 32-bit data register: • Writing this register to input CRC data. • Reading this register to get the calculated CRC result. Every writing operation of this data register triggers the calculation of this new data with the previous calculation result (CRC calculation is performed on the whole 32-bit word rather than byte by byte).
Page 416: Crc Registers
CRC registers 15.4.1 CRC register overview Table 15-1 CRC register overview Offset Register CRC32DAT CRC32DAT[31:0] 000h Reset Value CRC32IDAT CRC32IDAT[7:0] 004h Reserved Reset Value CRC32CTRL 008h Reserved Reset Value CRC16CTRL 00Ch Reserved Reset Value CRC16DAT CRC16DAT[7:0] 010h Reserved Reset Value CRC16D CRC16D[15:0] 014h...
Page 417: Crc32 Control Register (Crc_Crc32Ctrl)
Bit field Name Description 31:8 Reserved Reserved, the reset value must be maintained. CRC32IDAT[7:0] Independent 8-bit data register. General 8 bits data register. It is for temporary stored 1-byte data. CRC_CRC32CTRL.RESET reset signal will not impact this register. Note: This register is not a part of CRC calculation and can be used to store any data. 15.4.4 CRC32 control register (CRC_CRC32CTRL) Address offset: 0x08 Reset value: 0x0000 0000...
Page 418: Crc16 Input Data Register (Crc_Crc16Dat)
Bit field Name Description Clear CRC16 results. 0: Not clear. 1: Clear to default value 0x0000. Set this bit to 1 will only maintain 1 clock cycle, hardware will clear automatically. (Software read always 0). ENDHL Data to be verified start to calculate from MSB or LSB(configured endian). 0: From MSB to LSB 1: From LSB to MSB This bit is only for data to be verified.
Page 419: Lrc Result Register (Crc_Lrc)
Bit field Name Description CRC16 is updated in this register. Note: 8-bits, 16-bits and 32-bits operations are supported (8-bit operations must be performed twice in a row to ensure that 16-bit initial values are configured properly) 15.4.8 LRC result register (CRC_LRC) Address offset: 0x18 Reset value: 0x0000 0000 Bit field...
Page 420: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) Introduction The N32G45x has built-in independent watchdog (IWDG) and window watchdog (WWDG) timers to solve the problems caused by software errors. Watchdog timer is very flexible to use, which improves the security of the system and the accuracy of timing control. Independent Watchdog (IWDG) is driving by Low-speed internal clock (LSI clock) running at 40 KHz, which will still running event dead loop or MCU stuck is happening.
Page 421: Functional Description
Functional description Figure 16-1 Functional block diagram of the independent watchdog module User Program 40KHz IWDG_KEY.KEYV == 0x5555 IWDG_PREDIV.PD IWDG_STS.PVU 4/8/16/32/64/128/256 Counter == 0 IWDG_RELV.REL 12 Bit IWDG Reset 12-bit reload value Down Counter IWDG_STS.CRVU Reload Enable IWDG_KEY.KEYV Note: Watchdog function is in V power supply area, and it can still work normally in SLEEP, STOP0, STOP2 and STANDBY modes.
Page 422: Debug Mode
16.3.2 Debug mode In debug mode (Cortex-M4 core stops), IWDG counter will either continue to work normally or stops, depending on DBG_CTRL.IWDG_STOP bit in debug module. If this bit is set to ‘1’, the counter stops. The counter works normally when the bit is ‘0’.
Page 423: Iwdg Configuration Flow
Table 16-1 IWDG counting maximum and minimum reset time Minimum（ms） Maximum（ms） Pre-scale factor PD[2:0] RL[11:0]=0 RL[11:0]=0xFFF 409.6 819.2 1638.4 3276.8 6553.6 /128 13107.2 /256 26214.4 16.4.2 IWDG configuration flow Software flow: Write 0x5555 to IWDG_KEY.KEYV[15:0] bits to enable write access of IWDG_PREDIV and IWDG_RELV registers.
Page 424: Iwdg Registers
IWDG registers 16.5.1 IWDG register overview Table 16-2 IWDG register overview Offset Register IWDG_KEY KEYV[15:0] 0x00 Reserved Reset value IWDG_PREDIV PD[2:0] 0x04 Reserved Reset value IWDG_RELV REL[11:0] 0x08 Reserved Reset value IWDG_STS 0x0C Reserved Reset value 16.5.2 IWDG key register (IWDG_KEY) Address offset: 0x00 Reset value: 0x00000000 Bit field...
Page 425: Iwdg Reload Register (Iwdg_Relv)
Bit field Name Description 31:3 Reserved Reserved, the reset value must be maintained. PD[2:0] Pre-frequency division factor Pre-scaler divider: with write access protection when IWDG_KEY.KEYV[15:0] is not 0x5555. The IWDG_STS.PVU bit must be 0 otherwise PD [2:0] value cannot be changed. Divide number is as follow: 000: divider /4 001: divider /8...
Page 426: Iwdg Status Register (Iwdg_Sts)
Bit field Name Description 11:0 REL[11:0] Watchdog counter reload value. With write protection. Defines the reload value of the watchdog counter, which is loaded to the counter every time 0xAAAA is written to IWDG_KEY.KEYV[15:0] bits. The counter then starts to count down from this value.
Page 427: Window Watchdog (Wwdg)
Window watchdog (WWDG) Introduction The clock of the window watchdog (WWDG) is obtained by dividing the APB1 clock frequency by 4096, and whether the program operation is abnormal is detected through the configuration of the time window. Therefore, WWDG is suitable for precise timing, and is often used to monitor software failures caused by external disturbances or unforeseen logic conditions that cause an application to deviate from its normal operating sequence.
Page 428: Timing For Refresh Watchdog And Interrupt Generation
decrement speed of the counter. WWDG_CFG.W[6:0] bits set the upper limit of the window. When the down-counter is refreshed before reaching the window register value or after WWDG_CTRL.T6 bit becomes 0, a system reset will be generated. Figure 17-2 describes the working process of the window register. Set the WWDG_CFG.EWINT bit to enable early wake-up interrupt.
Page 429: Debug Mode
�� = �� × 4096 × 2 × (��[5: 0] + 1) �� 1 In which: : WWDG timeout WWDG :APB1 clock interval in ms PCLK1 Minimum-maximum timeout value at PCLK1 = 36MHz Table 17-1 Maximum and minimum counting time of WWDG TIMERB Maximum counting (ms) Minimum counting (ms)
Page 430: Wwdg Registers
WWDG registers 17.7.1 WWDG register overview Table 17-2 WWDG register overview Offset Register WWDG_CTRL T[6:0] 000h Reserved Reset Value TIMERB WWDG_CFG W[6:0] [1:0] 004h Reserved Reset Value WWDG_STS 008h Reserved Reset Value 17.7.2 WWDG control register (WWDG_CTRL) Address offset : 0x00 Reset value : 0x0000007F Bit field Name...
Page 431: Wwdg Status Register (Wwdg_Sts)
Bit field Name Description Reserved Reserved, the reset value must be maintained. 31:10 EWINT Early wake-up interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. TIMERB[1:0] Timer base.
Page 432: Sdio Interface（Sdio
SDIO Interface（SDIO） Main features of SDIO SDIO interface defines SD card, SD I/O card, Multimedia Card (MMC) host interface. It provides data transfer between AHB peripheral bus and SD memory card, SDIO card, Multimedia Card (MMC) and CE-ATA devices. Among them, the supported multimedia card system specifications are published by the MMCA technical committee and can be obtained on the website of the Multimedia Card Association (www.mmca.org), and the supported CE- ATA system specifications can be found in the CE-ATA working group.
Page 433: Figure 18-1 Sdio "No Response" And "No Data" Operations
initialize the card through a special message-based bus protocol. Each message is a command/response structure, additionally, some messages have data tokens. Each part of the message is described in detail as follows: • Command: The command is serially transmitted on the CMD line and is a token to initiate an operation, sent from the host to the card •...
Page 434: Sdio Function Description
Figure 18-2 SDIO (multi) data block read operation The stop command stops data transfer SDIO_CMD command command command response host to devise device to host host to devise device to host SDIO_DATA Data block Data block Data block Single block operation 单块读操作...
Page 435: Sdio Adapter
• SDIO adapter: It consists of control unit, command unit and data unit. The control unit generates a clock signal, and the command unit and data unit manage the transmission of commands and data respectively, thereby realizing the related functions of the MMC/SD/SD I/O card. . •...
Page 436: Adapter Register Block
The HCLK/2 of the AHB bus is used as the clock of the adapter register and FIFO, and the SDIOCLK(equal to HCLK) is used as the clock of the control unit, command channel and data channel. The SDIO adapter includes five parts: control unit, adapter register module, command unit, data unit and data FIFO. The signals output to the card bus are as follows: •...
Page 437: Command Unit
used to avoid FIFO underflow and overflow errors. The hardware controls the switch of SDIO_CLK according to whether the system bus is busy. When the FIFO cannot receive or transmit data, the host will turn off SDIO_CLK and freeze the SDIO state machine to avoid related errors. Only the state machine can be frozen, but the AHB interface is still working.
Page 438: Figure 18-9 Sdio Adapter Command Unit
Figure 18-9 SDIO adapter command unit Command Unit SDIO_CMD out Status flag To Control unit Logic Command control timer Adapter register Shift SDIO_CMD register Parameter To AHB interface Response Register • Command Path State Machine (CPSM) Figure 18-10 Command Path State Machine (CPSM) CE-ATA command received complete Idle Wait_CPL...
Page 439 • Idle This state is an idle state. After the system is reset, the state is ready to send a command or the command state machine (CPSM) is turned off. All belong to the Idle state. When the command state machine (CPSM) is enabled, wait for the end of data transmission bit (SDIO_CMDCTRL.WDATEND) Enable or disable can enter the Pend state.
Page 440: Data Channel
Figure 18-11 SDIO command transmission At least 8 SDIO_CLK cycles SDIO_CLK Command Response Command Controller Driven by a Controller Hi-Z SDIO_CMD Hi-Z Hi-Z driven card driven State Idle Send Wait Receive Idle Send • Command register The 6-bit command index and command type sent to the card are stored in the command register; the command type (see Section 18.7.4) determines whether and what type of response (48-bit or 136-bit).
Page 441: Data Path State Machine (Dpsm)
Figure 18-12 Data Channel Data channel SDIO_DAT out [7:0] Status flag To control unit Control logic Command timer Data FIFO Shift Send SDIO_DAT in [7:0] register Receive The data bus width of the card can be configured in the clock control register (SDIO_CLKCTRL). When the data width is 4 bits (SDIO_ CLKCTRL.BUSMODE bit is 0b01), 4 bits of data will be transmitted on the four data signal lines SDIO_DAT[3:0] in each clock cycle;...
Page 442: Figure 18-13 Data Path State Machine (Dpsm)
Figure 18-13 Data Path State Machine (DPSM) DPSM was closed DPSM enabled and Read Wait has started Idle Read Wait After reset and SD I/O mode has been enabled Enabled and Read wait stops not sent yet Data has been received "Read Wait"...
Page 443: Table 18-3 Data Token Format
• Wait_S: In this state, the DPSM waits for the data FIFO empty flag to be invalid or the end of the data transfer. If the data counter is 0, the DPSM enters the idle state; otherwise, the DPSM waits for the data FIFO empty flag to disappear before entering the sending state.
Page 444: Table 18-4 Transmit Fifo Status Flags
Data FIFO The data FIFO unit has a data buffer for sending and receiving data buffers. The FIFO contains a data buffer and transmit and receive circuits, where the buffer size is 32 bits wide per word, 32 words in total (32 words deep). The data FIFO operates in the AHB clock region (HCLK/2), and all signals connected to the SDIO clock region (SDIOCLK) are resynchronized.
Page 445: Sdio Ahb Interface
Flag Description clear register. 18.3.2 SDIO AHB Interface The AHB interface implements access to SDIO registers, data FIFOs, and generation of interrupts and DMA requests. Includes data channel, register decoder, and interrupt/DMA control logic. SDIO interrupt When at least one of the selected status flags is high, the interrupt control logic generates an interrupt request. The interrupt enable register allows the interrupt logic to generate the corresponding interrupt.
Page 446: Card Function Description
SDIO_DATCTRL.DATDIR is set to 0 (the transmission direction is from the controller to the card); SDIO_DATCTRL.TRANSMOD is set to 0 (block data transfer); SDIO_DATCTRL.DMAEN is set to 1 (DMA enabled); SDIO_DATCTRL.BLKSIZE is set to 9 (512 bytes); other fields do not need to be set. Bit10 DATBLKEND flag bit of wait status register SDIO_STS is set.
Page 447: Card Identification Mode
18.4.3 Card identification mode After the host resets, it enters the card identification mode to search for a new card on the bus. In card identification mode, the host resets all cards, verifies the operating voltage range, identifies the cards and asks each card for the relative card address (RCA).
Page 448: Write Data Block
The SDIO card host repeats steps 4 and 5 above for all activated cards until a timeout condition is received. The SD I/O card identification process is as follows: The bus is enabled The SDIO card host sends the CMD5 (IO_SEND_OP_COND) command to get the contents of the card's operating condition register If the card is not compatible, it will be placed in an inactive state The SDIO card host sends a CMD3 (SET_RELATIVE_ADDR) command and an address to an activated card,...
Page 449: Data Streaming Operation (Only For Multimedia Card)
size of the physical block. CMD17 (READ_SINGLE_BLOCK) means to start reading a data block, and the card returns to the sending state after the transmission is over. CMD18 (READ_MULTIPLE_BLOCK) starts to read multiple consecutive data blocks. In order to ensure the integrity of data transmission, there is a CRC check code after each data block. The block length is set by CMD16 and can be set to 512 bytes regardless of the setting of READ_BL_LEN.
Page 450: Erase
• TRAN_SPEED: Maximum bus clock frequency • WRITE_BL_LEN: maximum write block length • NSAC: Data read operation time in CLK cycles 2 • TAAC: Data read operation time 1 • R2W_FACTOR: Write speed factor All parameters are defined in CSD registers. If the host attempts to use a higher frequency, the card may not be able to process the data and stop programming while setting the error bit SDIO_STS.RXORERR in the status register and ignoring all subsequent data transfers, waiting (in the receive data state) for a stop command .
Page 451: Wide Bus Selection And De-Selection
The host can erase a contiguous range of erase groups. There are three steps involved in starting the erase operation. First, the host uses the ERASE_GROUP_START (CMD35) command to define the start address in the contiguous range, then uses the ERASE_GROUP_END (CMD36) command to define the end address of the contiguous range, and finally sends the erase command ERASE (CMD38) to start the erase operation.
Page 452: Password Protection
similar to the single data block read command. A data block of write protection bits, which represents 32 write protection groups starting from the specified address, followed by a 16-bit CRC code at the end. The address field of the write protect command is a group address in bytes, the card will truncate all addresses outside the group size. Physical write protection switch There is a mechanical slide switch on the side of the card, which provides the user with setting whether to write- protect the card.
Page 453: Clear Password
• PWD: password data, according to different commands, the password data is different. For example, in the case of setting a new password, it contains the new password, and when changing the password, it contains the old password and the new password set. The following sections list the command sequences to set/clear password, lock/unlock, and force wipe.
Page 454 a 16-bit CRC code. The data block contains the operation mode (LOCK_UNLOCK=1), the password length (PWDS_LEN) and the password data itself (PWD). If the PWD content is equal to the sent password, the card will be locked and the CARD_IS_LOCKED status bit in the status register will be set.
Page 455: Card Status Register
LOCK_UNLOCK_FAILED error bit in the status register, the data in the card remains unchanged, and the card remains locked. NOTE: Attempting to perform an erase operation on an already unlocked card will cause the operation to fail and set the LOCK_UNLOCK_FAILED error bit in the status register. 18.4.11 Card status register Card status register Card status refers to the error and status information of the executed command, indicated in the response.
Page 456 Clear Bits Identifier Type Value Description condition ‘1’=error block of data. ‘0’=card unlocked When this bit is set, it means the card has been CARD_IS_LOCKED ‘1’=card locked locked. ‘0’=no error Wrong sequence of commands in lock/unlock or LOCK_UNLOCK_FAILED ‘1’=error wrong password detected. ‘0’=no error COM_CRC_ERROR CRC check error in previous command.
Page 457: Sd Status Register
Clear Bits Identifier Type Value Description condition ‘7’= Program ‘8’= Disconnect ‘9’= Busy test ‘10~15’= Reserved READY_FOR_DATA ‘0’= no ready Corresponds to a buffer empty signal on the bus. ‘1’= ready SWITCH_ERROR ‘0’=no error The card did not switch to the desired mode as ‘1’=error required by the SWITCH command.
Page 458: Table 18-8 Sd Status
should be noted that ACMD13 commands can only be sent when the card is in the transmitting state (the card has been selected). Table 18-8 defines the different SD status register information. Table 18-8 SD Status Clear Bits Identifier Type Value Description condition...
Page 459: Table 18-9 Speed Type Codes
Clear Bits Identifier Type Value Description condition unit 401:400 ERASE_OFFSET Fixed offset value to increase (See below) when erasing 399:312 Reserved 311:0 Reserved for Manufacturer The abbreviations in the table for types and clearing condition fields are defined as follows: Type: •...
Page 460: Table 18-10 Mobility Performance Codes
Class 0 Class 2 Class 4 Class 6 04h~FFh Reserved PERFORMANCE_MOVE These 8 bits indicate the mobile performance (Pm) in units of 1MB/sec. If the card does not move data in RU (unit of record), Pm should be considered to be infinity. When this field is FFh, it means Pm is infinite. Table 18-10 Mobility Performance Codes PERFORMANCE_MOVE Value definition...
Page 461: Sd I/O Mode
ERASE_TIMEOUT. The host should determine the appropriate number of AUs to be erased in one operation so that the host can display the progress of the erase operation. If this field is 0, the timeout calculation for erasure is not supported.
Page 462: Commands And Responses
media card to the multi-media card. The /SD module makes an interrupt request. For each card or function within the card, the interrupt function is optional. The interrupt of SD I/O is level-effective, that is, the interrupt signal line must maintain the active level (low) before it can be recognized and responded by the multimedia card/SD module, and remains inactive level (high) after the interrupt process ends.
Page 463: Commands Of Multimedia Card/Sd Card Module
taking into account specific users and applications, so two types of general commands are defined in the standard: application-related commands (ACMD) and general commands (GEN_CMD) . When the card receives the APP_CMD (CMD55) command, the card expects the next command to be an application related command.
Page 464: Table 18-17 Block-Based Write-Protect Commands
Response Type Parameter Abbreviation Description Index Format received or the specified number of blocks is reached. Program the identification register of the card. This command can only be sent once per card. There are hardware CMD26 adtc [31:0]= Stuff bits PROGRAM_CID mechanisms in the card to prevent multiple programming operations.
Page 465: Table 18-18 Erase Command
Table 18-18 Erase command Response Type Parameter Abbreviation Description Index Format CMD32 Reserve. For backward compatibility with older versions of the media card protocol, these command codes cannot be …… used. CMD34 CMD35 [31:0]= Data Address ERASE_GROUP_START Within the selected erase range, set the address of the first erase group.
Page 466: Command Type
Response Type Parameter Abbreviation Description Index Format [15:0]= Stuff bits application-related command rather than a standard command. CMD56 adtc [31:1]= Stuff bits In general or application-related commands, either [0]=RD/WR to transfer a block of data to the card, or to read a block of data from the card.
Page 467: Response Format
[45:40] Command index [39:8] Parameter [7:1] CRC7 End bit Response: The response is a response to the previously received command, which is sent to the host by a card with a specified address. For all cards of MMC V3.31 or earlier, the response is sent simultaneously; the response is serially transmitted on the SDIO_CMD line.
Page 468: Table 18-25 R1 Response
Table 18-25 R1 response Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Card status [7:1] CRC7 End bit R1b has the same format as R1, the difference is that R1b can choose to send a busy signal on the data line. After receiving these commands, depending on the state before receiving the command, the card may become busy and the host should check the busy state in the response.
Page 469: Table 18-28 R4 Response
Table 18-28 R4 response Width Value Description Start bit Transmission bit [45:40] ‘111111’ Reserved [31:16] [39:8]Argument [15:8] Register address field [7:0] Read register contents [7:1] ‘1111111’ CRC7 End bit R4b is only available for SD I/O cards, and the code length is 48 bits. The SDIO card will return a unique SDIO response R4 after receiving the CMD5 command.
Page 470: Hardware Flow Control
Width Value Description [39:8]Argument [31:16] RCA[31:16] of a successful card or host field [15:0] Undefined. Can be used as interrupt data. [7:1] CRC7 End bit R6 (Interrupt Request) R6 only works with SD I/O cards. The code length is 48 bits. Bits[45:40] represent the command index to the CMD3 response.
Page 471: Sdio Register Overview
18.7.1 SDIO register overview Table 18-32 SDIO register overview Offset Register SDIO_PWRCTRL 000h Reserved CTRL Reset Value SDIO_CLKCTRL MODE DIV[7:0] 004h Reserved [1:0] Reset Value SDIO_CMDARG CMDARG 008h Reset Value SDIO_CMDCTRL RESP CMDIDX[5:0] 00Ch Reserved [1:0] Reset Value SDIO_CMDRESP RESPCMDIDX[5:0] 010h Reserved Reset Value...
Page 472: Sdio Power Control Register (Sdio_Pwrctrl)
18.7.2 SDIO power control register (SDIO_PWRCTRL) Address offset: 0x00 Reset value: 0x0000 0000 Bit Field Name Description 31:2 Reserved Reserved, the reset value must be maintained. PWRCTRL Power supply control bits. Defines the current functional state of the card clock: 00: The power is turned off and the clock of the card is stopped.
Page 473: Sdio Command Argument Register (Sdio_Cmdarg)
Bit Field Name Description 1: SDIO_CLK is generated on the falling edge of the master clock SDIOCLK. 12:11 BUSMODE Wide bus mode enable bit. 00: Default bus mode, use SDIO_DAT0. 01: 4-bit bus mode, use SDIO_DAT[3:0]. 10: 8-bit bus mode, use SDIO_DAT[7:0]. CLKBYP Clock divider bypass enable bit.
Page 474: Sdio Command Register (Sdio_Cmdctrl)
Bit Field Name Description 31:0 CMDARG Command argument. Command parameters are part of the command sent to the card. If a command contains a parameter, this register must be loaded before writing the command to the command register. 18.7.5 SDIO command register (SDIO_CMDCTRL) Address offset: 0x0C Reset value: 0x0000 0000 SDIO_CMDCTRL register contains the command index and command type bits.
Page 475: Sdio Command Response Register(Sdio_Cmdresp)
Bit Field Name Description The command index is sent to the card as part of the command. Notice: This register cannot be written within 7 HCLK clock cycles after writing data. The multimedia card can send 2 kinds of responses: 48-bit short response, or 136-bit long response. SD cards and SD I/O cards can only send short responses, the parameters can be changed according to the type of response, and the software will distinguish the type of response according to the command sent.
Page 476: Sdio Data Timer Register (Sdio_Dtimer)
31:0 CARDSTSx： See table below. Depending on the response status, the card's status length is either 32 bits or 127 bits. Table 18-33 Response Type and SDIO_RESPONSEx Register Register Short response Long response SDIO_ RESPONSE1 Card Status[31:0] Card Status[127:96] SDIO_ RESPONSE2 Unused Card Status[95:64] SDIO_ RESPONSE3...
Page 477: Sdio Data Control Register (Sdio_Datctrl)
Bit Field Name Description 31:25 Reserved Reserved, the reset value must be maintained. 24:0 DATLEN Data length value. Number of data bytes to transfer. Note: For block data transfers, the value in the data length register must be a multiple of the data block length (see SDIO_DATCTRL).
Page 478: Sdio Data Counter Register (Sdio_Datcount)
Bit Field Name Description 0001: block length = 2 = 2 bytes; 0010: block length = 2 = 4 bytes; 0011: block length = 2 = 8 bytes; 0100: (decimal 4) block length=2 =16 bytes; 0101: (decimal 5) block length=2 =32 bytes;...
Page 479: Sdio Status Register (Sdio_Sts)
Bit Field Name Description 31:25 Reserved Reserved, the reset value must be maintained. 24:0 DATCOUNT Data count value. When reading this register, it returns the number of data bytes to be transmitted. Writing this register has no effect. Note: This register can only be read at the end of a data transfer. 18.7.12 SDIO status register (SDIO_STS) Address offset: 0x34 Reset value: 0x0000 0000...
Page 480: Sdio Interrupt Clear Register (Sdio_Intclr)
Bit Field Name Description TFIFOF Transmit FIFO full. RFIFOHF Receive FIFO half full: There are at least 8 words left in the FIFO. TFIFOHE Transmit FIFO half empty: At least 8 more words can be written to the FIFO. RXRUN Data receive in progress.
Page 481: Sdio Interrupt Enable Register (Sdio_Inten)
Bit Field Name Description Software sets this bit to clear the SDIO_STS.DATBLKEND flag. SBERRC SBERR flag clear bit. Software sets this bit to clear the SDIO_STS.SBERR flag. DATENDC DATEND flag clear bit. Software sets this bit to clear the SDIO_STS.DATEND flag. CMDSENDC CMDSEND flag clear bit.
Page 482 Bit Field Name Description SDIOINTEN SDIO mode interrupt received interrupt enable Setting/clearing this bit by software to enable/disable the SDIO mode interrupt received interrupt function. 1: SDIO mode interrupt has been received and no interrupt will be generated 0: SDIO mode interrupt has been received and an interrupt is generated RDATVALIDEN Data available in Rx FIFO interrupt enable.
Page 483 Bit Field Name Description 0: Data is being sent without generating an interrupt 1: Interrupt when data is being sent CMDRUNEN Command acting interrupt enable. Setting/clearing this bit by software to enable/disable the command-in-transit interrupt. 0: Transmitting command without interrupt 1: Interrupt when command is being transmitted DATBLKENDEN Data block end interrupt enable.
Page 484: Sdio Fifo Counter Register (Sdio_Fifocount)
Bit Field Name Description Setting/clearing this bit by software to enable/disable the interrupt for block CRC detection failure. 0: Data block CRC detection failure does not generate an interrupt 1: Data block CRC detection failure generates an interrupt CCRCERREN Command CRC fail interrupt enable. Setting/clearing this bit by software to enable/disable the command CRC detection failure interrupt.
Page 485 The FIFO data occupies 32 entries of 32-bit words at the address: (SDIO base address + 0x80) to (SDIO base address + 0xFC) 485 / 816...
Page 486: Universal Serial Bus Full-Speed Device Interface (Usb_Fs_Device)
Universal serial bus full-speed device interface (USB_FS_Device) Introduction Universal serial bus full-speed device interface (USB_FS_Device) module is a peripheral that conforms to the USB2.0 full-speed protocol. It contains the USB PHY of the physical layer and does not require an additional PHY chip.
Page 487: Clock Configuration
Clock configuration The USB 2.0 protocol specification stipulates that the USB full-speed module uses a fixed 48MHz clock. In order to provide an accurate 48MHz clock to USB_FS_Device, a two-stage clock configuration is required, as follows: • In the first stage, the 48MHz working clock is obtained by accurate frequency division of PLLCLK, so when using USB_FS_Device, it is necessary to ensure that the PLLCLK clock is 48MHz/72MHz/96MHz/144MHz, otherwise USB_FS_Device cannot work normally;...
Page 488: Buffer Description Table
The description table of endpoint 7 starts from 56 bytes, so it will occupy 64 bytes of space. User application access Packet Buffer Memory The user application program on the microcontroller needs to access the Packet Buffer Memory from the APB1 bus according to 32-bit alignment and 16-bit read and write access, that is, the address of the operation data must be 32- bit aligned, and only 16-bit data can be read or written at a time, can't be 8-bit nor 32-bit.
Page 489: Double-Buffered Endpoints
0 only receives data up to the endpoint 0 packet receive buffer size, other redundant data is discarded and a buffer overflow exception occurs. Figure 19-3 The relationship between the buffer description table and the endpoint packet buffer Offset 0x1E CNT3_RX_1 Offset 0x1C ADDR3_RX_1...
Page 490: Table 19-1 Dattog And Sw_Buf Definitions
two flags for this: DATTOG and SW_BUF. DATTOG indicates the buffer currently being used by the USB module, and SW_BUF indicates the buffer currently being used by the application on the microcontroller. The definitions of DATTOG and SW_BUF are shown in Table 19-1 shown. A unidirectional endpoint using the double buffer mechanism only needs to use one USB_EPn register.
Page 491: Figure 19-4 Double Buffered Bulk Endpoint Example
another OUT data packet transmission on the USB bus at this time, the USB device will automatically reply the NAK handshake signal to indicate flow control until the application finishes processing the data in buffer0 corresponding to ADDR3_RX_0/CNT3_RX_0, and the software toggle SW_BUF = 1. In this case, the DATTOG and SW_BUF values are different.
Page 492: Usb Transfer
19.4.4 USB transfer Overview of USB transfer A USB transfer consists of multiple transactions, and a transaction consists of multiple packets. A packet is the basic unit of USB transmission. All data must be packaged before being transmitted on the USB bus. The process of one time receiving or sending data on the USB is called a transaction, and there are three types of transactions: Setup transaction, Data IN transaction, and Data OUT transaction.
Page 493: Control Transfer
USB_CNTn_RX register, which is used for buffer overflow detection. When the USB module receives data from the USB bus, the USB module organizes the received data in words (the first received is the low byte), and store it in the endpoint data packet receiving buffer pointed to by ADDR, at the same time, the CNT value is automatically incremented, and the BUF_COUNT value is automatically decremented.
Page 494 stage and entering the Status stage, the USB device can return a PID STALL handshake packet, and the Rx state of the direction to be used is set to VALID. When the first OUT transaction is completed correctly, the hardware generates the USB_EPn.CTRS_RX interrupt, and changes the Rx direction state of the USB device endpoint to NAK, the Tx direction state remains unchanged, the software judges whether the next OUT transaction to be enabled is the last Data stage in the interrupt.
Page 495: Figure 19-5 Control Transfer
Figure 19-5 Control transfer USB bus SETUP(0) DATA0 Tx = NAK Rx = NAK Tx = VALID Tx = STALL Rx = STALL Rx = VALID OUT(1) IN(1) DATA1 DATA1 Tx = STALL Tx = NAK Rx = NAK Rx = STALL Tx = VALID Tx = STALL Rx = STALL...
Page 496: Usb Events And Interrupts
mechanism, that is, there is no handshake stage, there is no handshake packet after the data packet, so there is no need to use the data toggle mechanism, and the isochronous transfer only transmits the PID DATA0 data packet. The isochronous endpoint uses a double buffer mechanism to reduce the processing pressure of the application. The buffer used by the USB module is identified by the DATTOG bit.
Page 497: Table 19-4 Resume Event Detection
• Wait for the internal reference voltage to stabilize, because it takes a start-up time to turn on the internal voltage, during which the USB transceiver is in an indeterminate state • Clear the USB_CTRL.FRST bit • Clear the USB_STS register, remove pending interrupts, and enable other units Note: Every time the USB module is enabled after system reset or power-on reset, the pull-up resistor on the DP signal line needs to be configured.
Page 498: Usb Interrupt
USB interrupt The USB controller has 3 interrupt lines, which are as follows: • USB low priority interrupt (channel 20): can be triggered by all USB events; • USB high-priority interrupt (channel 19): can only be triggered by correct transfer events for isochronous and double-buffered bulk transfers;...
Page 499: Usb Endpoint N Register (Usb_Epn), N=[0
Offset Register USB_EP2 EPADDR[3:0] 008h Reserved Reset Value USB_EP3 EPADDR[3:0] 00Ch Reserved Reset Value USB_EP4 EPADDR[3:0] 010h Reserved Reset Value USB_EP5 EPADDR[3:0] 014h Reserved Reset Value USB_EP6 EPADDR[3:0] 018h Reserved Reset Value USB_EP7 EPADDR[3:0] 01Ch Reserved Reset Value USB_CTRL 040h Reserved Reset Value USB_STS...
Page 500 Bit Field Name Description 31：16 Reserved Reserved, the reset value must be maintained. CTRS_RX Correct receive flag This bit is set by hardware when an OUT or SETUP transaction on this endpoint completes successfully. If USB_CTRL.CTRSM = 1, the corresponding interrupt will be generated.
Page 501 Bit Field Name Description 10：9 EP_TYPE[1:0] Endpoint type EP_TYPE[1:0] Description BULK: bulk endpoint CONTROL: control endpoint ISO: isochronous endpoint INTERRUPT: interrupt endpoint EP_KIND Endpoint special type EP_TYPE[1:0] EP_KIND meaning BULK DBL_BUF: double buffered endpoint CONTROL STATUS_OUT Undefined INTERRUPT Undefined CTRS_TX Correct send flag This bit is set by hardware when an IN transaction on this endpoint completes successfully.
Page 502: Usb Control Register (Usb_Ctrl)
Bit Field Name Description 3：0 EPADDR[3:0] Endpoint address This bit indicates the destination endpoint of the communication and must be written before enabling the corresponding endpoint. Note: 、 When the USB module receives the USB bus reset signal, or USB_CTRL.FRST = 1, the USB module will be reset. Except for the CTRS_RX and CTRS_TX bits that remain unchanged to process the following USB transfer, all other bits are reset.
Page 503 Bit Field Name Description interrupt is generated. ERRORM Error interrupt enable 0: Disable error interrupt 1: Enable error interrupt, when USB_STS.ERROR = 1, an interrupt will be generated. WKUPM Wake-up interrupt enable 0: Disable wake-up interrupt 1: Enable wake-up interrupt, when USB_STS.WKUP = 1, an interrupt will be generated.
Page 504: Usb Interrupt Status Register (Usb_Sts)
Bit Field Name Description 、 In low power mode, only the external pull-up resistor is used for power supply, and the system clock will also be stopped or reduced to a certain frequency to reduce power consumption. Power-down mode 0: Exit power-down mode 1: Enter power-down mode Note: When USB_CTRL.PD = 1, the USB module is completely shut down, disconnected from the host, and the USB module will not work.
Page 505 Bit Field Name Description Bit stuffing error, bit stuffing error detected in PID, data or CRC Frame format error, non-standard frame received Note: Software can read and write this bit, but only writing 0 is valid, writing 1 is invalid. WKUP Wake-up interrupt flag In the suspend state, when the wake-up signal is detected, the hardware sets this bit,...
Page 506: Usb Frame Number Register (Usb_Fn)
Bit Field Name Description Note: 、 Software can only read this bit, not write this bit. 、 When USB_EPn.CTRS_TX and USB_EPn.CTRS_RX are set at the same time, it indicates that there are OUT group and IN group at the same time. 3：0 EP_ID[3:0] Endpoint number...
Page 507: Usb Device Address Register (Usb_Addr)
Bit Field Name Description Hardware increments this bit every time the USB module receives a PID SOF token packet. 19.5.6 USB device address register (USB_ADDR) Address offset: 0x4C Reset value: 0x0000 0000 Bit Field Name Description 31:8 Reserved Reserved, the reset value must be maintained. EFUC USB module enable 0: The USB module stops working and does not respond to any USB communication...
Page 508: Buffer Description Table
Buffer description table The buffer description table is located in the packet buffer memory and is used to configure the address and size of the endpoint packet buffer shared by the USB module and the microcontroller core. Since the APB1 bus is addressed by 32 bits, the data packet buffer memory addresses use 32-bit aligned addresses, not the addresses used by the USB_BUFTAB register and the buffer description table.
Page 509: Receive Buffer Address Register N (Usb_Addrn_Rx)
19.6.3 Receive buffer address register n (USB_ADDRn_RX) Address offset: [USB_ BUFTAB] + n×16 + 8 USB local address: [USB_ BUFTAB] + n×8 + 4 Bit Field Name Description 15:1 ADDRn_RX[14:0] Receive buffer address Endpoint packet buffer start address for the endpoint to hold data when the next PID SETUP or OUT token packet is received Since packet buffer memory addresses are word (32-bit) aligned, this bit must be 0 19.6.4 Receive data byte number register n (USB_CNTn_RX)
Page 510: Table 19-8 Endpoint Packet Receive Buffer Size Definition
Table 19-8 Endpoint packet receive buffer size definition NUM_BLK[4:0] BLSIZE = 0 BLSIZE = 1 00000 Not allowed 32 bytes 00001 2 bytes 64 bytes 00010 4 bytes 96 bytes 00011 6 bytes 128 bytes … … … 01111 30 bytes 512 bytes 10000 32 bytes...
Page 511: Controller Area Network (Can)
Controller area network (CAN) Introduction to CAN As CAN network interface, basic extended CAN supports CAN protocols 2.0A and 2.0B. It can efficiently process a large number of received messages and greatly reduce the consumption of CPU resources. The priority characteristics of message sending can be configured by software, and the hardware function of CAN can support time-triggered communication mode for some applications with high security requirements.
Page 512: Can Overall Introduction
CAN overall introduction With the wide application of CAN, the nodes of CAN network are growing rapidly. Multiple CAN nodes are connected through CAN network. With increase number of CAN nodes, messages in CAN network also increase dramatically which will occupides lots of CPU resource. In this CAN controller, receive FIFOs and filter mechanism are added as hardware support for CPU message processing and reduce real-time response requirement of CAN message.
Page 513: Normal Mode
or sleep mode. The software reads values of the CAN_MSTS.INIAK or CAN_MSTS.SLPAK bit to confirm whether the initialization or sleep mode is entered, at this time the internal pull-up resistor of the CANTX pin is disabled. CAN is in normal mode when CAN_MSTS.INIAK and CAN_MSTS.SLPAK bits are both '0', and it must synchronize with CAN bus to enter normal mode.
Page 514: Send Mailbox
the software must clear the CAN_MCTRL.SLPRQ bit to exit the sleep state. If the wake-up interrupt (set the CAN_INTE.WKUITE bit) is enabled, the wake-up interrupt will be generated once the CAN bus activity is detected, regardless of whether the hardware is enabled to automatically wake up CAN. The CAN must be synchronized with the CAN bus before entering Normal mode Wait until the CAN_MSTS.SLPAK bit cleared to confirm the sleep mode has exited.Please refer to Figure 20-2.
Page 515: Figure 20-3 Dual Can Block Diagram
Figure 20-3 Dual CAN block diagram CAN1 with 512 bytes SRAM CAN1 Transmit Mailbox 0 CAN1 Transmit CAN1 Transmitter Mailbox 1 CAN1 Transmit Mailbox 2 CAN1 CAN1- Memory CTRL Access Controller CAN1 Receive FIFO0 Mailbox 0 Mailbox 1 Mailbox 2 CAN1 Acceptance Filter CAN1 Receive FIFO1 Mailbox 0...
Page 516: Can Test Mode
20.3.6 CAN Test mode In the initialization mode, a test mode must be selected by combining the CAN_BTIM.SLM bit and CAN_BTIM.LBM bit. After selecting a test mode, the software needs to clear the CAN_MCTRL.INIRQ bit to exit the initialization mode and enter the test mode. Loopback mode Loopback mode can be used for self-test.
Page 517: Figure 20-5 Silent Mode
Figure 20-5 silent mode CAN-CTRL transceiver CAN_Bus Loopback silence mode In loopback silent mode, the CANRX pin is disconnected from the CAN bus, while the CANTX pin is driven to the recessive bit state. It can be used for "Run-time self diagnose" just like CAN can be tested in loop-back mode, but not affect the whole CAN system connected by CANTX and CANRX.
Page 518: Can Debugging Mode
20.3.7 CAN Debugging mode CAN can continue to work normally or stop working according to the state of the following configuration bits: • DBG_CTRL.CAN1_STOP bit of CAN1 and DBG_CTRL.CAN2_STOP bit of CAN2 in the debug support(DBG) module.See paragraph 29.3.2 Section: Peripheral debugging support. •...
Page 519: Time Triggered Communication Mode
will be aborted immediately. If the mailbox is in the transmitting state, the request to abort may lead to two kinds of results: • if the message in the mailbox fails to be sent, the mailbox becomes ready state, then the sending request is aborted, the mailbox becomes an empty mailbox and the CAN_TSTS.TXOKM bit is cleared;...
Page 520: Receiving Management
20.4.4 Receiving management FIFOs with 3 levels depth are used to store received messages. When the application reads the FIFO output mailbox, it reads the first received message in the FIFO. FIFO is completely managed by hardware, which can simplify the application program, ensure the consistency of data and reduce the processing time of CPU.
Page 521: Identifier Filtering
bit is decremented by 1 until it is 0. Receive related interrupts The hardware will update the CAN_RFF.FFMP[1:0] bits when a message is stored in the receiving FIFO. If the FIFO message pending interrupt is currently enabled (the CAN_INTE.FMPITE bit is set), then the FIFO message pending interrupt request will be generated.
Page 522: Mask Mode
Figure 20-9 Filter bit width setting-register organization 32 bit Mask Mode(CAN_FS1.FSCx = 1;CAN_FM1.FBx = 0) USER ID STDID[10:0]/EXTID[28:18] EXTID[17:0] FiR1 Register filter ID FBC[31:21] FBC[20:3] FBC2 FBC1 FBC0 FiR2 Register filter filter Mask FBC[31:21] FBC[20:3] FBC2 FBC2 FBC2 32 bit List Mode(CAN_FS1.FSCx = 1;CAN_FM1.FBx = 1) USER ID STDID[10:0]/EXTID[28:18] EXTID[17:0]...
Page 523: Table 20-1 Examples Of Filter Numbers
be used to store one more filter ID. However, at this time, the identifier of the message needs to be exactly the same as the filter ID format, otherwise it will fail to pass the filter. Filter matching sequence number After CAN core received an valid message it will matching the message ID with filters one by one until there is one filter pass or all filters failed.
Page 524: Message Storage
16 bit mask mode 10/11 32 bit list mode 12/13 Filter priority rule According to different configurations of filters, it is possible that a message identifier can be filtered by multiple filters; In this case, the filter matching serial number stored in the receiving mailbox is first determined according to bit width,32-bit-wide filters have higher priority than 16-bit-wide filters.
Page 525: Bit Time Characteristic
CAN_TMIx CAN_TMDTx CAN_TMDLx CAN_TMDHx Receiving mailbox (FIFO) CAN_RMDTx.FMI[7:0] field can store the filter matching serial number and CAN_RMDTx.MTIM[15:0] field can store the 16-bit timestamp.The software can access the output mailbox of the receiving FIFO to read the received message. Once the software has processed the message, such as reading it out, the software should set the CAN_RFFx.RFFOM bit to release the corresponding, so as to reserve storage space for later messages.
Page 526: Figure 20-11 Bit Sequence
Notes: (1) The time characteristics and resynchronization mechanism of CAN bits are detailed in the ISO11898 standard. (2) In order to improve the CAN bit time accuracy, it is not recommended to use HSI as the clock source. Figure 20-11 Bit sequence One-bit time SYNC_SEG PROP_SEG 1...
Page 527: Figure 20-12 Various Can Frames
Figure 20-12 Various CAN frames 2bit Arbitration Field 12bit Ctrl Field 6bit Data Field 8*Nbit CRC Field 16bit 7bit ID[10:0] Data[N] Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) 44 + 8 * Nbit or Overload Frame CRC Field 16bit 2bit Arbitration Field 32bit Ctrl Field 6bit Data Field 8*Nbit...
Page 528: Can Interrupt
CAN interrupt Figure 20-13 Event flag and interrupt generation FMPITE0 FFMP0 CAN_RX0_IRQn FFITE0 FFULL0 FOVITE0 FFOVR0 FMPITE1 FFMP1 CAN_RX1_IRQn FFITE1 FFULL1 FOVITE1 FFOVR1 CAN_TX_IRQn RQCPM0 TMEITE CAN_ RQCPM1 TSTS RQCPM2 ERRITE EWGITE EWGFL EPVITE EPVFL ERRINT BOFITE BOFFL CAN_MSTS LECITE CAN_SCE_IRQn 1 LEC 6 WKUITE...
Page 529: Error Management
Send mailbox x becomes empty, and the corresponding CAN_TSTS.RQCPMx bit is set(x=1/2/3). • Error and status change interrupt(CAN_SCE_IRQn): CAN enters sleep mode; Wake-up condition, the start of frame bit (SOF) is monitored on the CAN receiving pin. Error condition, please refer to the CAN error status register (CAN_ESTS) for details of the error. 20.5.1 Error management As described in CAN protocol, the error management is completely realized by hardware through sending error counter (CAN_ESTS.TXEC field) and receiving error counter (CAN_ESTS.RXEC field).
Page 530 • Preparation Stage: 1. Configure RCC to enable CAN clock 2. Configure RCC to enable AFIO and GPIO clock 3. Write into GPIO registers to map CAN TX and CAN RX signals to desired GPIO pins. • Basic Configuration Stage: 1.
Page 531: Can Register File
Once CAN has received message and stored them inside reception FIFO, user needs to read the corresponding FIFO on time and release reception mailbox by writing ‘1’ to RFFOMx in register CAN_RFFx (x = 0,1). CAN Register File These peripheral registers must be operated as words (32 bits). 20.7.1 Register Description Register access protection When a CAN node is working normally, incorrect access/modification of some configuration registers may cause...
Page 532 Offset Register CAN_MSTS 004h Reset Value CAN_TSTS 008h Reset Value CAN_RFF0 00Ch Reset Value CAN_RFF1 010h Reset Value CAN_INTE 014h Reset Value CAN_ESTS RXEC[7:0] TXEC[7:0] 018h Reset Value CAN_BTIM TBS2[2:0] TBS1[3:0] BRTP[9:0] 01Ch Reset Value 020h 17Fh CAN_TMI0 STDID[10:0]/EXTID[28:18] EXTID[17:0] 180h Reset Value CAN_TMDT0...
Page 533 Offset Register CAN_TMDH1 DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 19Ch Reset Value CAN_TMI2 STDID[10:0]/EXTID[28:18] EXTID[17:0] 1A0h Reset Value CAN_TMDT2 MTIM[15:0] DLC[3:0] 1A4h Reset Value CAN_TMDL2 DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 1A8h Reset Value CAN_TMDH2 DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 1ACh Reset Value CAN_RMI0 STDID[10:0]/EXTID[28:18] EXTID[17:0] 1B0h Reset Value...
Page 534 Offset Register CAN_FM1 FB[13:0] 204h Reset Value 208h CAN_FS1 FSC[13:0] 20Ch Reset Value 210h CAN_FFA1 FAF[13:0] 214h Reset Value 218h CAN_FA1 FAC[13:0] 21Ch Reset Value 220h 224h 23Fh CAN_F0B1 FBC[31:0] 240h Reset Value CAN_F0B2 FBC[31:0] 244h Reset Value CAN_F1B1 FBC[31:0] 248h Reset Value CAN_F1B2...
Page 535: Can Control And Status Register
20.7.3 CAN control and status register Abbreviations used in register descriptions, please refer to 1.1 section. CAN master control register (CAN_MCTRL) Address offset: 0x00 Reset value: 0x0001 0002 Bit Field Name Description 31:17 Reserved Reserved, the reset value must be maintained. DBGF Debug freeze 0: During debugging, CAN works as usual.
Page 536 Bit Field Name Description This bit determines whether CAN is awakened by hardware or software when it is in sleep mode. 0: The sleep mode is awakened by the software by clearing the CAN_MCTRL.SLPRQ bit; 1: Sleep mode is automatically awakened by hardware by detecting CAN messages.
Page 537 Reset value: 0x0000c02 Bit Field Name Description 31:12 Reserved Reserved, the reset value must be maintained. CAN Rx signal This bit reflects the actual level of the CAN receive pin (CAN_RX). LSMP Last sample point The last sampled value of the CAN receive pin (corresponding to the value of the current receive bit).
Page 538 Bit Field Name Description and entering normal mode,it needs to be synchronized with CAN bus). Synchronization with CAN bus here means that the hardware needs to detect 11 consecutive recessive bits on the RX pin of CAN. Notes: clearing CAN_MCTRL.SLPRQ bit by software or hardware will start the process of exiting sleep mode.
Page 539 Bit Field Name Description When at least one sending mailbox is empty, these two bits represent the next empty sending mailbox number. When all sending mailboxes are empty, these two bits represent the sending mailbox number with the lowest priority. ABRQM2 Abort request for mailbox 2 Set this bit, software can stop the sending request of mailbox 2, and hardware...
Page 540 Bit Field Name Description When the last request (send or abort) for mailbox 1 is completed, the hardware sets this bit. Writing '1' to this bit by software can clear it; When the hardware receives the send request, it can also clears this bit (the CAN_TMI1.TXRQ bit is set). When this bit is cleared, other sending status bits (CAN_TSTS.TXOKM1, CAN_TSTS.ALSTM1 and CAN_TSTS.TERRM1 bits) of mailbox 1 are also cleared.
Page 541 Bit Field Name Description RFFOM0 Release FIFO 0 output mailbox. The software releases the output mailbox of the receive FIFO by setting this bit. If the receiving FIFO is empty, it will have no effect on setting this bit, that is, it will be meaningful to set this bit only when there is a message in the FIFO.
Page 542 Bit Field Name Description FFULL1 FIFO 1 full When there are 3 messages in FIFO 1, the hardware sets this bit. This bit is cleared by software. Reserved Reserved, the reset value must be maintained. FFMP1[1:0] FIFO 1 message pending Number of messages in FIFO 1 These two bits reflect the number of messages stored in the current receiving FIFO 1.
Page 543 Bit Field Name Description EPVITE Error passive interrupt enable 0: when CAN_ESTS.EPVFL bit is set, CAN_MSTS.ERRINT bit is not set; 1: when CAN_ESTS.EPVFL bit is set, set the CAN_MSTS.ERRINT bit. EWGITE Error warning interrupt enable 0: When CAN_ESTS.EWGFL bit is set, CAN_MSTS.ERRINT bit is not set; 1: when the CAN_ESTS.EWGFL bit is set, set the CAN_MSTS.ERRINT bit.
Page 544 Bit Field Name Description mechanism of CAN protocol. According to the standard of CAN, when receiving error, the counter is incremented by 1 or incremented by 8 according to the error condition; After each successful reception, the counter is decremented by 1, or when the value of the counter is greater than 127, its value is set to 120.
Page 545: Can Mailbox Register
Notes: This register CAN only be accessed by software when CAN is in initialization mode. Bit Field Name Description Silent mode（debug） 0: Normal state; 1: Silent mode. Loop back mode（debug） 0: Loopback mode is prohibited; 1: Loopback mode is allowed. 29:26 Reserved Reserved, the reset value must be maintained.
Page 546 Bit Field Name Description 31:21 STDID[10:0]/EXTID[28:18] Standard identifier or extended identifier Depending on the content of CAN_TMIx.IDE bits, these bits are either standard identifiers or high bytes of extended identity. 20:3 EXTID[17:0] Extended identifier Low byte of extended identity. Identifier extension. This bit determines the type of identifier used for sending messages in the mailbox.
Page 547 Bit Field Name Description 0: Do not send the time stamp CAN_TMDTx.MTIM[15:0]; 1: send the time stamp CAN_TMDTx.MTIM[15:0]. In a message of length 8, the time stamp CAN_TMDTx.MTIM[15:0] is the last two bytes sent: CAN_TMDTx.MTIM[7:0] is the seventh byte and CAN_TMDTx.MTIM[15:8] is the eighth byte.
Page 548 Bit Field Name Description 31:24 DATA7[7:0] Data byte 7 Data byte 7 of the message. Notes: If the CAN_MCTRL.TTCM bit is '1' and the CAN_TMDTx.TGT bit of this mailbox is also '1', then DATA7 and DATA6 will be replaced by TIME stamps. 23:16 DATA6[7:0] Data byte 6...
Page 549 Bit Field Name Description Reserved Reserved, the reset value must be maintained. Receive FIFO mailbox data length and time stamp register(CAN_RMDTx)( x=0..1) Address offset: 0x1B4, 0x1C4 Reset value: undefined Notes: All receiving mailbox registers are read-only. Bit Field Name Description 31:16 MTIM[15:0] Message time stamp...
Page 550: Can Filter Register
Bit Field Name Description Data byte 1 of the message. DATA0[7:0] Data byte 0 Data byte 0 of the message. Notes: the message contains 0 to 8 bytes of data, starting from byte 0. Receive FIFO mailbox high byte data register(CAN_RMDHx) (x=0..1) Address offset: 0x1BC, 0x1CC Reset value: undefined Note: All receiving mailbox registers are read-only.
Page 551 Bit Field Name Description Initialization mode settings for all filter groups. 0: The filter group works in normal mode; 1: The filter group works in initialization mode. CAN filter mode register (CAN_FM1) Address offset: 0x204 Reset value: 0x0000 0000 Notes: You can only write to this register when you set CAN_FMC.FINITM bit and put the filter in initialization mode.
Page 552 CAN filter FIFO assignment register (CAN_FFA1) Address offset: 0x214 Reset value: 0x0000 0000 Notes: You can only write to this register when you set CAN_FMC.FINITM bit and put the filter in initialization mode. Bit Field Name Description 31:28 Reserved Reserved, the reset value must be maintained. 13:0 FAFx Filter FIFO assignment for filter x...
Page 553 Only when the corresponding CAN_FA1.FACx bit is cleared or the CAN_FMC.FINIT bit is set, the corresponding filter register can be modified. Bit Field Name Description 31:0 FBC[31:0] Filter bits Identifier pattern Each bit of the register corresponds to the level of the corresponding bit of the expected identifier.
Page 554: Serial Peripheral Interface/Inter-Ic Sound (Spi/ I 2 S)
Serial peripheral interface/Inter-IC Sound (SPI/ I Introduction This module is about SPI/I2S. It works in SPI mode by default and users can choose to use I2S by setting the value of registers. Serial peripheral interface (SPI) is able to work in master or slave mode, support full-duplex and simplex high-speed communication mode, and have hardware CRC calculation and configurable multi-master mode.
Page 555: Spi Function Description
SPI function description 21.3.1 General description Figure 21-1 SPI block diagram address and data bus Read Receive buffer MOSI LSBFF SPI_CTRL2 control bit Shift register SSOEN TDMAEN RDMAEN MISO INTEN INTEN INTEN SPI_STS Send buffer BUSY OVER MODERR UNDER CHSIDE Write Communication circuit LSBFF...
Page 556: Figure 21-2 Selective Management Of Hardware/Software
The NSS pin is not used in software NSS mode. In this mode the internal NSS signal level is driven by writing the SPI_CTRL1.SSEL bit (master mode SPI_CTRL1.SSEL = 1, slave mode SPI_CTRL1.SSEL = 0). Hardware NSS mode The software slave device management is disabled when SPI_CTRL1.SSMEN = 0. NSS input mode: The NSS output of the master device is disabled (SPI_CTRL1.MSEL = 1, SPI_CTRL2.SSOEN = 0), allowing operation in multi-master mode.
Page 557: Figure 21-3 Master And Slave Applications
Figure 21-3 Master and slave applications Slave Master MSBit MSBit LSBit LSBit MISO 8-bit shift register 8-bit shift register MOSI SPI clock generator NSS(1) NSS(1) Not used if NSS is managed by software Note: NSS pin is set as input SPI is a ring bus structure.
Page 558: Data Format
Figure 21-4 Data clock timing diagram CLKPHA=1 CLKPOL=1 CLKPOL=0 MISO （from master） SPI_CTRL1 determines whether the data frame format is 8 or 16 bits MISO （from slave）（to slave） Capture strobe CLKPHA=0 CLKPOL=1 CLKPOL=0 MISO （from master） SPI_CTRL1 determines whether the data frame format is 8 or 16 bits MISO （from slave）...
Page 559: Figure 21-5 Schematic Diagram Of The Change Of Te/Rne/Busy When The Host Is Continuously Transmitting In
Set SPI_CTRL1.SPIEN = 1, Enable SPI module. Write the first data to be sent into SPI_DAT register (this operation will clear SPI_STS.TE bit). Wait for SPI_STS.TE bit to be set to '1', and write the second data to be sent into SPI_DAT. Wait for SPI_STS.RNE bit to be set to '1', read SPI_DAT to get the first received data, and the SPI_STS.RNE bit will be cleared by hardware while reading SPI_DAT.
Page 560: Figure 21-6 Schematic Diagram Of Te/Busy Change When The Host Transmits Continuously In One-Way Only
After writing the last data to SPI_DAT, wait for SPI_STS.TE bit to set '1'; then wait for SPI_STS.BUSY bit to be cleared to complete the transmission of all data. The process of data sending can also be implemented in the interrupt handler generated by the rising edge of the TE flag.
Page 561 RONLY = 1) Configure：CLKPOL=1.CLKPHA=1,RONLY=1 DATA1=0xAA DATA2=0xBB DATA3=0xCC MISO/MOSI （in） Set by hardware Clear by software RNE flag Rx buffer 0xAA 0xBB 0xCC （read fromSPI_DAT） Wait until RNE=1,read 0xAA from SPI_DAT Wait until RNE=1,read 0XBB from SPI_DAT Wait until RNE=1,read 0xCC from SPI_DAT •...
Page 562: Figure 21-8 Schematic Diagram Of The Change Of Te/Rne/Busy When The Slave Is Continuously Transmitting In
Figure 21-8 Schematic diagram of the change of TE/RNE/BUSY when the slave is continuously transmitting in full duplex mode Slave mode：CLKPOL=1.CLKPHA=1 DATA1=0x11 DATA2=0x22 DATA3=0x33 MISO/MOSI (out) TE flag Set by hardware Clear by software Tx buffer 0x11 0x22 0x33 （write to SPI_DAT） The flag set/clear by hardware BUSY flag DATA1=0xAA...
Page 563 SPI_CTRL1.BIDIROEN = 1) When the slave device receives the first edge of the clock signal, the sending process starts. No data is received in this mode, and the software must ensure that the data to be sent has been written in the SPI_DAT register before the SPI master device starts data transmission.
Page 564: Status Flag
In some configurations, when the last data is sent, the BUSY flag (SPI_STS.BUSY) can be used to wait for the end of the data sending. Continuous and discontinuous transmission. When sending data in master mode, if the software is fast enough to detect each TE (SPI_STS.TE) rising edge (or TE interrupt), and the data is written to the SPI_DAT register immediately before the end of the ongoing transmission.
Page 565: Disabling The Spi
Only when the device is in the master one-wire bidirectional receive mode, the BUSY flag (SPI_STS.BUSY) will be set to 0 when the communication is in progress. The BUSY flag (SPI_STS.BUSY) will be cleared to 0 in the following cases: •...
Page 566: Spi Communication Using Dma
21.3.5 SPI communication using DMA Users can choose DMA for SPI data transfer, the application program can be released, and the system efficiency can be greatly improved. When the send buffer DMA is enabled (SPI_CTRL2.TDMAEN = 1), each time the TE flag (SPI_STS.TE) bit is 1, a DMA request will be generated, and the DMA will automatically write the data to the SPI_DAT register, which will clear the TE flag (SPI_STS.TE) bit.
Page 567: Crc Calculation
Figure 21-12 Reception using DMA CLKPOL=1.CLKPHA=1 DATA1=0xAA DATA2=0xBB DATA3=0xCC MISO/MOSI (in) Clear by DMA RNE flag Set by hardware read Rx buffer 0xAA 0xBB 0xCC （read from SPI_DAT） DMA request DMA read from SPI_DAT DMA flag Set by hardware Clear by software （DMA transfer complete）...
Page 568: Spi Interrupt
The following two conditions will cause the master mode failure error: • NSS pin hardware management mode, the master device NSS pin is pulled low; • NSS pin software management mode, the SPI_CTRL1.SSEL bit is set to 0. When a master mode failure error occurs, the SPI_STS.MODERR bit is set to 1. An interrupt is generated if the user enables the corresponding interrupt (SPI_CTRL2.ERRINTEN = 1).
Page 569: I Sfunction Description
S function description The block diagram of I2S is shown in the figure below: Figure 21-13 I S block diagram Address and data bus Tx buffer SPI_STS MODER BUSY OVER UNDER CHSIDE MOSI/SD 16-bit LSBFF control bit Shift register MISO 16-bit Communication circuit Rx buffer...
Page 570: Supported Audio Protocols
Note: F is the sampling frequency of audio signal In master mode, I2S uses its own clock generator to generate clock signals for communication, and this clock generator is also the clock source of the master clock output (SPI_I2SPREDIV.MCLKOEN = 1, the master clock output is enabled).
Page 571: Figure 21-14 I 2 S Philips Protocol Waveform (16/32-Bit Full Precision, Clkpol = 0)
Figure 21-14 I S Philips protocol waveform (16/32-bit full precision, CLKPOL = 0) Receive Send Left channel (data format 16-bit or 32-bit) Right channel Figure 21-15 I S Philips protocol standard waveform (24-bit frame, CLKPOL = 0) Recieve Send The remaining 8 bits are forced to 0 24-bit data...
Page 572 Figure 21-16 I S Philips protocol standard waveform (16-bit extended to 32-bit packet frame, CLKPOL = 0) Recieve Send The remaining 16 bits are forced to 0 16-bit data Right channel Left channel 32-bit data If 16-bit data needs to be packed into 32-bit data frame format, the CPU only needs to read or write the SPI_DAT register once for each frame of data transmission.
Page 573: Figure 21-17 The Msb Is Aligned With 16-Bit Or 32-Bit Full Precision, Clkpol = 0
Figure 21-17 The MSB is aligned with 16-bit or 32-bit full precision, CLKPOL = 0. Send Receive Left channel (16-bit or 32-bit) Right Channel Figure 21-18 MSB aligns 24-bit data, CLKPOL = 0 Send Receive 8-bit remaining 0 forced 24-bit data Right channel Left channel 32-bit Figure 21-19 MSB-aligned 16-bit data is extended to 32-bit packet frame, CLKPOL = 0...
Page 574: Figure 21-20 Lsb Alignment 16-Bit Or 32-Bit Full Precision, Clkpol = 0
LSB alignment standard In 16-bit or 32-bit full-precision frame format, LSB alignment standard is the same as MSB alignment standard. Figure 21-20 LSB alignment 16-bit or 32-bit full precision, CLKPOL = 0 Send Receive Left channel (16-bit or 32-bit) Right channel Figure 21-21 LSB aligns 24-bit data, CLKPOL = 0 Send Receive...
Page 575: Figure 21-22 Lsb Aligned 16-Bit Data Is Extended To 32-Bit Packet Frame, Clkpol = 0
Figure 21-22 LSB aligned 16-bit data is extended to 32-bit packet frame, CLKPOL = 0 Send Receive 16-bit data forced 0 16-bit data Right channel Left channel 32-bit If the 16-bit data needs to be packaged into a 32-bit data frame format, the CPU only needs to read or write the SPI_DAT register once for each frame of data transmission.
Page 576: Clock Generator
Figure 21-23 PCM standard waveform (16 bits) WS short frame WS long frame 13-bit 16-bit Figure 21-24 PCM standard waveform (16-bit extended to 32-bit packet frame) WS short frame WS long frame 13-bit 16-bit 21.4.2 Clock generator In the master mode, the linear divider needs to be set correctly in order to obtain the desired audio frequency. 576 / 816...
Page 577: Figure 21-25 I 2 S Clock Generator Structure
Figure 21-25 I S clock generator structure MCLK 8-bit Linear Divider Divider Divider + by 2 by 4 reshaping I2Sx CLK stage MCLKOEN ODD_ MCLK LDIV[7:0] BITS EVEN Note: The clock source of I Sx CLK is HSI, HSE or PLL system clock that drives AHB clock. The bit rate of I2S determines the data flow on the I2S data line and the frequency of the I2S clock signal.
Page 578: I 2 S Transmission And Reception Sequence
Table 21-2 Use the standard 8MHz HSE clock to get accurate audio frequency. SYSCLK S_LDIV S_ODD_EVEN Target Real F (Hz) Error MCLK (Hz) （MHz） 16 bits 32 bits 16 bits 32 bits 16 bits 32 bits 16 bits 32 bits without 96000 97826.09...
Page 579 The sending process begins when data is written to the send buffer. When the data of the current channel is moved from the send buffer to the shift register in parallel, the flag bit TE (SPI_STS.TE) is set to '1'. At this time, the data of the other channel should be written into SPI_DAT.
Page 580: Status Flag
Wait for the penultimate RNE flag (SPI_STS.RNE) bit to be set to' 1'. Software delay, waiting for 17 I S clock cycles. Turn off I S (SPI_I2SCFG.I2SEN = 0). • The data length is 16 bits, the channel length is 32 bits (SPI_I2SCFG.TDATLEN = 00 and SPI_I2SCFG.CHBITS = 1), the MSB alignment standard (SPI_I2SCFG.STDSEL = 01), I S Philips standard (SPI_I2SCFG.STDSEL = 00) or PCM standard (SPI_I2SCFG.STDSEL = 11)
Page 581: Error Flag
receiving of each data item. Channel Side flag (CHSIDE) The CHSIDE (SPI_STS.CHSIDE) bit is used to indicate the channel where the data currently sent and received is located. Under the PCM standard, this flag has no meaning. In send mode, the flag is updated when the TE flag (SPI_STS.TE) is set; in receive mode, the flag is updated when the RNE flag (SPI_STS.RNE) is set.
Page 582: Spi And I 2 Sregister
SPI and I S register 21.5.1 SPI register overview Table 21-4 SPI register overview Offset Register SPI_CTRL1 BR[2:0] 000h Reserved Reset Value SPI_CTRL2 004h Reserved Reset Value SPI_STS 008h Reserved Reset Value SPI_DAT DAT[15:0] 00Ch Reserved Reset Value SPI_CRCPOLY CRCPOLY[15:0] 010h Reserved Reset Value...
Page 583 Bit field name describe BIDIROEN Output enable in bidirectional mode 0: Output disable (receive-only mode). 1: Output enabled (send-only mode). In master mode, the "one-wire" data line is the MOSI pin, and in slave mode, the "one-wire" data line is the MISO pin. Note: Not used in I S mode.
Page 584: Spi Control Register 2 (Spi_Ctrl2)
Bit field name describe LSBFF Frame format 0: Send MSB first. 1: Send LSB first. Note: This bit cannot be changed during communication. Note: Not used in I S mode. SPIEN SPI enable 0: Disable SPI device. 1: Enable the SPI device. Note: Not used in I S mode.
Page 585: Spi Status Register (Spi_Sts)
Bit field name describe 15:8 Reserved Reserved, the reset value must be maintained. TEINTEN Send buffer empty interrupt enable 0: Disable TE interrupt. 1: Enable TE interrupt, and interrupt request is generated when TE flag (SPI_STS.TE) is set to '1'. RNEINTEN Receive buffer non-empty interrupt enable 0: Disable RNE interrupt.
Page 586: Spi Data Register (Spi_Dat)
Bit field name describe BUSY Busy flag 0: SPI is not busy. 1: SPI is busy communicating or the send buffer is not empty. This bit is set or reset by hardware. Note: special attention should be paid to the use of this sign, see Section 21.3.3 and Section 21.3.4 for details..
Page 587: Spi Crc Polynomial Register (Spi_Crcpoly) (Not Used In I S Mode)
Bit field name describe 15:0 DAT[15:0] Data register Data to be sent or received The data register corresponds to two buffers: one for write (send buffer); The other is for read (receive buffer).Write operation writes data to send buffer; The read operation will return the data in the receive buffer.
Page 588: Spi Tx Crc Register Spi_Crctdat
15:0 CRCRDAT Receive CRC register When CRC calculation is enabled, CRCRDAT[15:0] will contain the calculated CRC value of subsequent received bytes. This register is reset when ‘1’ is written to the SPI_CTRL1.CRCEN bit. The CRC calculation uses the polynomial in SPI_CRCPOLY. When the data frame format is set to 8 bits, only the lower 8 bits participate in the calculation and follow the CRC8 standard;...
Page 589 Bit field Name Description Note: this bit can only be set when SPI or I S is turned off. S enable 0: Disable I 1: Enable I Note: not used in SPI mode. MODCFG S mode setting 00: Slave device sends. 01: Slave device receives.
Page 590: Spi_I S Prescaler Register (Spi_I2Sprediv)
Bit field Name Description CHBITS Channel length (number of data bits per audio channel) 0: 16 bits wide; 1: 32 bits wide. Writing to this bit is meaningful only when SPI_I2SCFG.TDATLEN = 00, otherwise the channel length is fixed to 32 bits by hardware. Note: For correct operation, this bit can only be set when I S is turned off.
Page 591: I 2 C Interface
C interface Introduction I2C(Inter-Integrated Circuit) bus is a widely used bus structure, it has only two bidirectional lines, namely data bus SDA and clock bus SCL. All devices compatible with I2C bus can communicate directly with each other through I2C bus with these two lines.
Page 592: Software Communication Process
to a current source or the positive of the power supply with a pull-up resistor. When the bus is idle, both lines are high level. The output of device which is connected to the bus must have open drain or open collector to provide wired-AND functionality.
Page 593: Figure 22-1 I 2 C Functional Block Diagram
Figure 22-1 I C functional block diagram Data Shift register Data register GPIO control Own address register Comparator calculation Dual address register PEC register Clock Clock Control Register control GPIO Control Register Control SMBALERT logic Status Register Interrupts DMA requests Note: in SMBus mode, SMBALERT is an optional signal.
Page 594: Clock Synchronization
concurrently when the bus is inactive. So some mechanisms are needed to grant a master the access to the bus. This process is generally named Clock Synchronization and Arbitration. I2C module has two key features: • SDA and SCL are drain open circuit structures, and the signal "wire-and" logic is realized through an external pull-up resistor.
Page 595 The I2C host is responsible for generating the start bit and the end bit in order to start and end a transmission. And is responsible for generating the SCL clock. The I2C module supports 7-bit and 10-bit addresses, and the user can configure the address of the I2C slave through software.
Page 596: Figure 22-3 Slave Transmitter Transfer Sequence Diagram
I2C_STS1.TXDATE bit is set after the second last byte is sent until the stop end bit is detected. 7. According to the I2C protocol, the I2C master will not send a ACK to the last byte received. Therefore, after the last byte is sent, the I2C_STS1.ACKFAIL bit (acknowledge fail) of the I2C slave will be set to notify the software of the end of sending.
Page 597: Figure 22-4 Slave Receiver Transfer Sequence Diagram
The software should check this bit by polling or interrupt. Once it is found that it is set, the software can read the first byte of I2C_DAT register, and then the I2C_STS1.RXDATNE bit is cleared to 0. Note that if the I2C_CTRL1.ACKEN bit is set, after receiving a byte,the slave should generate a response pulse.
Page 598 switch to the master mode (I2C_STS2.MSMODE bit set to “1”). Once the start condition is issued, I2C hardware will set I2C_STS1.STARTBF bit(START bit flag)and then enters the master mode. If the I2C_CTRL2.EVTINTEN bit is set, an interrupt will be generated. Then the software reads the I2C_STS1 register and then writes a 7-bit address bit or a 10-bit address bit with an address header to the I2C_DAT register to clear the I2C_STS1.STARTBF bit.
Page 599: Figure 22-5 Master Transmitter Transfer Sequence Diagram
bit. The software sets the I2C_CTRL1.STOPGEN bit at this time to generate a stop condition, and then the I2C interface will automatically return to the slave mode (I2C_STS2.MSMODE bit is cleared). Figure 22-5 Master transmitter transfer sequence diagram 7-bit address Master Master Master...
Page 600 Once the start condition is issued, the I2C hardware sets I2C_STS1.STARTBF(start bit flag) and enters the host mode. If the I2C_CTRL2.EVTINTEN bit is set to 1, an interrupt will be generated. Then the software reads the I2C_STS1 register and then writes a 7-bits address or a 10-bits address with an address header to the I2C_DAT register, in order to clear the I2C_STS1.STARTBF bit.
Page 601: Figure 22-6 Master Receiver Transfer Sequence Diagram
In order to generate a NACK pulse after receiving the last byte, the software should clear the I2C_CTRL1.ACKEN bit immediately after receiving the penultimate byte (N-1). In order to generate a stop/restart condition, the software must set the I2C_CTRL1.STOPGEN bit or I2C_CTRL1.STARTGEN to 1 after reading the penultimate data byte.
Page 602: Error Conditions Description
(3) The EV7 software sequence shall be completed before the end of the current byte transmission. (4) The software sequence of EV6_1 or EV7_1 shall be completed before the ACK pulse of the current transmission byte. Error conditions description 22.3.3 I2C errors mainly include bus error, acknowledge error, arbitration loss, overload\ underload error.
Page 603: Dma Application
first SCL rising edge. If cannot make sure do that, the first byte should be discard by receiver. 22.3.4 DMA application DMA can generate a requests when transfer data register empty or full. DMA can oprate write data to I2C or read data from I2C reduce burden of CPU.
Page 604: Packet Error Check
from I2C_DAT register to storage area. In DMA_TXNUMx register set the number of need to be transferred. In every I2C_STS1.RXDATEN event the number-1 until 0. In DMA_CHCFGx register set PRIOLVL[0:1] to configure the priority of channel. In DMA_CHCFGx register clear DIR to configure when ocurrs a interrupt request whether received half data or all data is received.
Page 605: Device Identification
SMBus have three types of device standard. • Master: device send command,generate clocks and stop transmmissions; • Slave: device receive,respond to commands; • Host: system have only one host. a device provides a master to system CPU. host have function of master and slave, it support SMBus alert protocol.
Page 606: Address Resolution Protocol
Address resolution protocol The SMBus resolves address conflicts by dynamically assigning a new unique address to each slave device. This is the address resolution protocol(ARP) . Any master device can connected bus to access all devices. SMBus physical layer arbitration enable to distribute addresses.When device power on, the device’s distribute address is not change, the protocol allows address retain when device power off.
Page 607: Debug Mode
the default address of the SMB device. If I2C_CTRL1.ARPEN=1 and I2C_CTRL1.SMBTYPE=1, use the SMB master header field. In order to support ARP (I2C_CTRL1.ARPEN=1), in SMBus host mode (I2C_CTRL1.SMBTYPE=1), software needs to respond to the I2C_STS2.SMBHADDR bit (in SMBus slave mode, respond to I2C_STS2.SMBDADDR bit) and implement the functions according to the ARP protocol.
Page 608: I2C Register Overview
I2C register 22.6.1 overview Table 22-3 I2C register overview Offset Register I2C_CTRL1 000h Reserved Reset Value I2C_CTRL2 CLKFREQ[5:0] 004h Reserved Reset Value I2C_OADDR1 ADDR[7:1] 008h Reserved Reserved Reset Value I2C_OADDR2 ADDR2[7:1] 00Ch Reserved Reset Value I2C_DAT DATA[7:0] 010h Reserved Reset Value I2C_STS1 014h Reserved...
Page 609 Bit field Name Description 0:I2C not reset; 1:I2C reset. Note: This bit can be used when the I2C_STS2.BUSY bit is set to 1 and no stop condition is detected on the bus. Reserved Reserved, the reset value must be maintained. SMBus alert It can be set or cleared by software.
Page 610: I2C Control Register 2 (I2C_Ctrl2)
Bit field Name Description ： Note When the STOPGEN, STARTGEN or PEC bit is set, the software should not take any write operation to I2C_CTRL1 until this bit is cleared by hardware. Otherwise, the STOPGEN, STARTGEN or PEC bits may be set twice. Start generation It can be set or cleared by software.
Page 611 Bit field Name Description 15:13 Reserved Reserved, the reset value must be maintained DMALAST DMA last transfer 0: Next DMA EOT is not the last transfer 1: Next DMA EOT is the last transfer Note: This bit is used in the master receiving mode, so that a NACK can be generated when data is received for the last time.
Page 612: I2C Own Address Register 1 (I2C_Oaddr1)
Bit field Name Description 000010：2MHz 000011：3MHz 100100：36MHz 100101~111111：Disable. I2C Own address register 1 (I2C_OADDR1) 22.6.4 Address offset: 0x08 Reset value: 0x0000 Bit field Name Description ADDRMODE Addressing mode (slave mode) 0: 7-bit slave address 1: 10-bit slave address Reserved Must always be kept as' 1' by the software. 13:10 Reserved Reserved, the reset value must be maintained.
Page 613: I2C Data Register (I2C_Dat)
1: Enable dual address mode, both OADDR1 and OADDR2 are recognized. Note: Valid only for 7-bit address mode 22.6.6 I2C Data register (I2C_DAT) Address offset: 0x10 Reset value: 0x0000 Bit field Name Description 15:8 Reserved Reserved, the reset value must be maintained. DATA[7:0] 8-bit data register Send or receive data buffer.
Page 614 Bit field Name Description • Master cumulative clock low extend time more than 10 ms (Tlow:mext). • Slave cumulative clock low extend time more than 25 ms (Tlow:sext). Timeout in slave mode: slave device resets the communication and hardware frees the bus. Timeout in master mode: hardware sends the stop condition.
Page 615 Bit field Name Description 1: Data register is empty. When sending data, this bit is set to' 1' when the data register is empty, and it is not set at the address sending stage. If a NACK is received, or the next byte to be sent is PEC(I2C_CTRL1.PEC=1), this bit will not be set.
Page 616: I2C Status Register 2 (I2C_Sts2)
Bit field Name Description In receiving mode, when a new byte (including ACK pulse) is received and the data register has not been read (I2C_STS1.RXDATNE=1).In sending mode, when a new data is to be transmitted and the data register has not been written with the new data (I2C_STS1.TXDATE=1). Note: After receiving a NACK, the BSF bit will not be set.
Page 617: I2C Clock Control Register (I2C_Clkctrl)
Bit field Name Description SMBHADDR SMBus host header（Slave mode） Hardware clears this bit when a stop condition or a repeated start condition is generated, or when I2C_CTRL1.EN=0. 0: SMBus host address was not received; 1: when I2C_CTRL1.SMBTYPE=1 and I2C_CTRL1.ARPEN=1, SMBus host address is received.
Page 618: I2C Rise Time Register (I2C_Tmrise)
correctly. 2. The CLKCTRL register can only be set when I C is turned off (I2C_CTRL1.EN=0) Bit field Name Description FSMODE I2C master mode selection 0: I2C in standard mode(duty cycle defaults to 1/1); 1: I2C in fast mode(duty cycle can be configured). DUTY Duty cycle in fast mode 0：Tlow/Thigh = 2；...
Page 619 Bit field Name Description 15:6 Reserved Reserved, the reset value must be maintained. TMRISE[5:0] Maximum rise time in fast/standard mode (master mode). These bits must be set to the maximum SCL rising time given in the I2C bus specification, and incremented step is 1.
Page 620: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
Universal synchronous asynchronous receiver transmitter (USART) Introduction USART is a full-duplex universal synchronous/asynchronous serial transceiver module. This interface is a highly flexible serial communication device that can perform full-duplex data exchange with external devices. The USART has programmable transmit and receive baud rates and can communicate continuously using DMA. It also supports multiprocessor communication, LIN mode, synchronous mode, single-wire half-duplex communication, smart card asynchronous protocol, IrDA SIR ENDEC function, and hardware flow control function.
Page 621: Functional Block Diagram
Functional block diagram Figure 23-1 USART block diagram CPU/DMA Transmit Data Receive Register(TDR) Data(RDR) IrDA ENDEC Transmit Shift Receive Shift BLOCK SW_RX Register Register Hardware nRTS flow TX control RX control controller nCTS Tx clock Rx clock Buadrate CTRL register PCLK generate BRCF...
Page 622: Usart Frame Format
start bit + 8 or 9 data bits (least significant bit first) + 1 parity bit (optional) + 0.5,1,1.5 or 2 stop bit. Use the fractional baud rate generator to configure transmit and receive baud rates. According to the block diagram, when using the hardware flow control mode, the nRTS output and nCTS input pins are required.
Page 623: Transmitter
Figure 23-3 word length = 9 setting 9-bit word length , 1 stop bit Clock Data frame bit8 can be the parity bit Data frame Start Stat Stop bit2 bit6 bit7 bit8 bit0 bit1 bit3 bit4 bit5 Start Idle frame Start Stop Break frame...
Page 624: Figure 23-4 Configuration Stop Bit
Figure 23-4 configuration stop bit 8-bit Word length (WL bit is reset) CLOCK bit7 can be the parity bit Data frame Start Stat bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Data frame 0.5 Stop bit 0.5Stop bit Data frame bit7 can be the parity bit Data frame Start...
Page 625: Single Byte Communication
Single byte communication A write to the USART_DAT register clears the USART_STS.TXDE bit. The USART_STS.TXDE bit is set by hardware when the data in the TDR register is transferred to the transmit shift register (indicating that data is being transmitted). An interrupt will be generated if USART_CTRL1.TXDEIEN is set.
Page 626: Figure 23-6 Start Bit Detection
10th bits have three '0' points, then the start bit is confirmed, but it will be set NEF noise flag. The samples of the 3rd, 5th, and 7th bits have three '0' points, and at the same time, the samples of the 8th, 9th, and 10th bits have two '0' points, then the start bit is confirmed, but it will be set NEF noise flag.
Page 627: Framing Error
The 1.5 stop bits can be divided into two parts: one is 0.5 clock cycles, during which nothing is done. This is followed by the stop bit of 1 clock cycle, which is sampled at the midpoint of this period of time. For details, see 23.4.14 Smartcard mode.
Page 628: Generation Of Fractional Baud Rate
is set, the value in the RDR register is not lost, but the data in the shift register is overwritten. It is cleared by a software sequence (read USART_STS register first, then write USART_DAT register). When an overflow error occurs, USART_STS.RXDNE is '1', and an interrupt is generated. If the USART_CTRL3.ERRIEN bit is set, an interrupt will be generated when the USART_STS.OREF flag is set in multi- buffer communication mode.
Page 629: Table 23-3 Error Calculation When Setting Baud Rate
If USARTDIV = 27.75, then： DIV_Decimal = 16*0.75 = 12 = 0x0C DIV_Integer = 27=0x1B So USART_BRCF = 0x1BC Example 2: If USARTDIV = 20.98, then： DIV_Decimal = 16*0.98 = 15.68 Nearest integer: DIV_Decimal = 16 = 0x10, out of configurable range, so a carry to integer is required So DIV_Integer = 20+1 = 21 = 0x15 DIV_Decimal = 0x0 So USART_BRCF = 0x150...
Page 630: Receiver's Tolerance Clock Deviation
4500 impossible impossible impossible 4500 Notes: The lower the clock frequency of the CPU, the lower the error for a particular baud rate. 23.4.5 Receiver’s tolerance clock deviation Variations due to transmitter errors (including transmitter side oscillator variations), receiver side baud rate rounding errors, receiver side oscillator variations, variations due to transmission lines (usually due to The inconsistency between the low-to-high transition timing of the transceiver and the high-to-low transition timing of the transceiver), these factors will affect the overall clock system variation.
Page 631: Odd Parity
Make the number of '1' in the transmitted data (including parity bit) be an even number. That is: if Data=11000101, there are 4 '1's, then the parity bit will be '0' (4 '1' in total). After the data and check digit are sent to the receiver, the receiver calculates the number of 1s in the data again.
Page 632: Figure 23-7 Transmission Using Dma
Figure 23-7 Transmission using DMA TXDE flag set by hardware cleared by DMA DMA writes Data1 DMA writes DataN DMA writes Data0 into USART_DAT into USART_DAT into USART_DAT DMA request Data 0 Data 1 Data N TX line Software waits TXC=1 TXC flag set by hardware...
Page 633: Hardware Flow Control
Figure 23-8 Reception using DMA Data 0 Data 1 Data N RX line RXDNE flag set by hardware cleared by DMA DMA reads Data0 DMA reads Data1 DMA reads DataN from USART_DAT from USART_DAT from USART_DAT DMA request DMA transfer is complete DMA TXCF flag set by hardware...
Page 634: Figure 23-10 Rts Flow Control
data arrives in RDR, pull high nRTS output, notifying the sender to stop data transmission at the end of the current frame. when receiver is ready to receive new data, assert (pull low) the nRTS output. Figure 23-10 RTS flow control Waiting to read data Read data register register,RTS high...
Page 635: Multiprocessor Communication
23.4.9 Multiprocessor communication USART allows multiprocessor communication. The principle is: multiple processors communicate through USART, and it is necessary to determine who is the master device, and the remaining processors are all slave devices. The TX output of the master device is directly connected to the RX port of all slave device. The TX outputs of the slaves are logically AND together and connected to the RX inputs of the master.
Page 636: Synchronous Mode
enters mute mode Note: When the receive buffer contains no data (RXNE=0 in USART_SR), the USART_CTRL1.RCVWU bit can be written to 0 or 1. Otherwise, the write operation is ignored. • When the received address does not match the address of the USART_CTRL2.ADDR[3:0] bits, USART_CTRL1.RCVWU is written to 1 by hardware.
Page 637: Figure 23-14 Usart Synchronous Transmission Example
A sync data cannot be received when no data is sent. Because the clock is only available when the transmitter is activated and data is written to the USART_DAT register. The USART_CTRL2.LBCLK bit controls whether to output the clock pulse corresponding to the last data byte (MSB) sent on the CK pin.
Page 638: Figure 23-15 Usart Data Clock Timing Example (Wl=0)
Figure 23-15 USART data clock timing example (WL=0) Clock（CLKPOL=0，CLKPHA=0） Clock（CLKPOL=0，CLKPHA=1） Clock（CLKPOL=1，CLKPHA=0） Clock（CLKPOL=1，CLKPHA=1） Data on TX (from master) MSB Stop Start LSB Data on RX (from slave) 638 / 816...
Page 639: Single-Wire Half-Duplex Mode
Figure 23-16 USART data clock timing example (WL=1) Clock（CLKPOL=0，CLKPHA=0） Clock（CLKPOL=0，CLKPHA=1） Clock（CLKPOL=1，CLKPHA=0） Clock（CLKPOL=1，CLKPHA=1） Data on TX (from master) MSB Stop Start LSB Data on RX (from slave) Figure 23-17 RX data sampling / holding time SCLK(capture strobe on SCLK rising edge in this example) Data on RX valid DATA bit (from slave)
Page 640: Irda Sir Endec Mode
wire half-duplex, USART_CTRL2. CLKEN, USART_CTRL2. LINMEN, USART_CTRL3. SCMEN, USART_CTRL3. IRDAMEN, these bits should be kept clear. After the half-duplex mode is turned on, the TX pin and the RX pin are interconnected inside the chip, and the Rx pin is no longer used. When there is no data to transmit, TX is always released. Therefore, when not driven by the USART, the TX pin must be configured as a floating input or an open-drain output high.
Page 641: Lin Mode
Figure 23-18 IrDASIRENDEC-Block diagram TX pin Transmit Encoder IRDAMEN NORMAL = 0 or 1 USART MODE Receive RX pin Decoder Figure 23-19 IrDA data Modulation (3/16)-normal mode Start TX normal Stop frame TX pin frame 3/16 RX pin frame Start RX normal Stop frame...
Page 642: Figure 23-20 Break Detection In Lin Mode (11-Bit Break Length-The Linbdl Bit Is Set)
By configuring the USART_CTRL2.LINBDL bit, 10-bit or 11-bit break character detection can be selected. After the receiver detects the start bit, the circuit samples each subsequent bit at the 8th, 9th, and 10th oversampling clock points of each bit. When 10 or 11 consecutive bits are detected as '0' and followed by a delimiter, it means that a LIN break is detected, and USART_STS.LINBDF is set.
Page 643: Smartcard Mode (Iso7816)
Figure 23-21 Break detection and framing error detection in LIN mode In these examples, we suppose that LINBDL=1(11-bit break length),WL=0(8-bit data) Break occurring after an Idle： RX line frame1 Idle frame2 frame3 1 frame time 1 frame time RXDNE/FEF LINBDF Break occurring while a data is being received：...
Page 644: Figure 23-22 Iso7816-3 Asynchronous Protocol
Figure 23-22 ISO7816-3 Asynchronous Protocol Without Parity error Guard time Start With Parity error Guard time Line pulled low by receiver during stop In case of parity error Start The break frame has no meaning in smart card mode. A 00h data with a framing error will be treated as data instead of a break symbol.
Page 645: Interrupt Request
Figure 23-23 Use 1.5 stop bits to detect parity errors 1.5 Stop Bit Parity Bit Bit 7 1 bit time 1.5 bit time sampling at sampling at 16th, 17th, 18th 8th, 9th, 10th 0.5 bit time 1 bit time sampling at sampling at 8th, 9th, 10th 8th, 9th, 10th...
Page 646: Mode Support
(1) This flag bit is used only when DMA is used to receive data(USART_CTRL3.DMARXEN=1). Mode support Table 23-8 USART mode setting Communication mode USART1 USART2 USART3 UART4 UART5 UART6 UART7 Asynchronous mode Multiprocessor LIN mode Synchronous mode Single-wire half duplex mode Smartcard mode IrDA infrared mode DMA communication mode...
Page 647: Usart Status Register (Usart_Sts)
Offset Register Reset Value USART_CTRL3 014h Reserved Reset Value USART_GTP GTV[7:0] PSCV[7:0] 018h Reserved Reset Value 23.7.2 USART Status register (USART_STS) Address offset : 0x00 Reset value : 0x0000 00C0 Bit field Name Description 31:10 Reserved Reserved, the reset value must be maintained CTSF CTS flag If USART_CTRL3.CTSEN bit is set, this bit is set by hardware when the nCTS input...
Page 648 Bit field Name Description the current data transmission is completed. Setting USART_CTRL1.TXCIEN bit will generate an interrupt. This bit is cleared by software. 0: Transmitting did not complete. 1: Send completed. RXDNE The Read data register not empty. This bit is set when the read data buffer receives data from the shift register. When USART_CTRL1.RXDNEIEN bit is set, an interrupt will be generated.
Page 649: Usart Data Register (Usart_Dat)
Bit field Name Description 1: A framing error or a Break Character is detected. Note: this bit will not generate an interrupt because it appears with USART_STS.RXDNE, and the hardware will generate an interrupt when setting the USART_STS.RXDNE flag. If the currently transmitted data has both framing errors and overload errors, the hardware will continue to transmit the data and only set the USART_STS.OREF flag bit.
Page 650: Usart Control Register 1 Register (Usart_Ctrl1)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:4 DIV_Integer[11:0] Integer part of baud rate divider. DIV_Decimal[3:0] Fractional part of baud rate divider. 23.7.5 USART control register 1 register (USART_CTRL1) Address offset : 0x0C Reset value : 0x0000 0000 Bit field Name Description...
Page 651 Bit field Name Description PEIEN PE interrupt enable If this bit is set to 1, an interrupt is generated when USART_STS.PEF bit is set. 0: Parity error interrupt is disabled. 1: Parity error interrupt is enabled. TXDEIEN TXDE interrupt enable If this bit is set to 1, an interrupt is generated when USART_STS.TXDE bit is set.
Page 652: Usart Control Register 2 Register (Usart_Ctrl2)
23.7.6 USART control register 2 register (USART_CTRL2) Address offset : 0x10 Reset value : 0x0000 0000 Bit field Name Description 31:15 Reserved Reserved, the reset value must be maintained LINMEN LIN mode enable 0:LIN mode is disabled 1:LIN mode enabled 13:12 STPB[1:0] STOP bits.
Page 653: Usart Control Register 3 Register (Usart_Ctrl3)
Bit field Name Description LINBDIEN LIN break detection interrupt enable. If this bit is set to 1, an interrupt will be generated when USART_STS.LINBDF bit is set. 0: Disconnect signal detection interrupt is disabled. 1: Turn-off signal detection interrupt enabled LINBDL LIN break detection length.
Page 654: Usart Guard Time And Prescaler Register (Usart_Gtp)
Bit field Name Description RTSEN RTS enable. This bit is used to enable RTS hardware flow control function. 0:RTS hardware flow control is disabled. 1:RTS hardware flow control is enabled. Note: This bit cannot be used for UART4/5/6/7 DMATXEN DMA transmitter enable. 0:DMA transmission mode is disabled.
Page 655 Reset value : 0x0000 0000 Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:8 GTV[7:0] Guard time value in Smartcard mode. This bit field specifies the guard time in baud clock. In Smartcard mode, this function is required.
Page 656: Quad Serial Peripheral Interface (Qspi)
Quad Serial Peripheral Interface (QSPI) Introduction QSPI is an interface for single,dual or quad SPI peripheral communication. It can work in indirect or memory mapped modes. Indirect Mode: All operations are performed using QSPI registers. Memory Mapped Mode: The external flash memory is mapped into the microcontroller address space, and the system treats it as internal storage space.
Page 657: Function Description
Function description Figure 24-1 QSPI block diagram Master Slave rxd[3] I/O Buffer I/O Buffer IO [3] txd[3] rxd[2] I/O Buffer IO [2] Txd[2] QSPI rxd[1] I/O Buffer IO [1]/DO txd[1] rxd[0] I/O Buffer IO [0]/DI txd[0] QSPI command sequence QSPI communicates with peripherals through commands. Each command includes five phase: Instruction phase, Address phase, Mode bits phase, Wait cycles phase and Data phase.
Page 658: Operating Procedures
Figure 24-2 QSPI command sequence Mode Wait Address bits cycles Instruction Data 0 4 0 4 0 4 0 4 0 1 5 1 5 1 5 1 5 1 2 6 2 6 2 6 2 6 2 3 7 3 7 3 7 3 7 3 A23-16 A15-8...
Page 659: Qspi Indirect Send Operation
24.5.2 QSPI Indirect send operation QSPI_CTRL0.SPI_FRF[1:0] specifies the frame transmission format (standard/dual-wire/quad-wire mode) QSPI_CTRL0.DFS[4:0] specifies the data length (4～32bit) QSPI_ENH_CTRL0.ADDR_LEN[3:0] specifies the address length (4bit ～ 60bit, configurable to skip the Address phase) QSPI_ENH_CTRL0.INST_L[1:0] specifies the instruction length (4bit, 8bit, 16bit, configurable to skip the Instruction stage) Note: One instruction occupies one FIFO address, and the address can occupy multiple FIFO locations.
Page 660: Qspi Indirect Receive Operation
IO[0](TX) ADDRESS DATA INSTRUCTION IO[N:1](TX) ADDRESS DATA QSPI_ENH_CTRL0.TRANS_TYPE[1:0] shall be configured as 0x01. When QSPI_CTRL0.SPI_FRF[1:0] is configured as 0x02 (Quad mode), N=3; when QSPI_CTRL0.SPI_FRF[1:0] is configured as 0x01 (Dual mode), N=1. • Instruction and address are sent timing in CTRL0.SPI_FRF specified mode IO[N:0](TX) ADDRESS DATA...
Page 661 NDF (QSPI_CTRL1[15:0]), and then cancels the slave select signal. The read operation can be divided into 4 phase: Instruction phase, Address phase, Wait cycles phase and Data phase. • Typical Read Operation Timing WAIT IO[0](TX) ADDRESS INSTRUCTION CYCLES IO[N:0](RX) DATA In quad mode N=3, each read command data will be transmitted in the format configured by QSPI_CTRL0.SPI_FRF[1:0].
Page 662 WAIT IO[0](TX) ADDRESS INSTRUCTION CYCLES IO[N:1](TX) ADDRESS IO[N:0](RX) DATA QSPI_ENH_CTRL0.TRANS_TYPE[1:0] should be configured as 0x1, QSPI_ENH_CTRL0.WAIT_CYCLES[4:0] configure the cycle of WAIT. When QSPI_CTRL0.SPI_FRF[1:0] is configured as 0x02 (Quad mode), N=3; when QSPI_CTRL0.SPI_FRF[1:0] is configured as 0x01 (Dual mode), N=1. • Instruction and address are received timing in QSPI_CTRL0.SPI_FRF specified mode WAIT IO[N:0](TX)
Page 663: Qspi Register
QSPI_ENH_CTRL0.WAIT_CYCLES[4:0] is configured to wait cycles. When QSPI_CTRL0.SPI_FRF[1:0] is configured as 0x02 (Quad mode), N=3; when QSPI_CTRL0.SPI_FRF[1:0] is configured as 0x01 (Dual mode), N=1. QSPI register 24.6.1 QSPI register overview Table 24-1 QSPI register overview Offset Register QSPI_CTRL0 CFS[3:0] DFS[4:0] 000h Reserved Reset Value...
Page 664 Offset Register QSPI_STS 028h Reserved Reset Value QSPI_IMASK 02Ch Reserved Reset Value QSPI_ISTS 030h Reserved Reset Value QSPI_RISTS 034h Reserved Reset Value QSPI_TXFOI_CL 038h Reserved Reset Value QSPI_RXFOI_CL 03Ch Reserved Reset Value QSPI_RXFUI_CL 040h Reserved Reset Value QSPI_MMC_CLR 044h Reserved Reset Value QSPI_ICLR 048h...
Page 665: Qspi Control 0 Register (Qspi_Ctrl0)
Offset Register Reset Value QSPI_DDR_TXD TXDE[7:0] 0F8h Reserved Reset Value QSPI_XIP_MODE XIP_MD_BITS[15:0] 0FCh Reserved Reset Value QSPI_XIP_INCR_ ITOC[15:0] 100h Reserved Reset Value QSPI_XIP_WRAP WTOC[15:0] _TOC 104h Reserved Reset Value QSPI_XIP_CTRL WAIT_CYCLES[4:0] ADDR_LEN[3:0] 108h Reset Value QSPI_XIP_SLAV E_EN 10Ch Reserved Reset Value QSPI_XIP_RXFO I_CLR 110h...
Page 666 Bit field Name Description 01: Dual SPI Format 10: Quad SPI Format 11: Reserved 21:20 Reserved Reserved, the reset value must be maintained 19:16 CFS[3:0] Control Frame Size Selects the length of the control word for the Microwire frame format. 0000: 1bit Control Word 0001: 2bit Control Word 0010: 3bit Control Word...
Page 667: Qspi Control 1 Register (Qspi_Ctrl1)
Bit field Name Description 11: Reserved Reserved Reserved, the reset value must be maintained DFS[4:0] Data Frame Size Selects the data frame length. When the data frame size is programmed to be less than 32 bits, the data is automatically right-aligned. 0x0/0x01/0x02: Reserved 0x03: 4bit 0x04: 5bit...
Page 668: Qspi Microwire Control Register (Qspi_Mw_Ctrl)
Bit field Name Description 31:1 Reserved Reserved, the reset value must be maintained QSPI Enable 0: Disabled. when QSPI is disabled, all serial transfers stop immediately. 1: Enable QSPI. 24.6.5 QSPI Microwire Control Register (QSPI_MW_CTRL) Note: This register cannot be written when the QSPI_EN.QEN = 1. Address offset: 0x0C Reset value: 0x0000 0000 Bit field...
Page 669: Qspi Baud Rate Select Register (Qspi_Baud)
Bit field Name Description 31:1 Reserved Reserved, the reset value must be maintained Slave Enable 0: Disable 1: Enable Note: You cannot write to this register when QSPI is busy and when QSPI_EN.QEN = 24.6.7 QSPI Baud Rate Select Register (QSPI_BAUD) Address offset: 0x14 Reset value: 0x0000 0000 Bit field...
Page 670: Qspi Receive Fifo Threshold Level Register (Qspi_Rxft)
Bit field Name Description 31:21 Reserved Reserved, the reset value must be maintained 20:16 TXFT_ST[4:0] Transmit FIFO Threshold to Start to Transfer. Tx transmission threshold, after reaching this value, start Tx transmission. 15:5 Reserved Reserved, the reset value must be maintained TXFT_TEI[4:0] Transmit FIFO Threshold to Trigger Empty Interrupt.
Page 671: Qspi Status Register (Qspi_Sts)
Reset value: 0x0000 0000 Bit field Name Description 31:6 Reserved Reserved, the reset value must be maintained RXFN[5:0] Number of Receive FIFO. 24.6.12 QSPI Status Register (QSPI_STS) Address offset: 0x28 Reset value: 0x0000 0006 Bit field Name Description 31:7 Reserved Reserved, the reset value must be maintained DC_ERR Data Conflict Error...
Page 672: Qspi Interrupt Mask Register (Qspi_Imask)
Bit field Name Description TXFNF Transmit FIFO Not Full. 0: Tx FIFO is full 1: Tx FIFO is not Full Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. BUSY Transfer Busy Flag.
Page 673: Qspi Interrupt Status Register (Qspi_Ists)
24.6.14 QSPI Interrupt Status Register (QSPI_ISTS) Address offset: 0x30 Reset value: 0x0000 0000 Bit field Name Description 31:7 Reserved Reserved, the reset value must be maintained XRXOIS XIP Receive FIFO Overflow Interrupt Status. 0: Invalid, after masking. 1: Validafter, after masking. MMCIS Multi-Master Contention Interrupt Status.
Page 674: Qspi Transmit Fifo Overflow Interrupt Clear Register (Qspi_Txfoi_Clr)
Bit field Name Description 31:7 Reserved Reserved, the reset value must be maintained XRXORIS XIP Receive FIFO Overflow Raw Interrupt Status. 0: Invalid, prior to masking. 1: Valid, prior to masking. MMCRIS Multi-Master Contention Raw Interrupt Status. 0: Invalid, prior to masking. 1: Valid, prior to masking.
Page 675: Qspi Receive Fifo Overflow Interrupt Clear Register (Qspi_Rxfoi_Clr)
Bit field Name Description 31:1 Reserved Reserved, the reset value must be maintained TXFOIC Clear Transmit FIFO Overflow Interrupt. After reading this register, clear the Tx FIFO overflow interrupt status. 24.6.17 QSPI Receive FIFO Overflow Interrupt Clear Register (QSPI_RXFOI_CLR) Address offset: 0x3C Reset value: 0x0000 0000 Bit field Name...
Page 676: Qspi Interrupt Clear Register (Qspi_Iclr)
Reset value: 0x0000 0000 Bit field Name Description 31:1 Reserved Reserved, the reset value must be maintained MMCIC Clear Multi-Master Contention Interrupt. After reading this register, clear the multi-master conflict interrupt status. 24.6.20 QSPI Interrupt Clear Register (QSPI_ICLR) Address offset: 0x48 Reset value: 0x0000 0000 Bit field Name...
Page 677: Qspi Dma Transmit Data Level Register (Qspi_Dmatdl_Ctrl)
Bit field Name Description TX_DMA_EN Transmit DMA Enable. 0: Disable 1: Enable RX_DMA_EN Receive DMA Enable. 0: Disable 1: Enable 24.6.22 QSPI DMA Transmit Data Level Register (QSPI_DMATDL_CTRL) Address offset: 0x50 Reset value: 0x0000 0000 Bit field Name Description 31:6 Reserved Reserved, the reset value must be maintained DMATDL[5:0]...
Page 678: Qspi Rx Sample Delay Register (Qspi_Rs_Delay)
Bit field Name Description 31:0 DATx[31:0] In the Rx state, it is the receive buffer, and the read data is automatically right- aligned; in the Tx state, it is the send buffer, and the write data must be right- aligned. Note: a total of 32 register addresses are 0x60+(0:31) ×...
Page 679 Bit field Name Description Reserved Reserved, the reset value must be maintained CLK_STRETCH_EN Clock Stretch Enable in SPI transfers. In case of write, if the FIFO becomes empty QSPI will stretch the clock until FIFO has enough data to continue the transfer. In case of read, if the receive FIFO becomes full QSPI will stop the clock until data has been read from the FIFO.
Page 680: Qspi Ddr Transmit Drive Edge Register (Qspi_Ddr_Txde)
Bit field Name Description 01: Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by QSPI_CTRL0.SPI_FRF. 10: Both Instruction and Address will be sent in the mode specified by QSPI_CTRL0.SPI_FRF. 11: Reserved 24.6.27 QSPI DDR Transmit Drive Edge Register (QSPI_DDR_TXDE) Address offset: 0xF8 Reset value: 0x0000 0000...
Page 681: Qspi Xip Wrap Transfer Opcode Register (Qspi_Xip_Wrap_Toc)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 ITOC[15:0] XIP INCR transfer OpCode. When QSPI_XIP_CTRL.XIP_INST_EN=1, QSPI sends XIP INCR type transmission instruction code. The number of bits to be sent during the command phase is determined by the QSPI_XIP_CTRL.INST_L field. 24.6.30 QSPI XIP WRAP transfer opcode Register (QSPI_XIP_WRAP_TOC) Address offset: 0x104 Reset value: 0x0000 0000...
Page 682 Bit field Name Description 27:26 XIP_MBL [1:0] XIP Mode bits length. 00: Mode bits length equal to 2 01: Mode bits length equal to 4 10: Mode bits length equal to 8 11: Mode bits length equal to 16 25:24 Reserved Reserved, the reset value must be maintained XIP_CT_EN...
Page 683: Qspi Xip Slave Enable Register (Qspi_Xip_Slave_En)
Bit field Name Description 0x3: 12bit …… 0xE: 56bit 0xF: 60bit TRANS_TYPE[1:0] Address and instruction transfer format. 00: Instruction and Address will be sent in Standard SPI Mode. 01: Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by QSPI_XIP_CTRL.FRF[1:0] 10: Both Instruction and Address will be sent in the mode specified by QSPI_XIP_CTRL.FRF[1:0].
Page 684: Qspi_Xip_Tout
Bit field Name Description 31:1 Reserved Reserved, the reset value must be maintained XRXFOIC Clear XIP Receive FIFO Overflow Interrupt. After reading this register, clear the Rx FIFO overflow interrupt status 24.6.34 QSPI XIP time out for continuous transfers register （QSPI_XIP_TOUT）...
Page 685: Ethernet (Eth)
Ethernet (ETH) MAC: Media Access Control MII: Media-Independent Interface RMII: Reduced Media-Independent Interface SMI: Station Management Interface CSMA/CD: Carrier Sense Multiple Access/Collision Detection SFD: Start Frame Delimiter FCS: Frame Check Sequence SOF: Start Of Frame EOF: End Of Frame Note: Only N32G457xx series chips support Ethernet module. Introduction Ethernet module includes a 10/100Mbps Ethernet MAC, which uses DMA to optimize the transmission and reception performance of data frames, supports MII and RMII two standard interfaces for communication with the physical...
Page 686 − Support programmable frame gap (40~96 bits, but must be an integer multiple of 8) − Support a variety of flexible address filtering − Support IEEE 802.1Q VLAN tag detection for receive frames − Support for mandatory network statistics using RMON/MIB counter (RFC2819/RFC2665) −...
Page 687: Function Block Diagram
− Support two calibration methods: rough adjustment and fine adjustment − Interrupt can be triggered when the system time reaches a predetermined time − Output second pulse Function block diagram Ethernet peripheral mainly includes MAC module, MII/RMII interface module and a DMA module controlled in the form of descriptor.
Page 688: Pin Configuration (Alternate) Method
Figure 25-2 MAC frame format and frame structure Basic format 46-1500 bytes 7 bytes 1 bytes 6 bytes 6 bytes 2 bytes 4 bytes Destination Source Preamble Length/Type Payload data address address (optional) QTag Prefix Tagged format 46-1500 bytes 4 bytes 7 bytes 1 bytes 6 bytes...
Page 689: Smi Interface
Default MII Signal RMII Signal Remap 1 Remap 2 Remap 3 Pin configuration mapping RxD1 RxD1 PD10 PD10 Input floating (reset state) RxD2 PD11 Input floating (reset state) RxD3 PD12 Input floating (reset state) Rx_ER PB10 Input floating (reset state) Push-pull alternate output, high speed Tx_EN Tx_EN...
Page 690: Mii Interface
judge whether the transmission is completed. During the transmission process, the ETH_MACMIIADDR.MB bit is always high until the transmission is completed, and the hardware will automatically clear the ETH_MACMIIADDR.MB bit. When the ETH_MACMIIADDR.MB bit is 1, modifying the contents of ETH_MACMIIADDR and ETH_MACMIIDAT will be invalid.
Page 691: Figure 25-4 Mii Interface Signal Line
Figure 25-4 MII interface signal line • MII_Tx_EN: Transmit enable signal, this signal must appear synchronously with the start bit of the data preamble, and keep it until the transmission is completed. • MII_Tx_CLK: The continuous clock signal used for transmit data. When the data transmission rate is 10Mbps, the clock is 2.5MHz;...
Page 692: Rmii Interface
• MII_COL: Collision detection signal, controlled by PHY, only works in half-duplex mode. This signal is enabled when a medium collision is detected and remains active for the duration of the collision. This signal does not need to be synchronized with the transmit/receive clock. Table 25-3 Transmit interface signal code MII_Tx_EN MII_TxD[3:0]...
Page 693: Mac Function Description
and receive data are transmitted through 2-bit line width respectively. Figure 25-6 RMII interface signal line RMII clock source As shown in the figure below, an external clock source or by configuring a suitable PLL, the clock output pin MCO of the MCU can provide a 50MHz clock signal.
Page 694 in full-duplex mode access the LAN, they can transmit and receive at the same time without conflict. MAC frame transmission process The DMA controller and MAC in the Ethernet module control all Ethernet frame data transmission. After received the application transmitted instruction, DMA will read the transmit frame from the system storage area and store it in the TxFIFO with a size of 2K.
Page 695 Retransmission conflict handling mechanism When the working mode is half-duplex, the data frame transmitted by MAC may collide. If a conflict event occurs and only frame data of no more than 96 bytes in TxFIFO is taken out to MAC, the frame retransmission function will be activated, and MAC will abort the current data transmission, read the data from TxFIFO and retransmit it.
Page 696 reached. Otherwise, the frame will be transmitted immediately. When working in half-duplex mode, MAC will start the frame gap counter after the previous transmission frame is completed or MAC enters the idle state. Depending on the situation in which the carrier signal is detected, the processing is different: If the carrier signal appears in the first 2/3 of the frame gap time, the frame gap counter will be reset and count again.
Page 697: Address Filter
of the header. There are two processing methods: Not included the pseudo-headers of TCP, UDP, or ICMPv6 are in the calculation. First include the checksum field in the checksum calculation, and then insert and replace the value of the original checksum field after the calculation is completed.
Page 698 • HASH list filtering MAC uses HASH mechanism to imperfectly filter unicast addresses using a 64-bit HASH list, which can cover any possible address with just a small table, but sometimes frames that should be discarded are also received. The filtering process is as follows: MAC calculates the CRC value of the destination address of the received frame, and uses the upper 6 bits of the CRC calculation result as an index to retrieve the HASH list;...
Page 699: Table 25-5 Destination Address Filter Result List
25.4.6.10.9 Pause control frame filtering MAC will detect the 6-byte destination address field in the received control frame. If ETH_MACFLWCTRL.UP = 0, it will judge whether the value of the destination address field is equal to 0x0180 C200 0001 (the unique value of the control frame in line with the IEEE802.3 specification);...
Page 700: Receive Flow Control
Frame type SAIF Source address filtering result description frame Pass when perfect/group filter matches, but don't drop frames that fail Fail when perfect/group filter matches, but don't drop frames Pass when perfect/group filter matches, drop frames that fail Fail when perfect/group filter matches, drop frames that fail MAC frame receive process As soon as MAC detects an SFD on the interface, the receive procedure is initiated.
Page 701 of the pause time field in the Pause frame. During a pause, if a new Pause frame is received, the new pause time will be loaded into the pause time counter immediately. If the value of the received pause time field is 0, MAC will stop the pause time counter and resume data transmission.
Page 702: Mac Loopback Mode
The receive checksum module does not calculate if IP packet is incomplete or with security features, IPv6 routing headers, and data types other than TCP, UDP, or ICMP. MAC loopback mode Loopback mode is disabled by default, which is generally used for application testing and debugging of system hardware and software.
Page 703: Table 25-7 Remote Wakeup Frame Filter Register Overview
Table 25-7 Remote wakeup frame filter register overview Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Wakeup frame filter Filter 0 byte mask register 0 Wakeup frame filter Filter 1 byte mask register 1...
Page 704: Magic Packet Detection
is wrong, whether Dribble bit is wrong, whether MII is wrong, whether there is a collision, and ensuring that the remote wake-up frame is not a stub frame. Even if the length of the remote wake-up frame exceeds 512 bytes, if the frame has a valid CRC value, it is still considered a valid wake-up frame.
Page 705: Ethernet Dma Function Description
the interrupt flag bit of external interrupt line 19 in interrupt handler; Set ETH_MACPMTCTRLSTS.MGKPKTEN to 1 to enable detection of Magic Packet wakeup frames or set ETH_MACPMTCTRLSTS.RWKPKTEN to 1 to enable detection of remote wakeup frames; Set ETH_MACPMTCTRLSTS.PWRDWN to 1 to enable low-power consumption mode; Set ETH_MACCFG.RE to 1, open MAC receive engine;...
Page 706: Figure 25-8 Two Structures Of Descriptor
Figure 25-8 Two structures of descriptor Chain structure Ring structure Buffer1 Buffer1 Descriptors 0 Descriptors 0 Buffer2 Buffer1 Buffer1 Descriptors 1 Descriptors 1 Buffer2 Buffer1 Buffer1 Descriptors 2 Descriptors 2 Buffer2 Descriptor N Buffer1 Descriptor N Buffer1 (last) (last) Buffer2 Data buffer address alignment The alignment types supported by Ethernet DMA controller include byte alignment, halfword alignment, and word alignment.
Page 707: Table 25-8 Transmit Descriptor Overview
that the total size of the cache is 1024 bytes, the address of the buffer is 0x2000 0001, and the lower 2 bits of the address are 01b, then the effective length of the buffer is 1023 bytes, ranging from 0x2000 0001 at the beginning of the frame to 0x2000 03FF.
Page 708 Register TDES2 Buffer 1 address/Timestamp low TDES3 Buffer 2 address/Next descriptor address/Timestamp high • TDES0: Transmit descriptor word 0 Bit field Name Description Occupancy bit. 0: Indicates that CPU occupies descriptor. 1: Indicates that DMA occupies descriptor. DMA clears this bit to 0 after transferring a complete frame or reading out all the data in buffer.
Page 709 Bit field Name Description TDES0[11]: Carrier loss TDES0[10]: No carrier TDES0[9]: Late collision TDES0[8]: Excessive collision TDES0[2]: Excessive deferral TDES0[1]: Data underflow error Jabber timeout. This bit is only set when ETH_MACCFG.JD bit is reset. 0: No Jabber timeout occurred. 1: A Jabber timeout occurred at MAC sender.
Page 710 Bit field Name Description Collision count. CC[3:0] This 4-bit value records the number of collision that occurred before frame was transmitted. These bits have no effect when TDES0.EC is 1. Excessive deferral. This bit is valid when ETH_MACCFG.DC is 1. If this bit is set, the transmission of the current frame is aborted.
Page 711 Bit field Name Description 01: Only enable calculation and insertion of checksum of hardware IP header. 10: Enable calculation and insertion of checksums of hardware IP headers and data fields, but do not calculate checksums of pseudo-headers. 11: Enable calculation and insertion of checksum of hardware IP header and data field, and also calculate checksum of pseudo-header.
Page 712 of the cache. When the value of these bits represents the lower 32 bits of the timestamp, TDES1.TTSE and TDES1.LS of the current descriptor must be set. • TDES3: Transmit descriptor word 3 Before transmit a frame, application must configure TDES3 as the address of transmit buffer 2, or as the address of next descriptor (depending on whether the descriptor type is chain or ring).
Page 713 transmitted. If TDES1.LS of current descriptor is 0, after all buffered data is transmitted to TxFIFO, clear TDES0.OWN to close this descriptor. TxDMA controller will wait to write back the descriptor status and the IEEE 1588 timestamp value (provided that timestamp function is enabled); After completing a complete frame transmission, ETH_DMASTS.TI (transmit status bit) will be set only when TDES1.IC is 1.
Page 714: Table 25-9 Receive Descriptor Overview
RxDMA 25.4.8.4.1 Receive frame processing When MAC receives the frame data, address filtering module also starts to work. If the frame does not pass address filtering, MAC RxFIFO will discard frame and will not forward it to receiving buffer through RxDMA. Conversely, if working in cut-through (threshold) mode and the received frame length is greater than or equal to the preset receive threshold, or working in store-and-forward mode and a complete frame is stored in the RxFIFO, it will be forwarded to the receive buffer.
Page 715 Bit field Name Description Occupancy bit. 0: Indicates that CPU occupies descriptor. 1: Indicates that DMA occupies descriptor. DMA clears this bit to 0 after transferring a complete frame or filling the buffer corresponding to descriptor. Failed destination address filter. 0: The received frame passes destination address filter.
Page 716 Bit field Name Description 0: No length error occurred. 1: A length error has occurred. Overflow error. This bit is set when RxFIFO has overflowed and part of the received frame has been transferred to input buffer. 0: No overflow error occurred. 1: RxFIFO overflow occurred and frame data is invalid.
Page 717 Bit field Name Description 0: No reception error occurred. 1: A reception error has occurred. Dribble bit error. This bit is only valid in MII mode, indicating that the received frame length is not an integer multiple of bytes. 0: No Dribble bit error occurred. 1: A Dribble bit error has occurred.
Page 718 Bit field Name Description Note: When RER=1, even if this bit is set, the next descriptor will return the list base address. 23:22 Reserved Reserved, the reset value must be maintained. Receive buffer 2 size. 21:11 RBS2[10:0] These bits indicate the size of receive buffer 2 in bytes. The buffer size must be set to a multiple of 4.
Page 719 • Before EOF is received, the buffer of current descriptor is full, and the entire buffer of current descriptor is not large enough to receive the entire frame • A complete frame is received and forwarded to receive buffer, but current descriptor has not been closed •...
Page 720: Precision Time Protocol (Ptp)
Set ETH_DMABUSMOD register bus access related parameters. Set ETH_DMAINTEN register to mask unnecessary interrupt sources. First write the base address of the transmit descriptor list into ETH_DMATXDLADDR register, and then write the base address of the receive descriptor list into ETH_DMARXDLADDR register. Configure the relevant filter registers as required.
Page 721: Figure 25-9 System Time Precision Calibration
characteristics of the crystal oscillator used, as well as how often the synchronization process is performed. System time calibration method The 64-bit PTP system time is used as the basis for recording send/receive timestamps, and is updated by PTP input reference clock.
Page 722 slave device is SLOCALT(n), and the local time of the master device is MLOCALT(n), the master clock count between two SYNC messages is MCLOCKC(n), the slave clock count between two SYNC messages is SCLOCKC(n), and the slave clock frequency adjustment factor is SCFAF(n) ), the clock addend value of the addend register is Clock_Addend_Value(n), then the calculation method to determine the synchronization frequency in multiple SYNC cycles is as follows, but note that multiple SYNC messages may be required to complete the synchronization of the master and slave devices according to the situation:...
Page 723: Typical Ethernet Configuration Flow Example
Set ETH_PTPTSCTRL.TSTRIG to 1 to enable timestamp interrupt; When timestamp interrupt occurs, read the value of ETH_MACINTSTS register and clear the corresponding interrupt flag bit; Write the original value into the timestamp addend register, then set ETH_PTPTSCTRL.TSADDREG to 1, and update the value to PTP module.
Page 724: Ethernet Interrupt
DMA transmission and reception by setting ETH_DMAOPMOD.ST and ETH_DMAOPMOD.SR to 1. When transmit frame data: Select one or more transmit descriptors, write the transmit frame data to the buffer address specified in the transmit descriptor, and set TDES0.OWN in transmit descriptor to make DMA occupy descriptor; Write any value into ETH_DMATXPD register to make TxDMA exit the suspend mode and start sending data;...
Page 725: Eth Register
25.4.11.1.2 Ethernet DMA interrupts DMA controller has two types of interrupt events, normal and abnormal, and has a corresponding interrupt enable bit to control whether an interrupt is generated. When the interrupt enable bit is cleared, or all interrupt events are cleared, the corresponding interrupt summary bit is also cleared.
Page 726 Offset Register ETH_MACINTMSK 03Ch Reserved Reserved Reserved Reset Value ETH_MACADDR0HI ADDRHI[15:0] 040h Reserved Reset Value ETH_MACADDR0LO ADDRLO[31:0] 044h Reset Value ETH_MACADDR1HI MBC[5:0] ADDRHI[15:0] 048h Reserved Reset Value ETH_MACADDR1LO ADDRLO[31:0] 04Ch Reset Value ETH_MACADDR2HI MBC[5:0] ADDRHI[15:0] 050h Reserved Reset Value ETH_MACADDR2LO ADDRLO[31:0] 054h Reset Value...
Page 727 Offset Register ETH_MMCRXFCECNT CNT[31:0] 194h Reset Value ETH_MMCRXFAECNT CNT[31:0] 198h Reset Value ETH_MMCRXGUFCNT CNT[31:0] 1C4h Reset Value ETH_PTPTSCTRL 700h Reserved Reset Value ETH_PTPSSINC SSINC[7:0] 704h Reserved Reset Value ETH_PTPSEC TSS[31:0] 708h Reset Value ETH_PTPNS TSSS[30:0] 70Ch Reset Value ETH_PTPSECUP TSS[31:0] 710h Reset Value ETH_PTPNSUP...
Page 728: Eth Mac Configuration Register (Eth_Maccfg)
Offset Register ETH_DMAMFBOCNT OVFFRMCNT[10:0] MISFRMCNT[15:0] 1020h Reserved Reset Value ETH_DMACHTXDESC ADDR[31:0] 1048h Reset Value ETH_DMACHRXDESC ADDR[31:0] 104Ch Reset Value ETH_DMACHTXBADDR ADDR[31:0] 1050h Reset Value ETH_DMACHRXBADDR ADDR[31:0] 1054h Reset Value 25.5.2 ETH MAC configuration register (ETH_MACCFG) Address offset: 0x0000 Reset value: 0x0000 8000 MAC configuration register is the operating mode register of the MAC.
Page 729 Bit field Name Description In half-duplex mode, these bits can be configured with a minimum interframe gap of 64-bit time. DCRS Disable carrier sense function. 0: MAC will report an error and terminate the transmission when the carrier signal is wrong.
Page 730: Eth Mac Frame Filter Register (Eth_Macfflt)
Bit field Name Description 01：k = min(n, 8) 10：k = min(n, 4) 11：k = min(n, 1) Where: n = number of retransmissions. Note: These bits are only valid in half-duplex mode. Deferral inspection. This bit is only valid in half-duplex mode. 0: Disable MAC deferral check function.
Page 731 Bit field Name Description 30:11 Reserved Reserved, the reset value must be maintained. HASH or perfect filtering. 0: If ETH_MACFFLT.HMC or ETH_MACFFLT.HUC is set to 1, only frames that conform to the HASH filter can pass the receive address filter. 1: If ETH_MACFFLT.HMC or ETH_MACFFLT.HUC is set to 1, and the received frame passes either HASH filter or the perfect filter, it is considered that it has passed the receiving address filter.
Page 732: Eth Mac Hash List High Register (Eth_Machashhi)
Bit field Name Description multicast frame with the set value of the destination address register. 1: MAC filters the destination address of the received multicast frame according to the HASH list. Unicast HASH filter. 0: MAC will compare the value of the destination address field of the received unicast frame with the set value of the destination address register.
Page 733: Eth Mac Mii Address Register (Eth_Macmiiaddr)
Bit field Name Description 31:0 HTL[31:0] HASH list low. These bits are the lower 32 bits of the HASH list. 25.5.6 ETH MAC MII address register (ETH_MACMIIADDR) Address offset: 0x0010 Reset value: 0x0000 0000 This register controls the management signals of the external PHY through the interface. Bit field Name Description...
Page 734: Eth Mac Mii Data Register (Eth_Macmiidat)
Bit field Name Description ETH_MACMIIDAT. When accessing the PHY, this bit is set by the application program to indicate that a read or write operation is being performed on the PHY. When writing to the PHY, the value of the ETH_MACMIIDAT register must be retained until this bit is cleared by hardware.
Page 735 Bit field Name Description 15:8 Reserved Reserved, the reset value must be maintained. DZQP Disable zero-value PAUSE function. 0: Normal operation, turning on the automatic generation of zero-value PAUSE control frames. 1: When the FIFO layer flow control signal is withdrawn, the automatic generation of the automatic zero-valued PAUSE control frame is turned off.
Page 736: Eth Mac Vlan Tag Register (Eth_Macvlantag)
Bit field Name Description PAUSE frame to the interface. During the process of transmit the control frame, the bit is always 1, and MAC resets this bit to 0 after the PAUSE control frame is transmitted. In half-duplex mode, setting this bit to 1 activates the backpressure function. When the backpressure function is valid, if MAC receives a new frame, it will transmit a blocking signal at the sender to notify that there is a conflict.
Page 737: Eth Mac Remote Wakeup Frame Filter Register (Eth_Macrmtwufrmflt)
25.5.10 ETH MAC remote wakeup frame filter register (ETH_MACRMTWUFRMFLT) Address offset: 0x0028 Reset value: 0x0000 0000 This register is essentially a pointer to 8 opaque wakeup frame filter registers (using the same offset). 8 consecutive write operations to this register address (offset 0x0028) can write all 8 wake-up frame filter registers; 8 consecutive read operations to this register address (offset 0x0028) can read all 8 wake-up frame filter registers.
Page 738: Eth Mac Interrupt Status Register (Eth_Macintsts)
Bit field Name Description MGKPRCVD Magic Packet received. This bit is cleared to 0 by reading this register. 0: No Magic Packet wakeup frame was received. 1: A Magic Packet wakeup frame is received and a wakeup event occurs. Reserved Reserved, the reset value must be maintained.
Page 739: Eth Mac Interrupt Mask Register (Eth_Macintmsk)
Bit field Name Description 0: ETH_MACINTSTS.MMCTXIS and ETH_MACINTSTS.MMCRXIS are both 0. 1: One of ETH_MACINTSTS.MMCTXIS and ETH_MACINTSTS.MMCRXIS is 1. PMTIS PMT status. In low power mode, this bit is set to 1 when a remote wakeup frame or Magic Packet wakeup frame is received.
Page 740: Eth Mac Address 0 Low Register (Eth_Macaddr0Lo)
Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained. 15:0 ADDRHI[15:0] MAC address 0 high 16 bits. These bits contain the upper 16 bits of the 6-byte MAC address 0. These bits are used as the address filtering of the received frame, it is also used in transmit flow control, and is inserted as the source address of the frame when transmit a PAUSE frame.
Page 741: Eth Mac Address 1 Low Register (Eth_Macaddr1Lo)
Bit field Name Description 1: Address filter uses MAC address 1 for perfect filtering. Source address comparison. 0: MAC address 1 is used to compare with the destination address of the received frame. 1: MAC address 1 is used to compare with the source address of the received frame. 29:24 MBC[5:0] Mask byte control bits.
Page 742: Eth Mac Address 2 Low Register (Eth_Macaddr2Lo)
Bit field Name Description Address enable. 0: Address filter does not use MAC address 2 for perfect filtering. 1: Address filter uses MAC address 2 for perfect filtering. Source address comparison. 0: MAC address 2 is used to compare with the destination address of the received frame.
Page 743: Eth Mac Address 3 High Register (Eth_Macaddr3Hi)
25.5.20 ETH MAC address 3 high register (ETH_MACADDR3HI) Address offset: 0x0058 Reset value: 0x0000 FFFF Bit field Name Description Address enable. 0: Address filter does not use MAC address 3 for perfect filtering. 1: Address filter uses MAC address 3 for perfect filtering. Source address comparison.
Page 744: Eth Mmc Control Register (Eth_Mmcctrl)
Bit field Name Description 31:0 ADDRLO[31:0] MAC address 3 low 32 bits. These bits contain the lower 32 bits of the 6-byte MAC address 3. 25.5.22 ETH MMC control register (ETH_MMCCTRL) Address offset: 0x0100 Reset value: 0x0000 0000 Bit field Name Description 31:4...
Page 745: Eth Mmc Transmit Interrupt Status Register (Eth_Mmctxint)
This register records the interrupt generated when the receive statistics register counts to half the maximum value (the highest bit of the counter is set). Reading the MMC counter that generates an interrupt can clear the corresponding interrupt bit (must read the lower 8 bits of the corresponding counter). Bit field Name Description...
Page 746: Eth Mmc Receive Interrupt Mask Register (Eth_Mmcrxintmsk)
Bit field Name Description 0: Transmit "good" frame counter value has not reached half of the maximum value. 1: Transmit "good" frame counter value reaches half of the maximum value. 20:16 Reserved Reserved, the reset value must be maintained. TXMCOLGFIS More than 1 collision state was encountered while transmit a "good"...
Page 747: Eth Mmc Transmit Interrupt Mask Register (Eth_Mmctxintmsk)
25.5.26 ETH MMC transmit interrupt mask register (ETH_MMCTXINTMSK) Address offset: 0x0110 Reset value: 0x0000 0000 Bit field Name Description 31:22 Reserved Reserved, the reset value must be maintained. TXGFRMIM Transmit "good" frame interrupt mask bit. 0: Do not mask the interrupt that occurs when ETH_MMCTXINT.TXGFRMIS is 1. 1: Mask the interrupt that occur when the ETH_MMCTXINT.TXGFRMIS bit is 1.
Page 748: Eth Mmc Transmitted "Good" Frame Counter Register After More Than 1 Collision
Bit field Name Description 31:0 CNT[31:0] Transmitted "good" frame counter after 1 collision. These bits are a counter of "good" frame transmitted after 1 collision. 25.5.28 ETH MMC transmitted “good” frame counter register after more than 1 collision (ETH_MMCTXGFAMSCCNT) Address offset: 0x0150 Reset value: 0x0000 0000 This register is used to count the number of frames successfully transmitted after more than one collision in half- duplex mode.
Page 749: Eth Mmc Crc Error Received Frame Counter Register (Eth_Mmcrxfcecnt)
25.5.30 ETH MMC CRC error received frame counter register (ETH_MMCRXFCECNT) Address offset: 0x0194 Reset value: 0x0000 0000 This register is used to count the number of frames with CRC errors in the received frames. Bit field Name Description 31:0 CNT[31:0] CRC error received frame counter.
Page 750: Eth Ptp Timestamp Control Register (Eth_Ptptsctrl)
This register is used to count the number of "good" unicast frames received. Bit field Name Description 31:0 CNT[31:0] "Good" unicast frame receive counter. These bits are a counter of "good" unicast frames received. 25.5.33 ETH PTP timestamp control register (ETH_PTPTSCTRL) Address offset: 0x0700 Reset value: 0x0000 0000 This register controls the timestamp generation and update logic.
Page 751: Eth Ptp Subsecond Increment Register (Eth_Ptpssinc)
Bit field Name Description the update is completed. TSINIT Timestamp system time initialization bit. Before setting this bit, must ensure that this bit read 0. 0: System time remains unchanged. 1: Initialize system time and replace the original system time with the values of the timestamp high and low update registers.
Page 752: Eth Ptp Timestamp Low Register (Eth_Ptpns)
Bit field Name Description 31:0 TSS[31:0] System time seconds. These bits represent the second value of the MAC's current system time. 25.5.36 ETH PTP timestamp low register (ETH_PTPNS) Address offset: 0x070C Reset value: 0x0000 0000 This register is read-only and contains the subsecond value of the system time. Bit field Name Description...
Page 753: Eth Ptp Timestamp Low Update Register (Eth_Ptpnsup)
Bit field Name Description 31:0 TSS[31:0] Timestamp seconds update value. The value represented by these bits is used to replace the system time when initialized, and when updated, it represents the value of seconds added or subtracted from the system time. 25.5.38 ETH PTP timestamp low update register (ETH_PTPNSUP) Address offset: 0x0714 Reset value: 0x0000 0000...
Page 754: Eth Ptp Target Time High Register (Eth_Ptpttsec)
Bit field Name Description 31:0 TSA[31:0] Timestamp addend. These bits represent the 32-bit value added to the accumulator when the clocks are synchronized. 25.5.40 ETH PTP target time high register (ETH_PTPTTSEC) Address offset: 0x071C Reset value: 0x0000 0000 Bit field Name Description 31:0...
Page 755: Eth Dma Bus Mode Register (Eth_Dmabusmod)
25.5.42 ETH DMA bus mode register (ETH_DMABUSMOD) Address offset: 0x1000 Reset value: 0x0000 2101 Bit field Name Description 31:26 Reserved Reserved, the reset value must be maintained. AALB Address alignment. 0: Disable the transfer address alignment function. 1: Enable transfer address alignment, if ETH_DMABUSMOD.FB is 1, the AHB interface aligns all LS bits of consecutive transfers to the starting address.
Page 756 Bit field Name Description This bit controls whether the AHB master interface performs fixed burst length transfers. 0: AHB uses only SINGLE and INCR data transfer operations during continuous transfer. 1: AHB uses SINGLE, INCR4, INCR8 and INCR16 data transfer operations during continuous transfer.
Page 757: Eth Dma Transmit Query Request Register (Eth_Dmatxpd)
25.5.43 ETH DMA transmit query request register (ETH_DMATXPD) Address offset: 0x1004 Reset value: 0x0000 0000 This register is used for TxDMA to query the list of transmit descriptors. TxDMA usually enters the pending state due to a data underflow error in the transmit frame or the descriptor is occupied by the CPU (TDES0.OWN = 0). Any value can be written to this register to enable sending queries.
Page 758: Eth Dma Receive Descriptor List Address Register (Eth_Dmarxdladdr)
25.5.45 ETH DMA receive descriptor list address register (ETH_DMARXDLADDR) Address offset: 0x100C Reset value: 0x0000 0000 The receive descriptor list register points to the beginning of the receive descriptor queue. Descriptor queues are located in physical memory, and their addresses must be word-aligned. Writing to this register is only allowed when reception is stopped.
Page 759: Eth Dma Status Register (Eth_Dmasts)
25.5.47 ETH DMA status register (ETH_DMASTS) Address offset: 0x1014 Reset value: 0x0000 0000 This register contains all the status bits that the DMA feeds back to the application. Software usually reads this register in an interrupt service routine or during polling. Most bits in this register can trigger interrupts. Reading this register does not clear the flags in it.
Page 760 Bit field Name Description 0: Error during RxDMA transfer of data. 1: Error during TxDMA transfer of data. EB[1]: 0: Error during write transfer. 1: Error during read transfer. EB[2]: 0: Error during data buffer access. 1: Error during descriptor access. 22:20 TPS[2:0] Transmit process status.
Page 761 Bit field Name Description • ETH_DMASTS [5]: Transmit data underflow • ETH_DMASTS [7]: Receive buffer unavailable • ETH_DMASTS [8]: Receive process stopped • ETH_DMASTS [9]: Receive watchdog timeout • ETH_DMASTS [10]: Early send interrupt • ETH_DMASTS [13]: Bus fatal error Only unmasked interrupts will affect this bit.
Page 762: Eth Dma Operation Mode Register (Eth_Dmaopmod)
Bit field Name Description 0: No transmit data underflow error occurred. 1: Data underflow error occurred during frame transmission. Receive overflow status. When this bit is 1, if some frame data has been forwarded to the memory, set RDES0.OE to 1. 0: No receive data overflow error occurred.
Page 763 Bit field Name Description Do not drop TCP/IP checksum error frames. 0: If ETH_DMAOPMOD.FEF is 0, MAC discards all erroneous frames. 1: If the received frame has only checksum errors, MAC will not discard the frame. Receive store-and-forward. 0: RxFIFO works in cut-through (threshold) mode, and the forwarding threshold is determined by these bits of ETH_DMAOPMOD.RTC[1:0].
Page 764 Bit field Name Description 1: Transmit process enters running state. TxDMA obtains the current transmit descriptor, and the transmit frame descriptor can be obtained from the ETH_DMATXDLADDR base address. If the last transmission was stopped, it can also be obtained from the pointer position of the transmit descriptor queue. If the TDES0.OWN of the current descriptor is 0, the TxDMA enters suspend (suspended) state and sets ETH_DMASTS.TU to 1.
Page 765: Eth Dma Interrupt Enable Register (Eth_Dmainten)
Bit field Name Description 1: Put the receiving process into the running state, and the DMA checks the current position of the receiving descriptor queue to process the next received frame. The receiving frame descriptor can be obtained from the base address of ETH_DMARXDLADDR, or from the pointer position of the receiving descriptor queue if the last receiving was stopped.
Page 766 Bit field Name Description • ETH_DMASTS[5]: Transmit underflow • ETH_DMASTS[7]: Receive buffer unavailable • ETH_DMASTS[8]: Receive process stop • ETH_DMASTS[9]: Receive watchdog timeout • ETH_DMASTS[10]: Early transmit interrupt • ETH_DMASTS[13]: Bus fatal error ERIE Early receive interrupt enable. 0: Mask early receive interrupt. 1: When ETH_DMAINTEN.NISE is 1, enable early receive interrupt.
Page 767: Eth Dma Missed Frames And Buffer Overflow Counter Register (Eth_Dmamfbocnt)
Bit field Name Description Transmit interrupt enable. 0: Mask transmit interrupt. 1: When ETH_DMAINTEN.NISE is 1, enable transmit interrupt. 25.5.50 ETH DMA missed frames and buffer overflow counter register (ETH_DMAMFBOCNT) Address offset: 0x1020 Reset value: 0x0000 0000 Ethernet DMA has 2 counters to count the number of frames lost during reception. The current value of the counter can be obtained by reading this register.
Page 768: Eth Dma Current Receive Descriptor Address Register (Eth_Dmachrxdesc)
Bit field Name Description 31:0 ADDR[31:0] Transmit descriptor address pointer. These bits are cleared on reset and are automatically updated by TxDMA during operation. 25.5.52 ETH DMA current receive descriptor address register (ETH_DMACHRXDESC) Address offset: 0x104C Reset value: 0x0000 0000 This register points to the start address (base address) of the receive descriptor that RxDMA is reading.
Page 769: Eth Dma Current Receive Buffer Address Register (Eth_Dmachrxbaddr)
Bit field Name Description 31:0 ADDR[31:0] Transmit buffer address pointer. These bits are cleared on reset and updated by TxDMA during operation. 25.5.54 ETH DMA current receive buffer address register (ETH_DMACHRXBADDR) Address offset: 0x1054 Reset value: 0x0000 0000 This register points to the address of the receive buffer that RxDMA is reading. Bit field Name Description...
Page 770: Comparator (Comp)
Comparator (COMP) The COMP module is used to compare the analog voltages of two inputs and output high/low levels based on the comparison results. When "INP" input voltage is higher than "INM" input voltage, the comparator output is high level, when "INP" input voltage is lower than "INM" input voltage, the comparator output is low level. COMP system connection block diagram The COMP module supports a maximum of seven independent comparators, which are connected to the APB1 bus..
Page 771: Figure 26-2 Comparator3 And Comparator4 Connection Diagram
Figure 26-2 Comparator3 and comparator4 connection diagram PB10/PC10/PA2 PB14 COMP Interrupt COMP3 TIM1_BKIN PB12 Polarity Selection TIM1_OCrefClear TIM1_IC1 DAC1/PA4 Window DAC2/PA5 TIM2_IC3 Window mode mode VREF1 TIM2_OCrefClear VREF2 TIM4_IC2 TIM4_OCrefClear TIM5_IC2 TIM8_BKIN TIM1_BKIN +TIM8_BKIN PC5/PB12/PC11 COMP4 COMP Interrupt PB15 Polarity Selection TIM1_BKIN PB13 TIM3_IC3...
Page 772: Figure 26-3 Comparator5,Comparator6,Comparator7 Connection Diagram
Figure 26-3 Comparator5,Comparator6,comparator7 connection diagram PA11/PB0/PB6/PB11 COMP5 COMP Interrupt PB10 Polarity Selection TIM1_BKIN PD10 TIM2_IC4 Window Window DAC1/PA4 TIM2_OCrefClear mode mode DAC2/PA5 TIM3_IC4 VREF1 TIM3_OCrefClear VREF2 TIM4_IC4 TIM4_OCrefClear TIM8_BKIN TIM8_OCrefClear TIM8_IC1 TIM1_BKIN + TIM8_BKIN PA12/PB7/PC9 COMP Interrupt COMP6 TIM1_BKIN Polarity Selection TIM2_IC1 DAC1/PA4 TIM2_OCrefClear...
Page 773: Main Features
Main features • Up to 7 independent comparators. • Built-in two 64 level programmable comparison voltage reference sources VREF1, VREF2. • Support filter clock, filter reset. • Output polarity can be configured high and low. • Hysteresis The value can be none, low, medium, or high. •...
Page 774: Comp Working Mode
11. Enable COMPx_CTRL.EN on the comparator Note: For the above steps, the filter should be enabled first and then the comparator should be enabled. The comparator should be enabled after the filtering (if enabled) is configured and enabled. In addition, when the comparator control register is locked, the LOCK can be cancelled only through reset.
Page 775: Interrupt
PB15 Other The comparator INM pins have the following configuration. INMSEL COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 PB12 PB10 DAC1/PA4 PB13 PD10 DAC1/PA4 DAC2/PA5 DAC1/PA4 DAC1/PA4 DAC1/PA4 DAC1/PA4 DAC1/PA4 DAC2/PA5 VREF1 DAC2/PA5 DAC2/PA5 DAC2/PA5 DAC2/PA5 DAC2/PA5 VREF1 VREF2 VREF1 VREF1 VREF1 VREF1...
Page 776: Comp Register
• The polarity of COMPx_CTRL.POL is reversed, and the interrupt is enabled. When INPSEL < INMSEL, the comparator interrupt is generated when COMPx_CTRL.OUT is set to 1 by hardware. COMP register 26.7.1 COMP register overview Table 26-1 COMP register overview Offset Register COMP1_CTRL...
Page 777 Offset Register COMP4_CTRL 040h Reset Value COMP4_FILC 044h Reset Value COMP4_FILP CLKPSC[15:0] 048h Reserved Reset Value 04Ch Reserved COMP5_CTRL 050h Reset Value COMP5_FILC 054h Reset Value COMP5_FILP CLKPSC[15:0] 058h Reserved Reset Value 05Ch Reserved COMP6_CTRL 060h Reset Value COMP6_FILC 064h Reset Value COMP6_FILP CLKPSC[15:0]...
Page 778: Comp Control Register (Compx_Ctrl)
Offset Register COMP_WINMODE 080h Reset Value COMP_LOCK 084h Reset Value 088h Reserved COMP_INTEN 08Ch Reset Value COMP_INTSTS 090h Reset Value COMP_VREFSCL 094h Reset Value 26.7.2 COMP control register (COMPx_CTRL) Comparator 1's INPDAC is valid, comparator 2 to comparator 7, the INPDAC bits are invalid. Address offset : 0x10,0x20,0x30,0x40,0x50,0x60,0x70 Reset value : 0x0000 0000 Bit field...
Page 779: Comp Window Mode Register (Comp_Winmode)
Bit field Name Description Other configurations: reserved. 13:12 HYST[1:0] These bits control the hysteresis level. 00: No hysteresis; 01: Low hysteresis; 10: Medium hysteresis; 11: High hysteresis. This bit is used to invert the comparator output. 0: Output is not inverted; 1: Output is inverted.
Page 780: Comp Lock Register (Comp_Lock)
Bit field Name Description input. 0: Comparators 1 and 2 are not in window mode. 1: Comparators 1 and 2 are in window mode. 26.7.4 COMP lock register (COMP_LOCK) Address offset : 0x84 Reset value : 0x0000 0000 Bit field Name Description 31:7...
Page 781: Comp Interrupt Status Register (Comp_Intsts)
Bit field Name Description CMP6IEN Same function as CMP7IEN. CMP5IEN Same function as CMP7IEN. CMP4IEN Same function as CMP7IEN. CMP3IEN Same function as CMP7IEN. CMP2IEN Same function as CMP7IEN. CMP1IEN Same function as CMP7IEN. 26.7.6 COMP interrupt status register (COMP_INTSTS) Address offset : 0x90 Reset value : 0x0000 0000 Bit field...
Page 782: Comp Filter Frequency Division Register (Compx_Filp)
Bit field Name Description 0: Disable 1: Enable 26.7.8 COMP filter frequency division register (COMPx_FILP) Address offset : 0x18,0x28,0x38,0x48,0x58,0x68,0x78 Reset value : 0x0000 0000 Bit field Name Description 31:16 Reserved Reserved, the reset value must be maintained 15:0 CLKPSC[15:0] Low filter sample clock prescale. System clock divider = CLK_PRE_CYCLE + 1, 0: Every cycle 1: Every 2 cycle...
Page 783 Bit field Name Description 1: enable. 783 / 816...
Page 784: Operational Amplifier (Opamp)
Operational Amplifier (OPAMP) The OPAMP module can be flexibly configured, suitable for applications such as independent op amp mode , programmable gain amplifier and follower mode, The internal op-amps can be configured as combined amplifiers with different gains or cascaded using external resistors..OPAMP has an input range of 0V to VDDA and an output range of 0.1V to VDDA-0.1V.
Page 785: Figure 27-1 Block Diagram Of Opamp1 And Opamp2 Connection Diagram
Figure 27-1 Block diagram of OPAMP1 and OPAMP2 connection diagram DAC2/PA5 ADC1 Channel3 OPAMP1 ADC2 Channel3 OPAMP2 785 / 816...
Page 786: Internal Connection Between Opamp And Comp
Figure 27-2 Block diagram of OPAMP3 and OPAMP4 connection diagram DAC2/PA5 ADC3 Channel1 OPAMP3 PB11 DAC1/PA OPAMP4 ADC4 Channel3 PB10 PB12 27.1.2 Internal connection between OPAMP and COMP OPAMP1, OPAMP2, COMP1, COMP2, COMP3, ADC1 and ADC2 constitute a group of analog linkage applications, and the topology relationship is as follows: 786 / 816...
Page 787: Figure 27-3 Simulation Module Linkage Relationship 1
Figure 27-3 Simulation module linkage relationship 1 VREF1 and VREF2 can be adjusted in average 64 steps based on VDDA PB10 PA0/PB1/PA11/PB8 COMP1 COMP Interrupt Polarity Selection TIM1_BKIN DAC1/PA4 TIM1_OCrefClear DAC2/PA5 TIM1_IC1 VREF1 TIM2_IC1 VREF2 TIM2_OCrefClear TIM3_IC1 DAC2/PA5 TIM3_OCrefClear TIM4_IC1 ADC1 Channel3 OPAMP1 TIM4_OCrefClear...
Page 788: Figure 27-4 Simulation Module Linkage Relationship 2
Figure 27-4 Simulation module linkage relationship 2 VREF1 and VREF2 can be adjusted in average 64 steps based on VDDA PB15 PC5/PB12/PC11 COMP4 COMP Interrupt Polarity Selection TIM1_BKIN PB13 TIM3_IC3 DAC1/PA4 TIM3_OCrefClear DAC2/PA5 TIM4_IC3 DAC2/PA5 VREF1 TIM4_OCrefClear VREF2 TIM5_IC3 TIM8_BKIN ADC3 Channel1 OPAMP3 TIM8_OCrefClear...
Page 789: Opamp Working Mode
OPAMP working mode 27.2.1 OPAMP independent op amp mode The amplification factor of the independent op amp mode is determined by the connected resistance and capacitance. When OPAMPx_CS.MOD is set to 2'b00 or 2'b01, it is the op amp function, OPAMPx_CS.VPSSEL or OPAMPx_CS.VPSEL selects the positive input, and OPAMPx_CS.VMSSEL or OPAMPx_CS.VMSEL selects the negative input.
Page 790: Opamp Internal Gain (Pga) Mode
Figure 27-6 Follow mode 27.2.3 OPAMP internal gain (PGA) mode The internal amplification mode, amplifies the input voltage through a built-in resistor feedback network. OPAMPx_CS. MOD = 2b’10 is a PGA function that supports 2/4/8/16/32 magnification. OPAMPx_CS. VMSSEL or OPAMPx_CS. VMSEL pins must be set to float. OPAMPx_CS.VPSSEL or OPAMPx_CS.VPSEL select positive input.The positive input can be connected to an external pin, which can be an output port for another OPAMP or a resistive network.Set OPAMPx_CS.
Page 791: Opamp With Filter Internal Gain Mode
Figure 27-7 Internal gain mode 27.2.4 OPAMP with filter internal gain mode In this mode, the amplification voltage is adjustable, supports 2/4/8/16/32, and the OPAMPx_CS.VPSSEL or OPAMAPx_CS.VPSEL is set to be connected to the external pin, and the negative of OPAMP can be connected to components such as capacitors.
Page 792: Opamp Calibration
27.2.5 OPAMP calibration The chip has been calibrated before delivery. Users can calibrate the chip again according to the actual environment. Note: Contact Nations for specific calibration methods to obtain relevant information. 27.2.6 OPAMP independent write protection By configuring the OPAMP_LOCK register, the write protection of OPAMP can be set independently.After the write protection is set, the software cannot write to the corresponding OPAMP register.
Page 793: Opamp Control Status Register (Opampx_Cs)
Offset Register OPAMP_CS4 030h Reserved Reset Value OPAMP_LOCK 040h Reserved Reset Value 27.3.2 OPAMP Control Status Register (OPAMPx_CS) Offset address: 0x00,0x10,0x20,0x30 Reset value: 0x0000 0000 Bit field Name Description 31:22 Reserved Retained, the reset value must be maintained. 21:19 VPSSEL[2:0] OPAMP non inverted input secondary selection VPSSEL[2:0] OPAMP1...
Page 794 Bit field Name Description automatically switches between OPAMP3 and OPAMP4. 0: Disable automatic switching; 1: Enable automatic switching. RANGE OPAMP voltage range (OPAMP Operational amplifier power supply range). 0: Low voltage range (VDDA < 2.4V); 1: High voltage range. CALOUT OPAMP calibration output (Operation amplifier calibration output) When this signal toggles, the offset during calibration mode is calibrated.
Page 795: Opamp Lock Register (Opamp_Lock)
Bit field Name Description 1: Enable. 27.3.3 OPAMP Lock register (OPAMP_LOCK) Offset address: 0x40 Reset value: 0x0000 0000 Bit field Name Description 31:4 Reserved Reserved, the reset value must be maintained OPAMP4LK OPAMP4 lock (OPAMP4 lock bit) After the reset, this bit can be written only once 0: OPAMP4 register can read and write;...
Page 796: Dvp Interface (Dvp)
DVP interface (DVP) Introduction DVP is a flexible and powerful CMOS optical sensor interface, which can easily achieve the customer's image capture requirements, and the entire capture process does not require CPU intervention. The functional characteristics of the DVP interface module are as follows: •...
Page 797: Interface Timing
28.2.2 Interface Timing Figure 28-1 DVP interface timing example DVP_PCLK DVP_VSYNC DVP_HSYNC DVP_D[7:0] As shown in above figure: • DVP_PCLK is the pixel clock, and capture 1 byte (8bit) of valid data per clock cycle; • DVP_VSYNC is a vertical sync (frame sync) signal, active high; •...
Page 798: Dma Application
28.3.2 DMA application Configure and enable the corresponding DMA channel (DMA2 channel 8); Configure the DVP FIFO watermark value (register DVP_CTRL.FWM) to 1 (DMA mode only supports transfers with a watermark of 1); Enable DMA transfer (register DVP_INTEN.DMAEN); When the FIFO receives 1 WORD data, it will send a DMA request; The DMA moves the FIFO data to the designated SRAM area.
Page 799: Interrupts
is a synchronous reset, it must be ensured that the input pixel clock (DVP_PCLK) and the DVP module clock (APB2 clock PCLK2) exist at the same time. The soft reset requires 8 PCLK2 clock cycles to synchronize. Do not operate the registers during the soft reset. The soft reset only resets the state machine, not the registers.
Page 800: Dvp Register
DVP register 28.4.1 DVP register overview Table 28-2 DVP register overview Offset Register DVP_CTRL FWM[2:0] LSM[2:0] BSM[2:0] 000h Reserved Reset Value DVP_STS FCNT[2:0] 004h Reserved Reset Value DVP_INTSTS 008h Reserved Reset Value DVP_INTEN 00Ch Reserved Reset Value DVP_MINTSTS 010h Reserved Reset Value DVP_WST VST[10:0]...
Page 801 Bit field Name Description that both DVP_PCLK and PCLK2 are provided normally, at least 8 PCLK2 clock cycles can be guaranteed to reset successfully, and the DVP module register can be operated after the reset is completed. Soft reset only resets the internal logic of the DVP module, not the registers.
Page 802: Dvp Status Register Dvp_Sts
Bit field Name Description HSPOL Horizontal sync polarity. This bit indicates the level of the HSYNC pin when there is valid data on the parallel interface. 0: HSYNC active low 1: HSYNC active high capture mode. 0: Single frame mode. Once activated, the interface waits for the frame sync signal to be valid, and then starts transmitting data.
Page 803 Bit field Name Description 31:10 Reserved Reserved, the reset value must be maintained. HERRIS HSYNC error status. Software write 0 to clear. When the received row data is smaller than the configured data size per line, an HSYNC error is generated (HSYNC arrives early). 0: No error 1: There is an HSYNC error VERRIS...
Page 804: Dvp Interrupt Enable Register
Bit field Name Description 1: Line has started. FMEIS Frame end state. Software write 0 to clear. 0: Frame not ended. 1: Frame has ended. FMSIS Frame start state. Software write 0 to clear. 0: Frame not started. 1: Frame has started. 28.4.5 DVP Interrupt Enable Register Address offset : 0x0c Reset value : 0x0000 0000...
Page 805: Dvp Interrupt Trigger Status Register Dvp_Mintsts
Bit field Name Description FEIE FIFO empty interrupt enable. 0: Disable FIFO empty interrupt 1: Enable FIFO empty interrupt LEIE End of line interrupt enable. 0: End-of-line interrupt is not enabled 1: Enable end-of-line interrupt LSIE Line start interrupt enable. 0: Disable line start interrupt 1: Enable line start interrupt FMEIE...
Page 806: Dvp Image Start Register Dvp_Wst
Bit field Name Description FWMIS FIFO watermark interrupt status. This bit is related to the real-time status of the FIFO and can only be cleared by reading the FIFO. 0: The data length in the FIFO has not reached DVP_CTRL.FWM[2:0]. 1: The data length in the FIFO has reached DVP_CTRL.FWM[2:0] and interrupt triggered.
Page 807: Dvp Image Size Register Dvp_Wsize
Bit field Name Description 31:24 Reserved Reserved, the reset value must be maintained. 23:13 VST[10:0] Start line number, the first line starts at 0. 12:11 Reserved Reserved, the reset value must be maintained. 10:0 HST[10:0] Starting pixel number, the first pixel starts at 0. 28.4.8 DVP image size register（DVP_WSIZE）...
Page 808: Debug Support (Dbg)
Debug support (DBG) Overview N32G45x uses Cortex -M4F core, which integrates hardware debugging module. Support instruction breakpoint (stop when instruction fetches value) and data breakpoint (stop when data access). When the kernel is stopped, the user can view the internal state of the kernel and the external state of the system. After the user's query operation is completed, the kernel and peripherals can be restored, and the corresponding program can continue to be executed.
Page 809: Jtag/Swd Function
• DWT: data trigger Reference: • Cortex -M4 Technical Reference Manual (TRM) • ARM debugging interface V5 structure specification • ARM CoreSight development tool set (r1p0 version) technical reference manual The system supports low-power mode debugging and debugging of some peripherals. The peripherals supporting debugging include: CAN, I2C interface and TIMER, WWDG and IWDG modules.
Page 810: Mcu Debugging Function
JTMS/SWDIO PA13 JTCK/SWCLK PA14 JTDI PA15 JTDO NJTRST • When both JTAG debugging interface and SWD debugging interface are enabled, the 5-wire JTAG debugging interface will be used by default after reset. • When using JTAG interface, users can not use NJTRST pin. In this case, NJTRST pin (PB4, internal hardware pull-up) can be used as a general-purpose GPIO.
Page 811: Dbg Registers
• WWDG/IWDG peripheral: WWDG/IWDG counter clock stops and debugs; • CAN peripheral: the CAN interface receiving register stops counting and debugs. DBG registers 29.4.1 DBG register overview These peripheral registers must be operated as words (32 bits). The base address of the register is 0xE004 2000. Table 29-2 DBG register overview Offset Register...
Page 812: Debug Control Register (Dbg_Ctrl)
Bit field Name Description Chip FLASH capacity is FLASH[3:0] * 64KB 15:12 DEV_NUM_H[3:0] The upper 4 digits of the device model. See the description of DEV_NUM_L[3:0]. 11:8 DEV_NUM_M[3:0] The middle 4 digits of the device model. See the description of DEV_NUM_L[3:0]. REV_NUM_H[3:0] High 4 bits of MCU version number REV_NUM_L[3:0]...
Page 813 Bit field Name Description WWDG_STOP When the kernel enters the debug state, the debug window watchdog stops working. Set or cleared by software. 0: The window watchdog counter still works normally; 1: Window watchdog counter stops working. IWDG_STOP The watchdog stops working when the kernel enters the debugging state. Set or cleared by software.
Page 814: Unique Device Serial Number (Uid)
Unique device serial number (UID) Introduction MCU series products have two built-in unique device serial numbers with different lengths, namely 96-bit UID (Unique device ID) and 128-bit UCID (Unique Customer ID). These two device serial numbers are stored in the system configuration block of the flash memory, and the information is programmed during manufacture, and any MCU microcontroller is guaranteed to be unique under any circumstances.
Page 815: Version History
Version history Version Date Changes V3.0 2022.7.8 Initial version V3.1.0 2022.09.07 Modify VERF to VREF in chapter 26.5 Setion 7.2.5.7, add TIMx_ETR Figure 12-1, Add description of ETR Delete RTC periodic wake-up support Standby mode. Modfiy PVD threshold gear information description error. Modfiy Figure 21-25 I2S clock generator structure.
Page 816: Dislcaimer
This document is the exclusive property of NSING TECHNOLOGIES PTE. LTD.(Hereinafter referred to as NSING). This document, and the product of NSING described herein (Hereinafter referred to as the Product) are owned by NSING under the laws and treaties of Republic of Singapore and other applicable jurisdictions worldwide. The intellectual properties of the product belong to Nations Technologies Inc.

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