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PDP-10
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Digital Equipment PDP-10 Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Reader's Comments
First Class
Table of Contents
Reference Material
General Description
PDP-10 I/O Bus Information Flow
Read-In Mode Data Format
PDP-10 I/O Bus Signals
Transmitting and Receiving Modules
Control Interface
Data Interface
SKIP Device (for CONSO and CONSZ)
Control Device
Interface Logic for Larger Devices
Data Interface for Larger Devices
Sources and Loads Shown Without Connections
Wired and
Wired or
Flip-Flop Representation
DCD Gate
Different Uses of a Particular Module
Trailing Edge Triggering
Module Information
Measurement Definitions
Inter-Series Pulse Conversion
Pulses
Input Loading
Technical Data
Up Counter Arrangement of B166 Module
B213 with Negative Data Input
B213 as Bus Driver
Flat Washer
Typical Connections, W102
Power Control Block Diagram
W991 Module, Location AB28
W990 Module, Location B06
Cable Connections to GPIOL
User Terminals
Functional Requirements
20 Ma, Full Duplex Terminal Interface
Bus Operation
Possible Memory Bus Arrangement
Memory Bus Information Flow
Interface Specifications
Memory Bus Signals
Pin Assignments
Memory Bus Timing
Memory Module Selection Decoding
Data and Parity Lines
Hypothetical Memory Control Flow Diagram
Enable Level Generator
Memory Cycle Flip-Flop Register
Memory Cycle Timing Chain
Channel Reset
Channel Register Organization
Electrical Characteristics
Channel Interconnections
Channel Bus Synchronizing Logic
Margin Check Bus Layout
Margin Bus Circuit
Ground Mesh
Waveform Requirements
Level Transmission Line
Driving Waveform
Waveforms During Reflection
CONTENTS (Cont)
Channel Bus
Installation Instructions
End Panel
Indicators and Switches
Memory Buffer
Control Word
Operational Description
Principles of Operation
Detailed Logic Description
Preventive Maintenance
Corrective Maintenance
Recommended Spare Parts List
Chapter 6 Spare Parts
General Information
Specifications
Operation
Indicator Panel
Memory Read Cycle
Maintenance
Engineering Drawings
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