User Manuals: Digital Equipment PDP-11/44 minicomputer

Manuals and User Guides for Digital Equipment PDP-11/44 minicomputer. We have 1 Digital Equipment PDP-11/44 minicomputer manual available for free PDF download: Handbook

Digital Equipment PDP-11/44 Handbook

Digital Equipment PDP-11/44 Handbook (244 pages)

UNIBUS Processor

Brand: Digital Equipment | Category: Computer Hardware | Size: 15 MB

Table of Contents

Table of Contents
4
Preface
8
Chapter 1 • Introduction

10
- PDP-Ll/84 System
  12
- Software
  15
- Networks
  17
- Peripherals
  17
- Service
  18
- Documentation
  18
Chapter 2 • PDP

19
- Introduction
  19
- Features
  21
- System Architecture
  22
- Central Processor
  23
  - General Registers
    25
  - Processor Status Word
    26
  - Program Interrupt Request Register
    29
  - Pipeline Processing
    30
  - CPU Error Register
    31
  - Stack Limit Protection
    32
  - Kernel Protection
    33
  - Trap and Interrupt Priorities
    34
  - Hardware Detected Errors
    35
- Private Memory Interconnect
  36
- Memory System
  37
  - Memory Management
    37
  - Error Correction Code
    38
  - Battery Backup Unit
    38
  - UNIBUS Adapter (UBA)
    39
  - Dmacache
    39
  - UNIBUS Mapping
    40
  - Boot ROM Facility
    40
  - Cache Memory
    41
  - Cache Registers
    43
- Console Functions
  48
  - Console Serial Line Unit Registers
    48
- Line-Time Clock
  52
  - Clock Status Register
    52
- Console
  53
  - Setup Mode
    54
  - Program Mode
    55
  - Console ODT Mode
    56
- Specifications
  57
Chapter 3' PDP

57
- System Architecture
  61
- Central Processor
  61
  - General Registers
    63
  - Processor Status Word
    64
- CPU Registers
  66
- Memory Systems
  72
  - Memory Management
    72
  - UNIBUS Map
    72
- Cache Memory
  72
  - General System Architecture
    72
  - CPU Bypass of the Cache
    73
  - Cache Memory Organization
    74
  - Cache-Control Registers
    74
- Floating-Point Processor
  80
- Backplane Configuration
  80
- Serial Line Unit Registers
  80
- Line Clock
  88
  - Line Clock Status Register
    88
- Address and Vector Assignment
  89
- Specifications
  90
Chapter 4 ·PDP

92
- System Architecture
  93
- Central Processor
  93
- Registers
  95
  - Processor Status Word
    96
  - CPU Error Register
    98
  - Processor Traps
    99
  - CPU and I/O Device Registers and Addresses
    100
- Memory System
  101
  - Memory Management
    101
- Console
  102
  - Console ODT Mode
    102
- Address Specification
  105
- Processor I/O Addresses
  105
  - Stack Pointer Selection
    105
  - Entering Octal Digits
    106
  - Terminal Serial Line Unit Control Registers
    107
  - Second Serial Line Unit Registers
    110
- Line Clock
  113
  - Clock Status Register
    113
- Address and Vector Assignments
  114
- Specifications
  114
Chapter 5 • UNIBUS Technical Description

119
- Characteristics of the UNIBUS
  119
  - Nonmultiplexed Bus
    119
  - Strict Master/Slave Relationship
    119
  - Partially Distributed Arbitration
    120
  - Overlapped Arbitration and Data Transfer
    122
  - Asynchronous Operation
    122
  - Address Bits
    124
  - Word or Byte Operations
    124
  - Parity Error Information from Slaves
    124
- UNIBUS Block Diagram
  125
- UNIBUS Data and Address Organization
  126
- Types of UNIBUS Data Transfers
  127
  - Read Word
    128
  - Write Word
    128
  - Write Byte
    128
  - Read Word with Write Intent
    130
  - Write Vector
    131
- UNIBUS Signal Details
  131
  - Initialization and Shutdown Signals
    132
  - Powerup Timing
    135
  - Powerdown Timing
    136
  - Initialization Timing
    137
  - Arbitration Signals
    138
  - UNIBUS Arbitration Timing
    139
  - Abnormal Cycles
    140
  - Data Transfer Signals
    142
  - DATI Timing
    144
  - Datip
    146
  - Write Vector Timing
    147
  - Abnormal Bus Cycles
    149
  - Multiple Bus Cycles
    149
  - Miscellaneous Signals
    150
- UNIBUS Electrical Characteristics
  151
- Design Suggestions
  154
  - Watch the DC Voltage Levels
    154
  - Maintain 120-Ohm Impedance and Watch Ac Signals
    155
  - Minimize Crosstalk
    156
  - Consider All Timing Cases
    156
  - Be a Good Bus Citizen
    157
Appendix A • PDP-Ll Family Differences Table

159
Appendix B· Console Commands

200
Appendix C • Instruction Times

200
Index

200

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