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Philips NXP NXP Product Data Sheet

Philips NXP NXP Product Data Sheet

Transmission modules
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1. Introduction

This Product data sheet document describes the functionality of the transceiver IC
PN512. It includes functional and electrical specifications.

2. General description

The PN512 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
The PN512 transceiver ICs support 4 different operating modes
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512's internal
transmitter part is able to drive a reader/writer antenna designed to communicate with
ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The
receiver part provides a robust and efficient implementation of a demodulation and
decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and
transponders. The digital part handles the complete ISO/IEC 14443A framing and error
detection (Parity & CRC).
The PN512 supports MIFARE 1 KB or MIFARE 4 KB emulation products. The PN512
supports contactless communication using MIFARE higher transfer speeds up to
424 kbit/s in both directions.
Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN512 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication
scheme, given correct implementation of additional components, like oscillator, power
supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4
and/or ISO/IEC 14443B anticollision are correctly implemented.
PN512
Transmission Module
Rev. 3.4 — 8 September 2009
111334
•
Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
•
Reader/Writer mode supporting ISO/IEC 14443B
•
Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
•
NFCIP-1 mode
Product data sheet
PUBLIC

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  • Page 1: Introduction

    PN512 Transmission Module Rev. 3.4 — 8 September 2009 Product data sheet 111334 PUBLIC 1. Introduction This Product data sheet document describes the functionality of the transceiver IC PN512. It includes functional and electrical specifications. 2. General description The PN512 is a highly integrated transceiver IC for contactless communication at 13.56 MHz.
  • Page 2 PN512 NXP Semiconductors Transmission Module PUBLIC In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer.

  • Page 3: Features

    PN512 NXP Semiconductors Transmission Module PUBLIC 3. Features Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers to connect an antenna with minimum number of external components Integrated RF Level detector Integrated data mode detector ISO/IEC 14443A/MIFARE support ISO/IEC 14443B reader/writer functionality Typical operating distance in Reader/Writer mode for communication to a ISO/IEC 14443A/ MIFARE or FeliCa card up to 50 mm depending on the antenna size,...

  • Page 4: Quick Reference Data

    PN512 NXP Semiconductors Transmission Module PUBLIC 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Unit [1][2] Supply Voltage = DV = PV = TV = 0 V, ≤ AV [1][2] = DV [1][2] Pad power supply = DV = PV = TV...

  • Page 5: Fig 1. Simplified Pn512 Block Diagram

    PN512 NXP Semiconductors Transmission Module PUBLIC 6. Block diagram The Analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin.

  • Page 6: Fig 2. Pn512 Block Diagram

    PN512 NXP Semiconductors Transmission Module PUBLIC NWR NRD A0 to A5 D0 to D7 PVSS PVDD DVDD Voltage 8 bit Parallel, SPI, UART, I2C Interface Control DVSS Monitor (incl. Automatic Interface Detection & Synchronisation) & Power On AVDD Detect AVSS FIFO Control State Machine Reset...

  • Page 7: Fig 3. Pinning Configuration Hvqfn32 (Sot617-1)

    PN512 NXP Semiconductors Transmission Module PUBLIC 7. Pinning information 7.1 Pinning terminal 1 index area PVDD DVDD OSCOUT DVSS OSCIN PN512 PVSS AUX2 NRSTPD AUX1 SIGIN AVSS SIGOUT SOT617-1 Transparent top view Fig 3. Pinning configuration HVQFN32 (SOT617-1) terminal 1 index area PVDD PN512...

  • Page 8: Pin Description

    PN512 NXP Semiconductors Transmission Module PUBLIC 7.2 Pin description Table 3. Pin description HVQFN32 Symbol Type Description Address Line PVDD Pad power supply DVDD Digital Power Supply DVSS Digital Ground PVSS Pad power supply ground NRSTPD Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world.
  • Page 9 PN512 NXP Semiconductors Transmission Module PUBLIC Table 4. Pin description HVQFN40 Symbol Type Description A2 to A5 1 to 4 Address Line PVDD Pad power supply DVDD Digital Power Supply DVSS Digital Ground PVSS Pad power supply ground NRSTPD Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world.

  • Page 10: Pn512 Register Set

    PN512 NXP Semiconductors Transmission Module PUBLIC 8. PN512 register SET 8.1 PN512 registers overview Table 5. PN512 registers overview Addr Register Name Function (hex) Page 0: Command and Status PageReg Selects the register page CommandReg Starts and stops command execution ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests DivlEnReg...
  • Page 11 PN512 NXP Semiconductors Transmission Module PUBLIC Table 5. PN512 registers overview …continued Addr Register Name Function (hex) PageReg Selects the register page CRCResultReg Shows the actual MSB and LSB values of the CRC calculation GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when the driver is switched off ModWidthReg Controls the setting of the ModWidth...

  • Page 12: Register Bit Behavior

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.1.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In Table 6 access conditions are described. Table 6.

  • Page 13: Register Description

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2 Register description 8.2.1 Page 0: Command and status 8.2.1.1 PageReg Selects the register page. Table 7. PageReg register (address 00h); reset value: 00h, 0000000b UsePage Select PageSelect Access Rights Table 8. Description of PageReg bits Symbol Description UsePageSelect...

  • Page 14: Commienreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 11. CommIEnReg register (address 02h); reset value: 80h, 10000000b IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Access Rights Table 12. Description of CommIEnReg bits Symbol Description...

  • Page 15: Divienreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 13. DivIEnReg register (address 03h); reset value: 00h, 00000000b IRQPushPull SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn Access Rights Table 14. Description of DivIEnReg bits Symbol Description IRQPushPull...

  • Page 16: Commirqreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 15. CommIRqReg register (address 04h); reset value: 14h, 00010100b Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq Access Rights Table 16. Description of CommIRqReg bits All bits in the register CommIRqReg shall be cleared by software. Symbol Description Set1...

  • Page 17: Divirqreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.6 DivIRqReg Contains Interrupt Request bits Table 17. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb Set2 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq Access Rights Table 18. Description of DivIRqReg bits All bits in the register DivIRqReg shall be cleared by software. Symbol Description Set2...

  • Page 18: Errorreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. Table 19. ErrorReg register (address 06h); reset value: 00h, 00000000b WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr Access Rights Table 20.

  • Page 19: Status1Reg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 21. Status1Reg register (address 07h); reset value: XXh, X100X01Xb RFFreqOK CRCOk CRCReady TRunning RFOn HiAlert LoAlert Access Rights Table 22. Description of Status1Reg bits Symbol Description RFFreqOK...

  • Page 20: Status2Reg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 23. Status2Reg register (address 08h); reset value: 00h, 00000000b TempSensClear I CForceHS TargetActivated MFCrypto1On Modem State Access Rights Table 24. Description of Status2Reg bits Symbol Description...

  • Page 21: Fifodatareg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. Table 25. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb FIFOData Access Rights Table 26. Description of FIFODataReg bits Symbol Description 7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer.

  • Page 22: Waterlevelreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. Table 29. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b WaterLevel Access Rights Table 30. Description of WaterLevelReg bits Symbol Description 7 to 6 Reserved for future use.

  • Page 23: Bitframingreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 33. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b StartSend RxAlign TxLastBits Access Rights Table 34. Description of BitFramingReg bits Symbol Description StartSend Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command.

  • Page 24: Collreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 35. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb Values CollPos CollPos AfterColl NotValid Access Rights Table 36. Description of CollReg bits Symbol Description ValuesAfterColl...

  • Page 25: Communication

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2 Page 1: Communication 8.2.2.1 PageReg Selects the register page. Table 37. PageReg register (address 10h); reset value: 00h, 00000000b UsePage Select PageSelect Access Rights Table 38. Description of PageReg bits Symbol Description UsePage Select Set to logic 1, the value of PageSelect is used as register address A5 and A4.

  • Page 26: Modereg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 39. ModeReg register (address 11h); reset value: 3Bh, 00111011b MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset Access Rights Table 40. Description of ModeReg bits Symbol Description MSBFirst...

  • Page 27: Txmodereg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 41. TxModeReg register (address 12h); reset value: 00h, 00000000b TxCRCEn TxSpeed InvMod TxMix TxFraming Access Rights Table 42. Description of TxModeReg bits Symbol Description TxCRCEn Set to logic 1, this bit enables the CRC generation during data...

  • Page 28: Rxmodereg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 43. RxModeReg register (address 13h); reset value: 00h, 00000000b RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming Access Rights Table 44. Description of RxModeReg bits Symbol Description RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.

  • Page 29: Txcontrolreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. Table 45. TxControlReg register (address 14h); reset value: 80h, 10000000b InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW CheckRF Tx2RF Tx1RF Access Rights Table 46.

  • Page 30: Txautoreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 47. TxAutoReg register (address 15h); reset value: 00h, 00000000b AutoRF Force100 Auto CAOn InitialRF Tx2RFAut Tx1RFAuto WakeUp Access Rights Table 48. Description of TxAutoReg bits Symbol Description AutoRFOFF...

  • Page 31: Txselreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.7 TxSelReg Selects the sources for the analog part. Table 49. TxSelReg register (address 16h); reset value: 10h, 00010000b DriverSel SigOutSel Access Rights Table 50. Description of TxSelReg bits Symbol Description 7 to 6 Reserved for future use.
  • Page 32 PN512 NXP Semiconductors Transmission Module PUBLIC Table 50. Description of TxSelReg bits …continued Symbol Description 3 to 0 SigOutSel Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg.

  • Page 33: Rxselreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.8 RxSelReg Selects internal receiver settings. Table 51. RxSelReg register (address 17h); reset value: 84h, 10000100b UartSel RxWait Access Rights Table 52. Description of RxSelReg bits Symbol Description 7 to 6 UartSel Selects the input of the contactless UART Value Description Constant Low...

  • Page 34: Demodreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.10 DemodReg Defines demodulator settings. Table 55. DemodReg register (address 19h); reset value: 4Dh, 01001101b AddIQ FixIQ TauRcv TauSync Access Rights Table 56. Description of DemodReg bits Symbol Description 7 to 6 AddIQ Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings.

  • Page 35: Felnfc1Reg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 57. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b FelSyncLen DataLenMin Access Rights Table 58. Description of FelNFC1Reg bits Symbol Description...

  • Page 36: Felnfc2Reg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 59. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b WaitForSelected ShortTimeSlot DataLenMax Access Rights Table 60. Description of FelNFC2Reg bits Symbol Description WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1.

  • Page 37: Mifnfcreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 61. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b SensMiller TauMiller MFHalted TxWait Access Rights Table 62. Description of MifNFCReg bits Symbol Description 7 to 5...

  • Page 38: Manualrcvreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 63. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b FastFilt Delay Parity LargeBW...

  • Page 39: Typebreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.2.15 TypeBReg Table 65. TypeBReg register (address 1Eh); reset value: 00h, 00000000b RxSOF RxEOF EOFSO NoTxSOF NoTxEOF TxEGT FWidth Access Rights Table 66. Description of TypeBReg bits Symbol Description RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting without SOF is ignored.

  • Page 40: Configuration

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3 Page 2: Configuration 8.2.3.1 PageReg Selects the register page. Table 69. PageReg register (address 20h); reset value: 00h, 00000000b UsePageSelect PageSelect Access Rights Table 70. Description of PageReg bits Symbol Description UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4.

  • Page 41: Gsnoffreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.3 GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 75. GsNOffReg register (address 23h); reset value: 88h, 10001000b CWGsNOff ModGsNOff Access Rights Table 76.

  • Page 42: Modwidthreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.4 ModWidthReg Controls the modulation width settings. Table 77. ModWidthReg register (address 24h); reset value: 26h, 00100110b ModWidth Access Rights Table 78. Description of ModWidthReg bits Symbol Description 7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active and Passive Communication mode as multiples of the carrier frequency (ModWidth +1/fc).

  • Page 43: Rfcfgreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 81. RFCfgReg register (address 26h); reset value: 48h, 01001000b RFLevelAmp RxGain RFLevel Access Rights Table 82. Description of RFCfgReg bits Symbol Description RFLevelAmp Set to logic 1, this bit activates the RF level detectors’...

  • Page 44: Gsnonreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Table 83. GsNOnReg register (address 27h); reset value: 88h, 10001000b CWGsNOn ModGsNOn Access Rights Table 84.

  • Page 45: Modgspreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. Table 87. ModGsPReg register (address 29h); reset value: 20h, 00100000b ModGsP Access Rights Table 88. Description of ModGsPReg bits Symbol Description 7 to 6 Reserved for future use. 5 to 0 ModGsP The value of this register defines the conductance of the output...
  • Page 46 PN512 NXP Semiconductors Transmission Module PUBLIC Table 90. Description of TModeReg bits …continued Symbol Description 6 to 5 TGated The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits.

  • Page 47: Treloadreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 93. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b TReloadVal_Hi Access Rights Table 94.

  • Page 48: Tcountervalreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. Table 97. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb TCounterVal_Hi Access Rights Table 98.
  • Page 49 PN512 NXP Semiconductors Transmission Module PUBLIC Table 102. Description of PageReg bits Symbol Description UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively.

  • Page 50: Testsel1Reg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.4.2 TestSel1Reg General test signal configuration. Table 103. TestSel1Reg register (address 31h); reset value: 00h, 00000000b SAMClockSel SAMClkD1 TstBusBitSel Access Rights Table 104. Description of TestSel1Reg bits Symbol Description 7 to 6 Reserved for future use. 5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock...

  • Page 51: Testpinenreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. Table 107. TestPinEnReg register (address 33h); reset value: 80h, 10000000b RS232LineEn TestPinEn Access Rights Table 108. Description of TestPinEnReg bits Symbol Description RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are disabled.

  • Page 52: Testbusreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.4.6 TestBusReg Shows the status of the internal testbus. Table 111. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb TestBus Access Rights Table 112. Description of TestBusReg bits Symbol Description 7 to 0 TestBus Shows the status of the internal testbus.

  • Page 53: Analogtestreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 117. AnalogTestReg register (address 38h); reset value: 00h, 00000000b AnalogSelAux1 AnalogSelAux2 Access Rights Table 118. Description of AnalogTestReg bits Symbol Description 7 to 4 AnalogSelAux1 Controls the AUX pin.

  • Page 54: Testdac1Reg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. Table 119. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb TestDAC1 Access Rights Table 120. Description of TestDAC1Reg bits Symbol Description Reserved for production tests. Reserved for future use. 5 to 0 TestDAC1 Defines the testvalue for TestDAC1.

  • Page 55: Rftreg

    PN512 NXP Semiconductors Transmission Module PUBLIC 8.2.4.13 RFTReg Table 125. RFTReg register (address 3Ch); reset value: FFh, 11111111b Access Rights Table 126. Description of RFTReg bits Symbol Description 7 to 0 Reserved for production tests. Table 127. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b Access Rights Table 128.

  • Page 56: Fig 5. Reader/Writer Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 9. Operating modes PN512 transceiver IC supports the following operating modes: • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail.

  • Page 57: Iso/Iec 14443A

    PN512 NXP Semiconductors Transmission Module PUBLIC Table 131. Communication overview for ISO/IEC 14443A/MIFARE reader/writer Communication ISO/IEC 14443A/ MIFARE Higher transfer speeds direction MIFARE transfer speed 106 kbit/s 212 kbit/s 424 kbit/s PN512 → PICC Modulation on 100% ASK 100% ASK 100% ASK (send data from reader side...

  • Page 58: Fig 8. Felica Reader/Writer Communication Diagram

    PN512 NXP Semiconductors Transmission Module PUBLIC 9.1.2 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. 1.

  • Page 59: Fig 9. Nfcip-1 Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 9.1.3 ISO/IEC 14443B reader/writer functionality The international standard ISO/IEC 14443 covers 2 communication schemes: the ISO/IEC 14443A and the ISO/IEC 14443B. The PN512 reader IC fully supports the ISO/IEC 14443. The following registers and bits cover the ISO/IEC 14443B communication scheme: As a reference documentation the international standard ISO/IEC 14443 'Identification cards- Contactless integrated circuit(s) cards- Proximity cards, part 1-4' can be taken.

  • Page 60: Fig 10. Active Communication Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 9.2.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. Initial Command Host Host NFC Target NFC Initiator 1. Initiator starts communication at selected transfer speed powered for digital processing...

  • Page 61: Fig 11. Passive Communication Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 9.2.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. Fig 11. Passive communication mode Table 136.

  • Page 62: Fig 12. Card Operation Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 9.2.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. Table 137. Framing and coding overview Transfer speed Framing and Coding 106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme...

  • Page 63: Mifare Card Operation Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 9.3.1 MIFARE Card operation mode Table 138. MIFARE Card operation mode Communication ISO/IEC 14443A/ MIFARE Higher transfer speeds direction MIFARE transfer speed 106 kbit/s 212 kbit/s 424 kbit/s reader / writer → Modulation on 100% ASK 100% ASK 100% ASK...

  • Page 64: Digital Interfaces

    PN512 NXP Semiconductors Transmission Module PUBLIC 10. Digital interfaces 10.1 Automatic host controller interface type detection The PN512 supports direct interfacing of various host controllers as the 8-bit parallel, SPI, C and serial UART interface type. The PN512 resets its interface and checks the current host controller interface type automatically having performed a Power-On or Hard Reset.

  • Page 65: Fig 13. Connection To Host Controller With Spi

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.2.1 General An interface compatible to an SPI interface enables a high-speed serial communication between the PN512 and a μ-Controller up to 5 Mbit in order to handle the requirements for the NFCIP-1 communication. The implemented SPI compatible interface is according to a standard SPI interface.

  • Page 66: Fig 14. Connection To Host Controller With Uart

    PN512 NXP Semiconductors Transmission Module PUBLIC Write data: To write data to the PN512 using the SPI interface the following byte order has to be used. It is possible to write out up to n-data bytes by only sending one’s address byte. The first send byte defines both, the mode itself and the address byte.

  • Page 67: Selection Of The Transfer Speeds

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.3.2 Selection of the transfer speeds The internal UART interface is compatible to an RS232 serial interface. Table 144 “Selectable transfer speeds” describes examples for different transfer speeds and relevant register settings. The resulting transfer speed error is less than 1.5% for all described transfer speeds. The default transfer speed is 9.6 kbit.

  • Page 68: Fig 15. Schematic Diagram To Read Data

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.3.3 Framing Table 145. UART Framing Length Value Start bit 1-bit Data bits 8 bits Data Stop bit 1-bit For data and address bytes the LSB bit has to be sent first. Note: No parity bit is used during transmission. Read data: To read out data using the UART interface the flow described below has to be used.

  • Page 69: Fig 16. Schematic Diagram To Write Data

    PN512 NXP Semiconductors Transmission Module PUBLIC Table 147. Byte order to write data byte 0 byte 1 adr 0 data 0 adr 0 Fig 16. Schematic Diagram to Write Data Remark: The data byte can be send directly after the address byte on RX. Address byte: The address byte has to fulfill the following format.

  • Page 70: Fig 17. I C Interface

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4 I C bus interface An Inter IC (I C) bus interface is supported to enable a low cost, low pin count serial bus interface to the host controller. The implemented I C interface is implemented according the NXP Semiconductors I interface specification, rev.

  • Page 71: Fig 18. Bit Transfer On The I 2 C-Bus

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4.2 Data validity Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH or LOW state of the data line shall only change when the clock signal on SCL is LOW. Fig 18.

  • Page 72: Fig 20. Acknowledge On The I 2 C- Bus

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4.4 Byte format Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure 22. The number of transmitted bytes during one data transfer is unrestricted but shall fulfill the read/write cycle format. 10.4.5 Acknowledge An acknowledge at the end of one data byte is mandatory.

  • Page 73: Fig 22. First Byte Following The Start Procedure

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4.6 7-bit addressing During the I C-bus addressing procedure the first byte after the START condition is used to determine which slave will be selected by the master. During device configuration, the designer has to ensure, that no collision with these reserved addresses is possible.

  • Page 74: Fig 23. Register Read And Write Access

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4.8 Register read access To read out data from a specific register address of the PN512 the host controller shall use the procedure: First a write access to the specific register address has to be performed as indicated in the following frame.

  • Page 75: Fig 24. I 2 C Hs Mode Protocol Switch

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4.9 HS mode In High-speed mode (HS mode) the device can transfer information at data rates of up to 3.4 Mbit, it remains fully downward compatible with Fast- or Standard mode (F/S mode) for bi-directional communication in a mixed-speed bus system. 10.4.10 High speed transfer To achieve a data rates of up to 3.4 Mbit the following improvements have been made to the regular I...

  • Page 76: Fig 25. I 2 C Hs Mode Protocol Frame

    PN512 NXP Semiconductors Transmission Module PUBLIC Fig 25. I C HS mode protocol frame 10.4.12 Switching from F/S to HS mode and Vice Versa After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward compatible to Standard mode).

  • Page 77: Fig 26. Connection To Host Controller With Separated Read/Write Strobes

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.4.13 PN512 at lower speed modes PN512 is fully downwards compatible, and can be connected to an F/S mode I C-bus system. As no master code will be transmitted in such a configuration, the device stays in F/S mode and communicates at F/S mode speeds.

  • Page 78: Fig 27. Connection To Host Controller With Common Read/Write Strobes

    PN512 NXP Semiconductors Transmission Module PUBLIC 10.5.3 Common Read/Write strobe PN512 PN512 Non Multiplexed Address Decoder Address Address Address Bus Decoder A0...A3[A5*] Address Bus (A0...A3[A5*]) HIGH HIGH Data Bus (D0...D7) D0...D7 Multiplexed Address/Data D0...D7 (AD0...AD7) HIGH Adress Strobe (AS) Not Data Strobe (NDS) Not Data Strobe (NDS) Read Not Write (RD/NWR) Read Not Write (RD/NWR)

  • Page 79: Analog Interface And Contactless Uart

    PN512 NXP Semiconductors Transmission Module PUBLIC 11. AnaLog interface and contactless UART 11.1 General The PN512 supports different Contactless Communication modes. The integrated contactless UART supports the external μ-Controller online with framing and error checking of the protocol requirements for the different selected communication schemes as Card Operation mode, Reader/Writer Operating mode or NFIP-1 mode up to 424 kbit.
  • Page 80 PN512 NXP Semiconductors Transmission Module PUBLIC Table 150. Settings for TX1 TX1RFEn Force InvTx1 InvTx1 Envelope GSPMos GSNMos Remarks 100ASK RFON RFOFF nModOff If TX1RFEN=0, the pin TX1 is set to logic 0 or 1 nCWOff depending on InvTx1. pMod The bit Force 100ASK has no effect, envelope modulates GS values...

  • Page 81: Rf Level Detector

    PN512 NXP Semiconductors Transmission Module PUBLIC The following abbreviations are used: • RF: 13.56 MHz clock derived from 27.12 MHz quartz divided by 2 • RF_n: inverted 13.56 MHz clock • gspmos: Conductance, configuration of the PMOS array • gspmos: Conductance, configuration of the NMOS array •...

  • Page 82: Fig 28. Data Mode Detector

    PN512 NXP Semiconductors Transmission Module PUBLIC To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp in register RFCfgReg to 1. Remark: During soft Power-down mode the RF level detector amplifier is automatically switched off to ensure that the power consumption is less than 10 μA at 3 V.

  • Page 83: Fig 29. Serial Data Switch For Tx1 And Tx2

    PN512 NXP Semiconductors Transmission Module PUBLIC 11.5 Serial data switch Two main blocks are implemented in the PN512. A digital circuitry, comprising state machines, coder and decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT.

  • Page 84: Fig 30. Communication Flows Using The S

    PN512 NXP Semiconductors Transmission Module PUBLIC Host contoller 1.Secure Access PN512 Module (SAM) mode SPI, I2C, Serial UART FIFO and State Maschine SIGOUT Secure Core IC Serial signal switch SIGIN Contactless Uart 2. Contactless card mode Fig 30. Communication flows using the S C interface Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT.

  • Page 85: Fig 32. Signal Shape For Sigin In Sam Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 11.6.1 Signal shape for Felica S C interface support The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal.

  • Page 86: Signal Shape For Sigout In Mifare Card Sam Mode

    PN512 NXP Semiconductors Transmission Module PUBLIC 11.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S C support The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode.

  • Page 87: Hardware Support For Felica And Nfc Polling

    PN512 NXP Semiconductors Transmission Module PUBLIC 11.7 Hardware support for FeliCa and NFC polling 11.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot, or if required an interrupt is generated at the end of the last timeslot.

  • Page 88: Additional Hardware Support For Felica And Nfc

    PN512 NXP Semiconductors Transmission Module PUBLIC 11.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length.

  • Page 89: Fifo-Buffer

    PN512 NXP Semiconductors Transmission Module PUBLIC 12. FIFO-buffer 12.1 Overview An 64*8-bit FIFO-buffer is implemented in the PN512. It buffers the input and output data stream between the host controller and the internal state machine of the PN512. Thus, it is possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account.

  • Page 90: Status Information About The Fifo-Buffer

    PN512 NXP Semiconductors Transmission Module PUBLIC 12.4 Status information about the FIFO-buffer The host controller may obtain the following data about the FIFO-buffers status: • Number of bytes already stored in the FIFO-buffer: FIFOLevel in register FIFOLevelReg • Warning, that the FIFO-buffer is almost full: HiAlert in register Status1Reg •...

  • Page 91: Timer Unit

    PN512 NXP Semiconductors Transmission Module PUBLIC 13. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: •...

  • Page 92: Interrupt Request System

    PN512 NXP Semiconductors Transmission Module PUBLIC 14. Interrupt request system 14.1 Overview The PN512 indicates certain events by setting bit IRq in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host controller using its interrupt handling capabilities.
  • Page 93 PN512 NXP Semiconductors Transmission Module PUBLIC Table 153. Interrupt sources Interrupt bit Interrupt source Is set automatically, when TimerIRq Timer Unit the timer counts from 1 to 0 TxIRq Transmitter a transmitted data stream ends CRCIRq CRC co-processor all data from the FIFO-buffer has been processed RxIRq Receiver a received data stream ends...

  • Page 94: Fig 35. Quartz Connection

    PN512 NXP Semiconductors Transmission Module PUBLIC 15. Oscillator circuitry The clock applied to the PN512 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible.

  • Page 95: Power Reduction Modes

    PN512 NXP Semiconductors Transmission Module PUBLIC 16. Power reduction modes 16.1 Hard Power-down A Hard Power-down is enabled with LOW level on pin NRSTPD. This turns off all internal current sinks as well as the oscillator. All digital input buffers are separated from the input pads and clamped internally (except pin NRSTPD itself).

  • Page 96: Fig 36. Oscillator Start Up Time

    PN512 NXP Semiconductors Transmission Module PUBLIC 17. Reset and Oscillator start up time 17.1 Reset timing requirements The reset signal is filtered by a hysteresis circuit and a spike filter (rejects signals shorter than 10 ns) before it enters the digital circuit. In order to perform a reset, the signal has to be low for at least 100 ns.

  • Page 97: Pn512 Command Set

    PN512 NXP Semiconductors Transmission Module PUBLIC 18. PN512 Command set 18.1 General description The PN512 behavior is determined by a state machine capable to perform a certain set of commands. By writing the according command to the Command-Register the command is executed.

  • Page 98: Pn512 Command Description

    PN512 NXP Semiconductors Transmission Module PUBLIC 18.3.1 PN512 Command description 18.3.1.1 Idle command The PN512 is in Idle mode. This command is also used to terminate the actual command. 18.3.1.2 Config command To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for these transactions has to be stored internally.

  • Page 99: Calccrc Command

    PN512 NXP Semiconductors Transmission Module PUBLIC 18.3.1.4 CalcCRC command The content of the FIFO is transferred to the CRC co-processor and a CRC calculation is started. The result of this calculation is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped, when the FIFO gets empty during the data stream.

  • Page 100: Transceive Command

    PN512 NXP Semiconductors Transmission Module PUBLIC 18.3.1.8 Transceive command This circular command repeats transmitting data from the FIFO and receiving data from the RF field continuously. If the bit Initiator in the register ControlReg is set to logic 1, it indicates that the first action is transmitting and after having finished transmission the receiver is activated to receive data.

  • Page 101: Fig 37. Autocoll Command

    PN512 NXP Semiconductors Transmission Module PUBLIC MODE Dedection RXFraming NFCIP-1 106kBaud NFCIP-1 >106kBaud ISO14443-3 FELICA MFHalted=1 REQA HALT IDLE MODE0 SELECT Polling, SELECT REQA, REQA, nSELECT Polling Response nSELECT WUPA, WUPA, HLTA HLTA nAC, nAC, REQA, REQA, WUPA REQA, WUPA nSELECT, nSELECT, WUPA,...

  • Page 102: Mfauthent Command

    PN512 NXP Semiconductors Transmission Module PUBLIC FeliCa (Card Operation mode): The FeliCa polling command is finished and the command has automatically changed to transceive. The FIFO contains the first command followed after the Polling by the FeliCa protocol.The bit TargetActivated in the Status2Reg register is set to logic 1. 18.3.1.10 MFAuthent command This command handles the MIFARE authentication in Reader/Writer mode to enable a secure communication to any MIFARE card.

  • Page 103: Testsignals

    PN512 NXP Semiconductors Transmission Module PUBLIC 19. Testsignals 19.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3.
  • Page 104 PN512 NXP Semiconductors Transmission Module PUBLIC Table 157. Testsignal routing (TestSel2Reg = 0Dh) Pins Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf Table 158. Description of Testsignals Pins Testsignal Description clkstable shows if the oscillator delivers a stable signal. clk27/8 shows the output signal of the oscillator divided by 8 clk27rf/8 shows the clk27rf signal divided by 8...

  • Page 105: Testsignals At Pin Aux

    PN512 NXP Semiconductors Transmission Module PUBLIC 19.3 Testsignals at pin AUX Table 161. Testsignals description SelAux Description for Aux1 / Aux2 0000 Tristate 0001 DAC: register TestDAC 1/2 0010 DAC: testsignal corr1 0011 DAC: testsignal corr2 0100 DAC: testsignal MinLevel 0101 DAC: ADC_I 0110...

  • Page 106: Fig 38. Typical Circuit Diagram

    PN512 NXP Semiconductors Transmission Module PUBLIC 20. Application design-in information The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN512. The antenna tuning and RF part matching is described in the application note “NFC Transmission Module Antenna and RF Design Guide”.

  • Page 107: Limiting Values

    PN512 NXP Semiconductors Transmission Module PUBLIC 21. Limiting values Table 162. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Unit Supply voltage -0.5 +4.0 Input voltage for all input-pins except -0.5 PV +0.5 V in, abs SigIn and Rx for SigIn...

  • Page 108: Characteristics

    PN512 NXP Semiconductors Transmission Module PUBLIC 24. Characteristics 24.1 Input pin characteristics 24.1.1 Input pin characteristics for pins A0, A1, A2, A3, A4, A5, NCS, NWR, NRD and NRESET Table 165. Input pin characteristics for pins A0, A1, A2, A3, A4, A5, NCS, NWR, NRD, SIGIN and NRESET Symbol Parameter Conditions...

  • Page 109: Output Pin Characteristics For Pin Sigout

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.1.5 Output pin characteristics for pin SIGOUT Table 169. Output pin characteristics for Pin SIGOUT Symbol Parameter Conditions Unit Output voltage HIGH = 3 V, I = 4 mA -400 mV - Output voltage LOW = 3 V, I = 4 mA +400 mV V...

  • Page 110: Output Pin Characteristics For Pins Tx1 And Tx2

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.1.9 Output pin characteristics for pins AUX1 and AUX2 Table 173. Input/Output pin characteristics for pins AUX1 and AUX2 Symbol Parameter Conditions Unit Output voltage HIGH = 3 V, I = 4 mA -400 mV - Output voltage LOW = 3 V, I = 4 mA...

  • Page 111: Current Consumption

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.2 Current consumption Table 175. Current consumption Symbol Parameter Conditions Unit μA Hard Power-down Current AV = DV = TV = PV = 3 V, = LOW RESET μA Soft Power-down Current = DV = TV = PV = 3 V,...

  • Page 112: Fig 39. Rx Input Voltage Range

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.4 RX input sensitivity Table 177. RX input sensitivity Symbol Parameter Conditions Unit Minimum Modulation index, Miller coded AV = 3 V, 106 kbit RX,Mill = 1.5 V , SensMiller = 3 Minimum modulation voltage = 3 V, RxGain = 7 RXMod,Man The minimum modulation voltage is valid for all modulation schemes except Miller coded signals.

  • Page 113: Clock Frequency

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.5 Clock frequency Table 178. Clock frequency Symbol Parameter Conditions Unit Clock Frequency 27.12 OSCIN Duty Cycle of Clock Frequency Jitter of Clock Edges ps, RMS jitter 24.6 XTAL oscillator Table 179. XTAL oscillator Symbol Parameter Conditions...

  • Page 114: Fig 40. Timing Diagram For Spi

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.8 Timing for the SPI compatible interface Table 181. Timing specification for SPI Symbol Parameter Conditions Unit NSS high before communication NHNL SCK low pulse width SCKL SCK high pulse width SCKH SCK high to data changes SHDX data changes to SCK high DXSH...

  • Page 115: I 2 C Timing

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.9 I C timing Table 182. Overview I C timing in fast mode Symbol Parameter Fast mode High speed mode Unit SCL clock frequency 3400 Hold time (repeated) START condition. After this HD;STA period, the first clock pulse is generated Set-up time for a repeated START condition SU;STA Set-up time for STOP condition...

  • Page 116: 8-Bit Parallel Interface Timing

    PN512 NXP Semiconductors Transmission Module PUBLIC 24.10 8-bit parallel interface timing 24.10.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Table 183.

  • Page 117: Bus Timing For Common Read/Write Strobe

    PN512 NXP Semiconductors Transmission Module PUBLIC LHLL CLWL WHCH LLWL WHWL WLWH WHWL WLDV WHDX AVLL LLAX RLDV RHDZ Multiplexed Addressbus D0 ... D7 D0 ... D7 A0 ... A3 AVWL WHAX Separated Addressbus A0 ... A3 A0 ... A3 Fig 42.
  • Page 118 PN512 NXP Semiconductors Transmission Module PUBLIC LHLL CLSL SHCH RVSL SHRX R/NW LLSL SHSL SLSH SHSL SLDV,R SHDX AVLL LLAX SLDV,W SHDZ D0 ... D7 Multiplexed Addressbus D0 ... D7 A0 ... A3 AVSL SHAX Separated Addressbus A0 ... A3 A0 ...

  • Page 119: Package Information

    PN512 NXP Semiconductors Transmission Module PUBLIC 25. Package information The PN512 can be delivered in 2 different packages. Table 186. Package information Package Remarks HVQFN32 8-bit parallel interface not supported HVQFN40 Supports the 8-bit parallel interface 111334 © NXP B.V. 2010. All rights reserved. Product data sheet Rev.

  • Page 120: Package Outline

    PN512 NXP Semiconductors Transmission Module PUBLIC 26. Package outline HVQFN32: plastic, heatsink very thin quad flat package; no leads; SOT617-1 32 terminals; body 5 x 5 x 0.85 mm terminal 1 index area detail X y1 C pin 1 index 5 mm scale DIMENSIONS (mm are the original dimensions)
  • Page 121 PN512 NXP Semiconductors Transmission Module PUBLIC HVQFN40: plastic, heatsink very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 terminal 1 index area detail X y1 C pin 1 index 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max.

  • Page 122: Abbreviations

    PN512 NXP Semiconductors Transmission Module PUBLIC 27. Abbreviations Table 187. Abbreviations Acronym Description Amplitude Shift keying Start of frame End of frame Proximity Coupling Device. Definition for a Card reader/writer according to the ISO/IEC 14443 specification. PICC Proximity Cards. Definition for a contactless Smart Card according to the ISO/IEC 14443 specification.

  • Page 123: Revision History

    PN512 NXP Semiconductors Transmission Module PUBLIC 28. Revision history Table 188. Revision history Document ID Release date Data sheet status Change notice Supersedes 111334 8 September 2009 Product data sheet Revision 3.3 • Modifications: Section 8.2.3.10 on page 45 ISO14443B mode added •...

  • Page 124: Legal Information

    PN512 NXP Semiconductors Transmission Module PUBLIC 29. Legal information 29.1 Data sheet status [1][2] Document status Product status Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

  • Page 125: Tables

    PN512 NXP Semiconductors Transmission Module PUBLIC 31. Tables Table 1. Quick reference data .....4 Table 34. Description of BitFramingReg bits ..23 Table 2.
  • Page 126 PN512 NXP Semiconductors Transmission Module PUBLIC Table 66. Description of TypeBReg bits ....39 Table 99. TCounterValReg (Lower bits) register Table 67. SerialSpeedReg register (address 1Fh); (address 2Fh); reset value: XXh, reset value: EBh, 11101011b .
  • Page 127 PN512 NXP Semiconductors Transmission Module PUBLIC Table 132.Communication overview for FeliCa Table 173.Input/Output pin characteristics for pins AUX1 reader/writer ......58 and AUX2.

  • Page 128: Table Of Contents

    PN512 NXP Semiconductors Transmission Module PUBLIC 32. Figures Fig 1. Simplified PN512 Block diagram ....5 Fig 41. Timing for F/S mode devices on the I C-bus . . 115 Fig 2.

  • Page 129: Contents

    PN512 NXP Semiconductors Transmission Module PUBLIC 33. Contents Introduction ......1 8.2.3.1 PageReg ......40 8.2.3.2 CRCResultReg .
  • Page 130 PN512 NXP Semiconductors Transmission Module PUBLIC 10.2.1 General ......65 Timer unit ......91 10.3 UART interface .
  • Page 131 PN512 NXP Semiconductors Transmission Module PUBLIC 24.1.8 Input pin characteristics for pin OSCIN..109 24.1.9 Output pin characteristics for pins AUX1 and AUX2 ......110 24.1.10 Output pin characteristics for pins TX1 and TX2 .

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