Philips NXP NXP Manuals

Manuals and User Guides for Philips NXP NXP. We have 1 Philips NXP NXP manual available for free PDF download: Product Data Sheet

Philips NXP NXP Product Data Sheet (131 pages)

Transmission modules

Brand: Philips | Category: Control Unit | Size: 1 MB

Introduction
1
General Description
1
Features
3
Quick Reference Data
4
Ordering Information
4
Fig 1. Simplified PN512 Block Diagram
5
Block Diagram
5
Fig 2. PN512 Block Diagram
6
Fig 3. Pinning Configuration HVQFN32 (SOT617-1)
7
Fig 4. Pinning Configuration HVQFN40 (SOT618)
7
Pinning Information
7
Pinning
7
Pin Description
8
PN512 Register SET
10
PN512 Registers Overview
10
Register Bit Behavior
12
Register Description
13
Command and Status
13
Pagereg
13
Commandreg
13
Commienreg
14
Divienreg
15
Commirqreg
16
Divirqreg
17
Errorreg
18
Status1Reg
19
Status2Reg
20
Fifodatareg
21
Fifolevelreg
21
Waterlevelreg
22
Controlreg
22
Bitframingreg
23
Collreg
24
Communication
25
Pagereg
25
Modereg
26
Txmodereg
27
Rxmodereg
28
Txcontrolreg
29
Txautoreg
30
Txselreg
31
Rxselreg
33
Rxthresholdreg
33
Demodreg
34
Felnfc1Reg
35
Felnfc2Reg
36
Mifnfcreg
37
Manualrcvreg
38
Typebreg
39
Serialspeedreg
39
Configuration
40
Pagereg
40
Crcresultreg
40
Gsnoffreg
41
Modwidthreg
42
Txbitphasereg
42
Rfcfgreg
43
Gsnonreg
44
Cwgspreg
44
Modgspreg
45
Tmode Register, Tprescaler Register
45
Treloadreg
47
Tcountervalreg
48
Test
48
Pagereg
48
Testsel1Reg
50
Testsel2Reg
50
Testpinenreg
51
Testpinvaluereg
51
Testbusreg
52
Autotestreg
52
Versionreg
52
Analogtestreg
53
Testdac1Reg
54
Testdac2Reg
54
Testadcreg
54
Rftreg
55
Fig 5. Reader/Writer Mode
56
Communication Diagram
56
Operating Modes
56
Reader/Writer Mode
56
ISO/IEC 14443A/MIFARE Reader/Writer Functionality
56
Iso/Iec 14443A
57
Data Coding and Framing According to ISO/IEC 14443A/MIFARE
57
Fig 8. Felica Reader/Writer Communication Diagram
58
Felica Reader/Writer Functionality
58
Felica Framing and Coding
58
Fig 9. NFCIP-1 Mode
59
ISO/IEC 14443B Reader/Writer Functionality
59
NFCIP-1 Mode
59
Fig 10. Active Communication Mode
60
Active Communication Mode
60
Fig 11. Passive Communication Mode
61
Passive Communication Mode
61
Fig 12. Card Operation Mode
62
NFCIP-1 Framing and Coding
62
NFCIP-1 Protocol Support
62
Card Operation Mode
62
MIFARE Card Operation Mode
63
Felica Card Operation Mode
63
Digital Interfaces
64
Automatic Host Controller Interface Type Detection
64
SPI Compatible Interface
64
Fig 13. Connection to Host Controller with SPI
65
General
65
Fig 14. Connection to Host Controller with UART
66
UART Interface
66
Connection to a Host Controller
66
Selection of the Transfer Speeds
67
Fig 15. Schematic Diagram to Read Data
68
Framing
68
Fig 16. Schematic Diagram to Write Data
69
Fig 17. I C Interface
70
C Bus Interface
70
General
70
Fig 18. Bit Transfer on the I 2 C-Bus
71
Fig 19. START and STOP Conditions
71
Data Validity
71
START and STOP Conditions
71
Fig 20. Acknowledge on the I 2 C- Bus
72
Fig 21. Data Transfer on the I 2 C-Bus
72
Byte Format
72
Acknowledge
72
Fig 22. First Byte Following the START Procedure
73
7-Bit Addressing
73
Register Write Access
73
Fig 23. Register Read and Write Access
74
Register Read Access
74
Fig 24. I 2 C HS Mode Protocol Switch
75
HS Mode
75
High Speed Transfer
75
Serial Data Transfer Format in HS Mode
75
Fig 25. I 2 C HS Mode Protocol Frame
76
Switching from F/S to HS Mode and Vice Versa
76
Fig 26. Connection to Host Controller with Separated Read/Write Strobes
77
PN512 at Lower Speed Modes
77
8-Bit Parallel Interface
77
Overview of Supported Host Controller Interfaces
77
Separated Read/Write Strobe
77
Fig 27. Connection to Host Controller with Common Read/Write Strobes
78
Common Read/Write Strobe
78
Analog Interface and Contactless UART
79
General
79
TX Driver
79
RF Level Detector
81
Fig 28. Data Mode Detector
82
Data Mode Detector
82
Fig 29. Serial Data Switch for TX1 and TX2
83
Serial Data Switch
83
Serial Data Switch for Driver
83
C Interface Support
83
Fig 30. Communication Flows Using the S
84
Interface
84
Mode
84
Fig 32. Signal Shape for SIGIN in SAM Mode
85
Signal Shape for Felica S C Interface Support
85
Signal Shape for SIGOUT in MIFARE Card SAM Mode
86
Fig 34. Signal Shape for SIGIN in MIFARE Card SAM
86
Waveform Shape for ISO/IEC 14443A and MIFARE S C Support
86
Hardware Support for Felica and NFC Polling
87
Polling Sequence Functionality for Initiator
87
Polling Sequence Functionality for Target
87
Additional Hardware Support for Felica and NFC
88
CRC Co-Processor
88
FIFO-Buffer
89
Overview
89
Accessing the FIFO-Buffer
89
Access Rules
89
Controlling the FIFO-Buffer
89
Status Information about the FIFO-Buffer
90
Timer Unit
91
Interrupt Request System
92
Overview
92
Interrupt Sources Overview
92
Fig 35. Quartz Connection
94
Oscillator Circuitry
94
Power Reduction Modes
95
Hard Power-Down
95
Soft Power-Down
95
Transmitter Power-Down
95
Fig 36. Oscillator Start up Time
96
Reset and Oscillator Start up Time
96
Reset Timing Requirements
96
Oscillator Start up Time
96
PN512 Command Set
97
General Description
97
General Behavior
97
PN512 Commands Overview
97
PN512 Command Description
98
Idle Command
98
Config Command
98
Generate Randomid Command
98
Calccrc Command
99
Transmit Command
99
Nocmdchange Command
99
Receive Command
99
Transceive Command
100
Autocoll Command
100
Fig 37. Autocoll Command
101
Mfauthent Command
102
Softreset Command
102
Testsignals
103
Selftest
103
Testbus
103
Testsignals at Pin aux
105
Prbs
105
Fig 38. Typical Circuit Diagram
106
Application Design-In Information
106
Limiting Values
107
Recommended Operating Conditions
107
Thermal Characteristics
107
Characteristics
108
Input Pin Characteristics
108
Input Pin Characteristics for Pins A0, A1, A2, A3, A4, A5, NCS, NWR, NRD and NRESET
108
Input Pin Characteristics for Pin SIGIN
108
Input/Output Pin Characteristics for Pins D0, D1, D2, D3, D4, D5, D6 and D7
108
Input Pin Characteristics for Pin ALE
108
Output Pin Characteristics for Pin SIGOUT
109
Output Pin Characteristics for Pin IRQ
109
Input Pin Characteristics for Pin Rx
109
Input Pin Characteristics for Pin OSCIN
109
Output Pin Characteristics for Pins TX1 and TX2
110
Output Pin Characteristics for Pins AUX1 and AUX2
110
Current Consumption
111
RX Input Voltage Range
111
Fig 39. RX Input Voltage Range
112
RX Input Sensitivity
112
Clock Frequency
113
XTAL Oscillator
113
Typical 27.12 Mhz Crystal Requirements
113
Fig 40. Timing Diagram for SPI
114
Timing for the SPI Compatible Interface
114
I 2 C Timing
115
8-Bit Parallel Interface Timing
116
AC Symbols
116
AC Operating Specification
116
Bus Timing for Separated Read/Write Strobe
116
Bus Timing for Common Read/Write Strobe
117
Package Information
119
Package Outline
120
Abbreviations
122
Revision History
123
Legal Information
124
Data Sheet Status
124
Definitions
124
Disclaimers
124
Licenses
124
Trademarks
124
Contact Information
124
Tables
125
Table of Contents
128
Figures
128
Contents
129

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