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Emerson PmPPC7448 User Manual

Emerson PmPPC7448 User Manual

Powerpc-based processor pmc module
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Embedded Computing
PmPPC7448:
PowerPC™-Based Processor PMC Module
September 2007

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  • Page 1 User’s Manual from Emerson Network Power ™ Embedded Computing PmPPC7448: PowerPC™-Based Processor PMC Module September 2007...
  • Page 2 EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others.

  • Page 3: Emc Compliance

    Emerson Network Power. Caution: For applications where the PmPPC7448 is provided without a front panel, or where the front panel has been removed, your system chassis/enclosure must provide the required electromagnetic interference (EMI) shielding to maintain EMC compliance.

  • Page 4: Ec Declaration Of Conformity

    EMC Directive and RTTE Directive. We have an inter- nal production control system that ensures compliance between the manufactured products and the technical documentation. Bill Fleury Compliance Engineer Issue date: September 26, 2007 PmPPC7448 User’s Manual 10006757-02...

  • Page 5: Table Of Contents

    PCI Interface Registers ... 5-7 PmPPC7448 Setup ....2-8 PCI Bus Control Signals ....5-7 Power Requirements .
  • Page 6 ......11-13 PmPPC7448 to DMC JTAG ..10-7 Flash Commands .
  • Page 7 ......11-20 12 Acronyms isdram ..... . .11-20 10006757-02 PmPPC7448 User’s Manual...
  • Page 8 (blank page) PmPPC7448 User’s Manual 10006757-02...
  • Page 9 Module Location on Emerson CC1000-DM........2-10...
  • Page 10 (blank page) viii PmPPC7448 User’s Manual 10006757-02...
  • Page 11 PmPPC7448 CPU Features ........
  • Page 12 (blank page) PmPPC7448 User’s Manual 10006757-02...
  • Page 13 Register 7-7: PmPPC7448 ERdy Register (ERdy) at 0xf820,5000 ......7-5 Register 7-8: Hardware Version Register (HVR) at 0xf820,7000 .
  • Page 14 (blank page) PmPPC7448 User’s Manual 10006757-02...

  • Page 15: Overview

    Section 1 Overview The Emerson PmPPC7448 module is a Processor PCI Mezzanine Card (PPMC). It is based on the Freescale® Semiconductor PowerPC™ MPC7448 central processor unit and provides additional processing power for the baseboard, which must be compatible with PPMC architecture.

  • Page 16: Components And Features

    The real-time clock is an ST®Microelectronics M41T00 Serial Access Timekeeper®. Development Mezzanine Card (DMC): The DMC is a custom, optional plug-on card mounted on the back of the PmPPC7448. This card facilitates hardware and software development. See Chapter 10. PmPPC7448 User’s Manual...

  • Page 17: Functional Overview

    Overview: Functional Overview FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the PmPPC7448: Figure 1-1: General System Block Diagram Mini-USB Mini-USB Front Panel Development Motorola Mezzanine Card MPC7448 (DMC) Microprocessor 10/100 Magnetics MPX Bus up to 166 MHz...

  • Page 18: Physical Memory Map

    Overview: Physical Memory Map PHYSICAL MEMORY MAP illustrates the PmPPC7448 memory map: Fig. 1-1 Figure 1-2: PmPPC7448 Memory Map Hex Address FFFF,FFFF Hex Address Boot Mirror F820,E000 PCI Reset Out Enable Register FF80,0000 DMC LED Register F820,D000 Reserved Board Configuration Register 3...

  • Page 19: Address Summary

    Overview: Physical Memory Map summarizes the physical addresses for the PmPPC7448 and provides a reference Table 1-1 to more detailed information: Table 1-1: Address Summary Hex Physical Access Address: Mode: Description: See Page: FF80,0000 Boot Mirror – FF80,0000 Boot Mirror –...

  • Page 20: Additional Information

    Issue 1 Method I Case 3. Product Certification The PmPPC7448 hardware has been tested to comply with various safety, immunity, and emissions requirements as specified by the Federal Communications Commission (FCC), Industry Canada (IC), Underwriters Laboratories (UL), and the European Union Directives (CE mark).

  • Page 21: Ul Certification

    Also, EMC testing was not performed for the configuration with the taller heatsink (for 15 mm connector stackup). This configuration is designed for use on a customer’s proprietary carrier that can support 15 mm PCI mezzanine cards. It is the customer’s responsibility to test this PmPPC7448 configu- ration in their system.

  • Page 22: Rohs Compliance

    Additional Information RoHS Compliance The PmPPC7448 is compliant with the European Union’s RoHS (Restriction of Use of Haz- ardous Substances) directive created to limit harm to the environment and human health by restricting the use of harmful substances in electrical and electronic equipment. Effec-...
  • Page 23 Processor PMC Standard for Processor PCI Mezzanine Cards: VITA 32-2003 Revision 1.0a / 29 April 2003 (VITA: Scottsdale, AZ) http://www.vita.com 3.Frequently, the most current information regarding addenda/errata for specific documents may be found on the corresponding web site. 10006757-02 PmPPC7448 User’s Manual...
  • Page 24 (blank page) 1-10 PmPPC7448 User’s Manual 10006757-02...

  • Page 25: Setup

    Do not place the board on metal or other conductive surfaces. PMPPC7448 CIRCUIT BOARD The PmPPC7448 is a fourteen-layer circuit board that conforms to the IEEE 1386 Common Mezzanine Card (CMC) standard. It has the following physical dimensions: Table 2-1:...

  • Page 26: Pmppc7448 Circuit Board

    Setup: PmPPC7448 Circuit Board The following figures show the component maps for the PmPPC7448 circuit board. Figure 2-1: Component Map, Top (Rev. 06) MPC7447 R564 C320 R505 C325 C321 R507 R33 R34 R510 R511 R508 SODIMM U5 U6 R303 R306...

  • Page 27: Figure 2-2: Component Map, Bottom (Rev. 06)

    Setup: PmPPC7448 Circuit Board Figure 2-2: Component Map, Bottom (Rev. 06) RN21 RN20 1000XXXX-XX D XXXXXX R101 R100 R103 R102 R494 R104 R111 R115 R114 R565 R566 R118 R513 R119 R568 R567 R121 R120 R520 R125 R129 R468 C100 C103...

  • Page 28: Connectors

    Table 8-2 assignments. This is an 80-pin PCB-to-PCB male connector on the bottom side of the PmPPC7448. P3 routes memory, CPLD, and CPU signals from the PmPPC7448 to the DMC for development use. See for the pin assignments.

  • Page 29: Leds

    Setup: PmPPC7448 Circuit Board LEDs The PmPPC7448 has fifteen green light-emitting diodes (LEDs) on the back side of the board (see Fig. 2-3 Figure 2-3: LED Locations, Bottom CR1-Debug LED4 CR2-Debug LED3 CR3-Debug LED2 CR4-Debug LED1 CR5-MPC7448 Check stop out...

  • Page 30: Front Panel

    Emerson. Caution: For applications where the PmPPC7448 is provided without a front panel, or where the front panel has been removed, your system chassis/enclosure must provide the required electromagnetic interference (EMI) shielding to maintain EMC compliance.

  • Page 31: Reset

    Reset The reset signals are routed to the CPLD, unless stated otherwise. See Chapter 7 for the reset registers. The following sources can reset the PmPPC7448: This causes a hard reset to the entire board, including the PCI interfaces. Power-on:...

  • Page 32: Pmppc7448 Setup

    MV_SDA PMC_CPLD_PCI_RST_R* Flash PMPPC7448 SETUP You need the following items to set up and check the operation of the Emerson PmPPC7448: ❐ An Emerson PmPPC7448 board ❐ A compatible host board, such as the Emerson CC1000-DM or Katana750i ❐ Card cage and power supply ❐...

  • Page 33: Power Requirements

    Do not install the board in a rack or remove the board from a rack while power is applied, at risk of damage to the board. Power Requirements Be sure your power supply is sufficient for the PmPPC7448 circuit board. Standard power is 3.3 volts, however a dual power supply option is available. lists the board’s specific Table 2-2 power requirements.

  • Page 34: Installing The Module

    Installing the Module Most PPMC-compatible baseboards have two sets of four connectors (J11, J12, J13, J14 and J21, J22, J23, J24), as defined by the PMC standard P1386.1. This allows the PmPPC7448 to be installed in either PPMC slot. shows the location of these connectors and the Fig.

  • Page 35: Troubleshooting

    Using four M2.5x5 mm panhead screws (Emerson part #10006275-00), secure the PmPPC7448 module from the bottom of the baseboard. First, insert and tighten the screws closest to the P11 through P14 connectors. Next, insert and tighten the screws nearest to the front panel.

  • Page 36: Setup Troubleshooting

    Setup: Troubleshooting ❐ Be sure the PmPPC7448 module is seated firmly on the PPMC host and that the PPMC host is seated firmly in the card cage. ❐ Verify the boot jumper setting if the DMC is installed (see page 10-9).

  • Page 37: Product Repair

    Product ID Serial Number Product Repair If you plan to return the board to Emerson Network Power for service, visit http://www.emersonembeddedcomputing.com/contact/productrepair.html on the inter- net or send e-mail to serviceinfo@artesyncp.com to obtain a Return Merchandise Authori- zation (RMA) number. We will ask you to list which items you are returning and the board serial number, plus your purchase order number and billing information if your PmPPC7448 hardware is out of warranty.
  • Page 38 Setup: Troubleshooting Emerson Network Power, Embedded Computing Test and Repair Services Department 8310 Excelsior Drive Madison, WI 53717 RMA #____________ Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA num- ber.

  • Page 39: Central Processing Unit

    Section 3 Central Processing Unit This chapter is an overview of the processor logic on the PmPPC7448. It includes informa- tion on the CPU, exception handling, and cache memory. The PmPPC7448 utilizes the Free- scale MPC7448 RISC microprocessor, for more detailed information reference the Freescale Semiconductor MPC7450 RISC Microprocessor Family User’s Manual.

  • Page 40: Processor Reset

    Reset Command register in Register Map 7-2. PROCESSOR INITIALIZATION Initially, the PmPPC7448 powers up with specific values stored in the CPU registers. The ini- tial power-up state of the Hardware Implementation Dependent register (HID0) and the...

  • Page 41: Register

    Hardware Implementation Dependent 0 Register The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the PmPPC7448. Please refer to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of the HIDx registers.
  • Page 42 LRSTK: Link Register Stack Enable 0 Link register prediction disabled 1 Allows bclr and bclrl instructions to predict the branch target address using the link reg- ister stack FOLD: Branch Folding Enable 0 Disabled 1 Enabled PmPPC7448 User’s Manual 10006757-02...

  • Page 43: Register 3-2: Mpc7448 Hardware Implementation Dependent, Hid1

    Enable/disable 60x/MPX Bus Data parity checking 0 Disabled 1 Allows a data bus parity error to cause a checkstop or machine check exception BCLK/ECLK: Enable the CLK_OUT output and clock type selection: HRESET*: HID1[ECLK]: HID1[BCLK]: CLK_OUT: Asserted High impedance Negated Zero 10006757-02 PmPPC7448 User’s Manual...

  • Page 44: Exception Handling

    Nonmaskable exceptions have priority over all other exceptions. These exceptions cannot Asynchronous: be delayed and do not wait for completion of any precise exception handling. PmPPC7448 User’s Manual 10006757-02...

  • Page 45: Table 3-3: Mpc7448 Exception Priorities

    AltiVec™ Unavailable Any unavailable AltiVec exception Program (PI) Due to a floating-point enabled exception Alignment Any alignment exception condition Data Storage (DSI) Due to stvx, stvxl, lvx, or lvxl Alignment Due to stvx, stvxl, lvx, or lvxl 10006757-02 PmPPC7448 User’s Manual...

  • Page 46: Exception Processing

    The Machine State register (MSR) configures the state of the MPC7448 CPU. On initial power-up of the PmPPC7448, most of the MSR bits are cleared. Please refer to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of the individual bit fields.

  • Page 47: Register 3-3: Cpu Machine State Register (Msr)

    0 Prevents floating-point instructions dispatch (loads, stores, moves) 1 Executes floating-point instructions Machine Check enable Machine check exceptions disabled 1 Machine check exceptions enabled FE0/FE1: These bits define the Floating-Point Exception mode: FE0: FE1: FP Exception Mode: Disabled Imprecise nonrecoverable 10006757-02 PmPPC7448 User’s Manual...

  • Page 48: Cache Memory

    The MPC7448 processor implements two separate 32-kilobyte, level-one (L1) instruction and data caches that are eight-way, set-associative. The L1 supports a four-state modi- fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ pseudo least-recently-used (PLRU) replacement algorithms within each way. 3-10 PmPPC7448 User’s Manual 10006757-02...

  • Page 49: L2 Cache

    L2 Data-Only mode—for this operation, only data accesses cause new entries to be allocated in the L2 cache. 0 Operation enabled 1 Operation disabled L2REP: L2 Replacement Algorithm 0 Pseudo-random replacement algorithm is used (default) 1 3-bit counter replacement algorithm is used 3-11 10006757-02 PmPPC7448 User’s Manual...
  • Page 50 Power-on reset (automatically performed by the assertion of HRESET* signal). Disable interrupts and dynamic power management (DPM). Disable L2 cache by clearing L2CR[L2E]. Perform an L2 global invalidate. Enable the L2 cache for normal operation by setting the L2CR[L2E] bit to 1. 3-12 PmPPC7448 User’s Manual 10006757-02...

  • Page 51: On-Card Memory Configuration

    • Synchronous DRAM (SDRAM) configurations up to 2 gigabytes • Eight kilobytes of non-volatile memory BOOT MEMORY CONFIGURATION The PmPPC7448 boot default is the on-board Flash which occupies the physical address space beginning at E800,0000 . Selecting jumper JP2 on the optional Development Mez- zanine Card (DMC) allows the 8-bit ROM socket as the boot device (see “DMC Jumpers...

  • Page 52: On-Card Sdram

    • ECC provides single bit correction and two bits detection. NVRAM ALLOCATION The PmPPC7448 uses an eight kilobyte SROM attached to the MV64460 bridge for storing non-volatile information such as board, monitor, and operating system configurations, as well as information specific to user application. All Emerson-specific data is stored in the upper two kilobytes of the device.
  • Page 53 NVRAM Memory Map Window Size Address Offset (hex): Name: (bytes): 0x1E14-0x1FFF Reserved 0x1E00-0x1E13 Test software flags 0x1DDC-0x1DFF Boot verify parameters 0x1DD8-0x1DDB Power-on self-test (POST) diagnostic results 0x1800-0x1DD7 Monitor configuration parameters 1508 0x1600-0x17FF Operating system 0x0000-0x15FF User defined 5632 10006757-02 PmPPC7448 User’s Manual...
  • Page 54 (blank page) PmPPC7448 User’s Manual 10006757-02...

  • Page 55: System Controller

    • A 64-bit interface to DDR SDRAM • A 32-bit interface to devices • Two 64-bit PCI/PCI-X interfaces, only PCI0 is used on the PmPPC7448 These interfaces are connected through a crossbar fabric, or central routing unit, which enables simultaneous operation of the CPU bus, PCI device, and access to memory. The crossbar fabric contains programmable arbitration mechanisms to optimize device perfor- mance.

  • Page 56: Cpu Interface

    • Support for up to 16 pipelined address transactions CPU Interface Registers The PmPPC7448 monitor configures the MV64460 controller so that it provides these 32- bit registers to the PowerPC processor in the correct byte order (assuming the access width is 32 bits).

  • Page 57: Internal Sram

    • Dedicated 32-bit multiplexed address/data bus (separate from the SDRAM bus) • Up to 133 MHz bus frequency • Five chip selects, each with programmable timing • Use as a high bandwidth interface to user specific logic • Supports many types of standard memory devices 10006757-02 PmPPC7448 User’s Manual...

  • Page 58: Device Control Registers

    (PCI) modules and the specification for Processor PCI Mezzanine Cards (PPMC). The MV64460 supports two 64-bit PCI interfaces, compliant to the PCI Local Bus Specification revision 2.3. Only PCI0 is functional on the PmPPC7448. Other features include: •...

  • Page 59: Pci Configuration Space

    Fig. 5-3 Fig. 5-4 Note: Fig. 5-3 is a typical example depending on the PCI system and only if another PmPPC7448 in the system rack is the Monarch. Depending on the host, the PCI memory space may shift. 10006757-02 PmPPC7448 User’s Manual...
  • Page 60 0000,0000 0000,0000 0000,0000 Figure 5-4: Example PCI0 Address Map, Non-Monarch (Default) PCI0 I/O PCI0 Memory B400,0000 B000,0000 B000,0000 PCI Memory Space 8000,0000 8000,0000 Max SDRAM Size SDRAM Size PCI Memory 0400,0000 Space 0000,0000 0000,0000 0000,0000 0000,0000 PmPPC7448 User’s Manual 10006757-02...

  • Page 61: Pci Interface Registers

    A sustained tri-state line is driven high for one clock cycle before float. Note: The PmPPC7448 host board must adhere to the PCI Local Bus Specification (Revision 2.3) for terminating JTAG signals. ACK64*: ACKNOWLEDGE 64-bit TRANSFER This sustained three-state signal indicates the target is willing to transfer data using 64 bits.
  • Page 62 PARITY UPPER DWORD This three-state signal is the even parity bit that protects AD[63:32] and C/BE[7:4]*. PERR*: PARITY ERROR This sustained three-state line is used to report data parity errors during all PCI transactions except a Special Cycle. PmPPC7448 User’s Manual 10006757-02...
  • Page 63 TEST MODE SELECT This input signal controls the state of the TAP controller in the device. TRDY*: TARGET READY A sustained three-state signal that indicates the target’s ability to com- plete the current data phase of the transaction. TRST*: TEST RESET This input signal provides asynchronous initialization of the TAP controller. 10006757-02 PmPPC7448 User’s Manual...

  • Page 64: Pmc Connector Pinouts

    +5 V V(I/O) AD30 AD31 AD29 AD28 AD27 AD26 AD25 AD24 +3.3 V IDSEL C/BE3* AD23 AD22 +3.3 V AD21 AD20 AD19 AD18 +5 V V(I/O) AD16 AD17 C/BE2* FRAME* Not connected TRDY* IRDY* +3.3 V 5-10 PmPPC7448 User’s Manual 10006757-02...

  • Page 65: P13 And P14 Pin Assignments

    AD57 LPb_DB+ LPb_DD+ V(I/O) LPb_DB- AD56 LPb_DD- AD55 AD54 AD53 Not connected Not connected Not connected AD52 Not connected AD51 Not connected AD50 Not connected AD49 Not connected Not connected Not connected AD48 Not connected 5-11 10006757-02 PmPPC7448 User’s Manual...

  • Page 66: Pmc Connector

    SERIAL PORT 1-2 RECEIVE DATA (Input to PMC, TTL or EIA-232) PMC Connector Refer to the component map in for the location of the PMC connectors on the Fig. 2-1 PmPPC7448 circuit board. Figure 5-6: PMC Connector 5-12 PmPPC7448 User’s Manual...

  • Page 67: Doorbell Registers

    MONARCH FUNCTIONALITY The PmPPC7448 can be configured to function as either a Monarch or non-Monarch mod- ule, as described in the VITA 32 PPMC specification. A Monarch is the main PPMC device on the local PCI bus.

  • Page 68: 66 Mhz Bus Operation

    RESET Circuitry on the PmPPC7448 resets the entire module if the voltages fall out of tolerance (due to power-on reset) or if the optional on-board reset switch is activated. The Marvell MV64460 control register settings are initialized immediately following this reset to config- ure the module properly before allowing any external PCI accesses to occur.

  • Page 69: Ethernet Interface

    Section 6 Ethernet Interface The PmPPC7448 provides three independent full duplex Ethernet ports. Using the Marvell MV64460, these ports are configured to one 10/100 Mbps Media Independent Interface (MII) and two 10/100/1000 Mbps Gigabit MII (GMII). The two gigabit Ethernet ports (ports 0 and 1) are routed through PMC connector P14.

  • Page 70: Ethernet Address

    24 bits define a unique identifier that has been assigned to Emerson Network Power by IEEE. The lower 24 bits are defined by Emerson for identification of each of our products. The Ethernet address for the PmPPC7448 is a binary number referenced as 12 hexadecimal digits separated into pairs, with each pair representing eight bits.

  • Page 71: Ethernet Connection (P1)

    Ethernet Cable Wiring Assignments Mini-B USB Pin: Description: RJ45 Pin: Shell Drain wire (shield) Shell (G) White/orange wire (TX+) Orange wire (TX-) White/blue wire (RX+) Blue wire (RX-) No connection No connection No connection No connection 10006757-02 PmPPC7448 User’s Manual...
  • Page 72 (blank page) PmPPC7448 User’s Manual 10006757-02...

  • Page 73: Cpld

    Reset Command Register (RCR) The Reset Command register forces one of several types of resets, as shown below. A reset sequence is initiated by writing a one to a valid bit, then the bit is automatically cleared. 10006757-02 PmPPC7448 User’s Manual...

  • Page 74: Pci Reset Out Enable Register (Roer)

    0 No hard reset (default) PCI Reset Out Enable Register (ROER) The Reset Out Enable register determines the functionality of the PCI ResetOut signal. Register 7-3: Reset Out Enable Register (ROER) at 0xf820,e000 COPH PCI0 Reserved (default is 00) PmPPC7448 User’s Manual 10006757-02...

  • Page 75: Interrupt Registers

    • PERR and SERR are combined into a single interrupt and routed to MPP13. • The non-maskable watchdog timer is routed to MPP18. To control the routing of the interrupts, the CPLD implements the following enable and pending registers. 10006757-02 PmPPC7448 User’s Manual...

  • Page 76: Interrupt Enable Register (Ier)

    CPLD: Interrupt Registers Interrupt Enable Register (IER) Register 7-4: PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000 Reserved SR0EN PR0EN Reserved (default is 000) PCI0 SERR Enable interrupt routed from PCI0 SERR to MV64460 SR0EN: 1 Enabled to generate an interrupt...

  • Page 77: Product Id Register (Pir)

    PmPPC7448 EREADY REGISTER (ERDY) The PmPPC7448 provides a register for status and control of enumeration. In a Monarch system, the register is readable to indicate that other boards in the system are ready for enumeration. In a non-Monarch system, the register is writeable to indicate the PmPPC7448 is ready for enumeration.

  • Page 78: Hardware Version Register (Hvr)

    Monarch/non-Monarch, DMC status, Boot device, and system clock speed. Note: Board Configuration register 2 (0xf820,b000) is not available. Register 7-10: PmPPC7448 Board Configuration 3 (BCR3) at 0xf820,c000 Reserved Reserved: Reserved for future use, default is 0 Mon: Processor PMC Monarch indication...

  • Page 79: Register 7-11: Pmppc7448 Board Configuration 1 (Bcr1) At 0Xf820,A000

    Board Configuration Registers DMC: Development Mezzanine Card installation option 1 DMC is installed 0 DMC is not installed Register 7-11: PmPPC7448 Board Configuration 1 (BCR1) at 0xf820,a000 Reserved Boot Reserved Reserved, default is 0 Boot DMC: Boot from Development Mezzanine Card ROM or PPMC Flash...
  • Page 80 (blank page) PmPPC7448 User’s Manual 10006757-02...

  • Page 81: Serial Input/Output

    Section 8 Serial Input/Output The PmPPC7448 has two EIA-232 serial ports. These ports operate between 9600 and 115,200 baud. Software selects the speed and these settings are stored in non-volatile memory. Serial port one is always routed to the Development Mezzanine Card (DMC) serial connector as 12 volts;...

  • Page 82: Brgx Tuning Register

    RTC (U36) 0xD0 SO-DIMM I2C (U3) 0xAE I/O CONNECTION Specific PmPPC7448 configurations provide a standard EIA-232 serial I/O port; P2 is a mini- USB connector available at the front panel. See below. The cable wiring assign- Table 8-2 ments are in...

  • Page 83: Figure 8-2: Serial Cable Assembly (Emerson Part Number C0007662-00)

    Ground Connector housing ground 1.Signals (pins 2 and 3) can be switched as a factory build option. Figure 8-2: Serial Cable Assembly (Emerson Part Number C0007662-00) Mini-B USB DB9 Connector Caution: The Mini-USB cable connection to P2 does not have a locking mechanism. Pulling on the cable may result in a disconnection.
  • Page 84 (blank page) PmPPC7448 User’s Manual 10006757-02...

  • Page 85: Real-Time Clock

    Section 9 Real-Time Clock The standard real-time clock (RTC) for the PmPPC7448 is provided by an M41T00 device from STMicroelectronics. This device has an integrated year-2000-compatible RTC, power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function.

  • Page 86: Clock Operation

    10 Seconds Seconds Seconds 00—59 10 Minutes Minutes Minutes 00—59 10 Hours Hours Century/ 0-1/ Hours 00-23 01—07 10 Date Date Date 01—31 10 M Month Month 01—12 10 Years Years Years 00—99 Calibration Control — PmPPC7448 User’s Manual 10006757-02...
  • Page 87 256 stage. The number of times pulses are blanked (subtracted, neg- ative calibration) or split (added, positive calibration) depends on this five-bit byte. Adding counts accelerates the clock, and subtracting counts slows the clock down. Don’t care bit 10006757-02 PmPPC7448 User’s Manual...
  • Page 88 (blank page) PmPPC7448 User’s Manual 10006757-02...

  • Page 89: Development Mezzanine Card

    The Development Mezzanine Card (DMC) is an optional plug-on card mounted on the back of the PmPPC7448 board to expedite product development. This chapter describes the physical layout of the DMC, the setup process, and how to check for proper operation once the board has been installed.

  • Page 90: Dmc Circuit Board

    The board serial number appears on a bar code sticker located on the bottom of the board. ❐ The board product identification (ID): _________________________________ . This product ID sticker is located near the serial number. ❐ Any custom or user ROM installed, including version and serial number: ________________________________________________________________ . 10-2 PmPPC7448 User’s Manual 10006757-02...

  • Page 91: Connectors

    The DMC has the following connectors: This 80-pin PCB-to-PCB female connector on the bottom side of the DMC routes memory, CPLD, and CPU signals from the PmPPC7448 to the DMC for development use. See Table 10- for the pin assignments.
  • Page 92 GND/DMC_PD 11 Not connected Not connected Not connected 3.3 V 1. When pin 75 is grounded, this notifies the PmPPC7448 that a DMC module is attached—presence detect (PD). 3.3 V is the power supply to the DMC (analog). 3.3 V: CPLD_TCK: PLD Test Clock is an input to DMC and part of the PLD JTAG interface.
  • Page 93 CPU Test Clock is an output from DMC and part of CPU JTAG interface. DMC_BOOT_SRC: Boot source is an output from DMC and indicates to the PmPPC7448 whether to boot from the DMC socketed Flash or the PmPPC7448 soldered Flash (default).

  • Page 94: P2 Eia-232 Interface

    Development Mezzanine Card: Connectors P2 EIA-232 Interface Use the standard serial cable, Emerson part number C0007662-00, to access connector P2. Pin assignments are listed in Table 10-3 Figure 10-3: DMC P2 Mini-USB Connector Pin 1 Table 10-3: DMC P2 Pin Assignments...

  • Page 95: Pmppc7448 To Dmc Jtag

    3.3 V 1.8V CPLD CPLD_TDI MPC7448_TRST_OUT* P3 JTAG/COP The JTAG/COP interface provides for boundary-scan testing of the CPU and the PmPPC7448. This interface is compliant with the IEEE 1149.1 standard. Figure 10-5: DMC P3 JTAG/COP Header 10-7 10006757-02 PmPPC7448 User’s Manual...

  • Page 96: P4 Jtag Chain Header

    Development Mezzanine Card: PmPPC7448 to DMC JTAG Table 10-4: DMC P3 Pin Assignments Pin: Signal: Pin: Signal: MPC7448_TDO Not connected MPC7448_TDI DEBUG_TRST* Not connected JTAG_PWR (1.8 V) MPC7448_TCK Not connected MPC7448_TMS Not connected DEBUG_SRESET* DEBUG_HRESET* MPC7448CKSTP_OUT* 2. Pin 14 is not installed.

  • Page 97: Dmc Jumpers (Jp1)

    JP2 (pins 3 and 4) selects the 8-bit ROM socket as the boot device. So in order for the socket to provide boot code, the DMC must be seated on the PmPPC7448 and the boot jumper must be in place.

  • Page 98: Jumper Setting Register

    1 Installed (Boot from DMC ROM socket) 0 Not installed (Boot from PmPPC7448 Flash-default) JP1: Jumper 1 on DMC (ENET) is not used for the PmPPC7448. DEBUG/STATUS LEDS The DMC has four green, light-emitting diodes (LEDs) for software development; see for LED locations.

  • Page 99: Dmc Setup

    Development Mezzanine Card: DMC Setup DMC SETUP You need the following items to set up and check the operation of the Emerson DMC. ❐ A compatible PPMC board, such as the Emerson PmPPC7448 ❐ Card cage and power supply ❐ CRT terminal When you unpack the board, save the antistatic bag and box for future shipping or storage.

  • Page 100: Figure 10-8: Dmc Location On Pmppc7448

    Development Mezzanine Card: DMC Setup Figure 10-8: DMC Location on PmPPC7448 1000XXXX-XX XXXXXX Mini-USB RJ45 RJ45 CPLD JTAG 10002939-00 10-12 PmPPC7448 User’s Manual 10006757-02...

  • Page 101: Troubleshooting

    Troubleshooting TROUBLESHOOTING In case of difficulty, use this checklist: ❐ Be sure the PmPPC7448 module is seated firmly on the baseboard and that the baseboard is seated firmly in the card cage. ❐ Verify the boot jumper settings (see Fig. 10-7 ❐...
  • Page 102 Madison, WI 53717 RMA #____________ Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA num- ber. 10-14 PmPPC7448 User’s Manual 10006757-02...

  • Page 103: Monitor

    Section 11 Monitor The PmPPC7448 monitor is based on the Universal Boot (U-Boot) program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.emersonembeddedcomputing.com, send an e- mail to support@artesyncp.com, or call Emerson at 1-800-327-1251.

  • Page 104: Basic Operation

    PM/PPC-7448(1.8)=> BASIC OPERATION The PmPPC7448 monitor performs various configuration tasks upon power-up or reset. This section describes the monitor operation during initialization of the PmPPC7448 board. The flowchart (see ) illustrates the power-up and global reset sequence (bold text Fig. 11-2 indicates environment variables).

  • Page 105: Figure 11-2: Power-Up/Reset Sequence Flowchart

    Turn off debug LEDs Configure the Configure L2 Relocate U-Boot MV64460 device cache per l2cache to RAM chip selects for environment LED 0101 Main Loop flash and CPLD variable 11-3 10006757-02 PmPPC7448 User’s Manual...

  • Page 106: Post Diagnostic Results

    First, make sure that a monitor ROM device is installed in the PLCC socket of the DMC mod- ule and the DMC module is installed on the PmPPC7448. Then, place a jumper on JP2, across pins 3 and 4 on the DMC.

  • Page 107: Updating The Monitor Via Tftp

    PM/PPC-7448 (1.8) => setenv netmask 255.255.255.0 PM/PPC-7448 (1.8) => setenv serverip 10.64.16.168 Optionally, save your settings: PM/PPC-7448 (1.8) => saveenv TFTP the new monitor (binary) image to memory location 0x100000: PM/PPC-7448 (1.8) => tftpboot 100000 path_to_file_on_tftp_server Update the monitor: 11-5 10006757-02 PmPPC7448 User’s Manual...

  • Page 108: Restoring The Pmppc7448 Monitor Using The Katanaqp

    Monitor” on page 11-4. Restoring the PmPPC7448 Monitor Using the KatanaQP To restore the PmPPC7448 monitor image from the soldered flash, the monitor image can be copied to the KatanaQP carrier’s RAM, to the soldered flash, and finally to the socket flash (EEPROM) via a PCI interface.

  • Page 109: Resetting Environment Variables

    Verify that the checksum is correct. KatanaQp(1.0.a) => imi e8100000 The PmPPC7448 monitor image has been successfully copied to the KatanaQP’s soldered flash. Now from the KatanaQP console, copy the image to the socket flash using the following steps. Toggle the memory map to see the socket flash window.

  • Page 110: Accessing The Console Over Ethernet

    PM/PPC-7448 (1.8) => saveenv MONITOR COMMAND REFERENCE This section describes the syntax and typographic conventions for the PmPPC7448 monitor commands. Subsequent sections in this chapter describe individual commands, which fall into the following categories: boot, memory, Flash, environment variables, test, and other commands.

  • Page 111: Command Syntax

    BOOT COMMANDS The boot commands provide facilities for booting application programs and operating sys- tems from various devices. bootd Execute the command stored in the “bootcmd” environment variable. DEFINITION: bootd 11-9 10006757-02 PmPPC7448 User’s Manual...

  • Page 112: Bootelf

    <primary|secondary> update <source> <size> Check validity of images in Flash. bootv <primary|secondary> check bootvx The bootvx command boots VxWorks from an ELF image, where address is the load address of the VxWorks ELF image. DEFINITION: bootvx [address] 11-10 PmPPC7448 User’s Manual 10006757-02...

  • Page 113: Dhcp

    If you do not specify a flag, memory commands default to 32-bit long words. Numeric arguments are in hexadecimal. The cmp command compares count objects between addr1 and addr2. Any differences are displayed on the console display. 11-11 10006757-02 PmPPC7448 User’s Manual...

  • Page 114: Find

    00080000: ffff ffff ffff ffff ffff ffff ffff ffff ....00080010: ffff ffff ffff ffff ffff ffff ffff ffff ....00080020: ffff ffff ffff ffff ffff ffff ffff ffff ....00080030: ffff ffff ffff ffff ffff ffff ffff ffff ....11-12 PmPPC7448 User’s Manual 10006757-02...
  • Page 115 00080010: ffffffff ffffffff ffffffff ffffffff ....00080020: ffffffff ffffffff ffffffff ffffffff ....00080030: ffffffff ffffffff ffffffff ffffffff ....00080040: ffffffff ffffffff ffffffff ffffffff ....00080050: ffffffff ffffffff ffffffff ffffffff ....00080060: ffffffff ffffffff ffffffff ffffffff ....11-13 10006757-02 PmPPC7448 User’s Manual...

  • Page 116: Flash Commands

    The Flash commands affect the StrataFlash devices on the PmPPC7448 circuit board. There is one Flash bank on the PmPPC7448 board. The following Flash commands access the indi- vidual Flash bank as Flash bank 1. To access the individual sectors within each Flash bank, the sector numbers start at 0 and end at one less than the total number of sectors in the bank.

  • Page 117: Protect

    53 100000 1800 100 reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 (right-shifted 7-bit address) and places it in memory at address 0x100000. DEFINITION: Read/write cnt bytes from devaddr EEPROM at offset off. 11-15 10006757-02 PmPPC7448 User’s Manual...

  • Page 118: Icrc32

    .1, .2] value [count] The inm command modifies I C memory, reads it, and keeps the address. DEFINITION: inm chip address[.0, .1, .2] iprobe The iprobe command probes to discover valid I C chip addresses. DEFINITION: iprobe 11-16 PmPPC7448 User’s Manual 10006757-02...

  • Page 119: Environment Parameter Commands

    Set the environment variable name to value or adds the new variable name and value to the environment. setenv name value Removes the environment variable name from the environment. setenv name TEST COMMANDS The commands described in this section perform diagnostic and memory tests. 11-17 10006757-02 PmPPC7448 User’s Manual...

  • Page 120: Diags

    DEFINITION: um [.b, .w, .l] base_addr [top_addr] OTHER COMMANDS This section describes all the remaining commands supported by the PmPPC7448 monitor. autoscr The autoscr command runs a script, starting at address addr, from memory. A valid autoscr header must be present.

  • Page 121: Crc32

    The echo command echoes args to console. DEFINITION: echo [args..] enumpci The enumpci command enumerates the PCI bus if the PmPPC7448 is the Monarch board. DEFINITION: enumpci getmonver The getmonver command prints the monitor version string of the currently running moni- tor (default).

  • Page 122: Help

    Initialize environment variables and serial number in NVRAM but do not update the moni- tor in soldered Flash. moninit <serial#> noburn Initialize environment variables and serial number in NVRAM and copy the monitor from <src_address> into soldered Flash. 11-20 PmPPC7448 User’s Manual 10006757-02...

  • Page 123: Pci

    Other Commands moninit <serial#> <src_address> The pci command enumerates the PCI bus if the PmPPC7448 is the Monarch board. It dis- plays enumeration information about each detected device. The pci command allows you to display values for and access the PCI Configuration Space.

  • Page 124: Script

    Command to execute when auto-booting or executing the ‘bootd’ command. bootdelay Choose the number of seconds the Monitor counts down before booting user application code. Valid options: time in seconds, -1 to disable autoboot 11-22 PmPPC7448 User’s Manual 10006757-02...
  • Page 125 Valid options: all, portdbg, porta (cPSB Port A), portb (cPSB Port B) eth_porta auto Select speed and duplex settings for Ethernet porta. Valid options: 10t_half, 10t_full, 100t_half, 100t_full, auto, disable (must autonegotiate for gigabit speeds) 11-23 10006757-02 PmPPC7448 User’s Manual...

  • Page 126: Table 11-3: Optional Environment Variables

    This parameter takes a decimal value. pri_bootargs Sets the boot arguments that are passed into the primary application images when using the bootv command. If not defined, the bootv will pass the bootargs configuration parameters into the primary application image. 11-24 PmPPC7448 User’s Manual 10006757-02...

  • Page 127: Troubleshooting

    Reset the module while holding down the ‘s’ key. Pressing the ‘s’ key forces a configuration based on default environment variables. DOWNLOAD FORMATS The PmPPC7448 monitor supports binary and Motorola S-Record download formats, as described in the following sections. Binary The binary download format consists of two parts: •...
  • Page 128 (blank page) 11-26 PmPPC7448 User’s Manual 10006757-02...

  • Page 129: Acronyms

    NEBS Network Equipment-Building System Peripheral Component Interconnect Physical Interface PLCC Plastic Leaded Chip Carrier Programmable Logic Device Phase-locked Loop PCI Mezzanine Card POST Power-on Self-test PrPMC Processor PCI Mezzanine Card RISC Reduced Instruction Set Computing 12-1 10006757-02 PmPPC7448 User’s Manual...
  • Page 130 Acronyms: Return Merchandise Authorization Real-time Clock SDRAM Synchronous Dynamic Random Access Memory SO-DIMM Small-outline Dual In-line Memory Serial Presence Detect SROM Serial Read Only Memory UART Universal Asynchronous Receiver/Transmitter Underwriters Laboratories Universal Serial Bus 12-2 PmPPC7448 User’s Manual 10006757-02...
  • Page 131 ... 11-9 serial (P2) pin assignments command syntax ....ii-iii contents, table of ..11-1 command-line interface 10006757-02 PmPPC7448 User’s Manual...
  • Page 132 PCI interfaces .....11-16 ... 1-8 reference manuals PmPPC7448 User’s Manual 10006757-02...
  • Page 133 ....1-7 technical support UL certifications ....1-8 terminology 10006757-02 PmPPC7448 User’s Manual...
  • Page 134 (blank page) PmPPC7448 User’s Manual 10006757-02...
  • Page 135 Notes ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ 10006757-02 PmPPC7448 User’s Manual...
  • Page 136 ■ Embedded Computing Power Switching & Controls Surge & Signal Protection Emerson Network Power, Embedded Computing Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and 8310 Excelsior Drive Madison, WI 53717-1935 USA ■ service marks of Emerson Electric Co.

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