Advertisement

Quick Links

AES-S32V-NXP-G EVK
Designer's Guide
Version 1.1
Page 1
Copyright © 2019 Avnet, Inc. AVNET, "Reach Further," and the AV logo are registered
trademarks of Avnet, Inc. All other brands are the property of their respective owners.
LIT# AES-S32V-NXP-G EVK Designer's Guide rev-1.1

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AES-S32V-NXP-G EVK and is the answer not in the manual?

Questions and answers

Summary of Contents for Avnet AES-S32V-NXP-G EVK

  • Page 1 Designer’s Guide Version 1.1 Page 1 Copyright © 2019 Avnet, Inc. AVNET, “Reach Further,” and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners. LIT# AES-S32V-NXP-G EVK Designer’s Guide rev-1.1...
  • Page 2: Table Of Contents

    Contents Introduction ............................- 4 - 1.1. Glossary ............................- 4 - 1.2. Additional Documentation:......................- 4 - AES-S32V-NXP-G (Core board) ......................- 5 - AES-S32V-NXP-G (Core board) Resources ..................- 7 - 3.1. S32v234 vision processing MPU ....................- 7 - 3.2.
  • Page 3 S32v234 DDR3L PCB Layout ..................... - 47 - Getting Help and Support ........................- 47 - Avnet AES-S32V-NXP-G (Core board) Schematics ................- 47 - Avnet AES-S32V-NXP-G (Carrier board) Schematics ................ - 48 - Release Note ............................- 48 -...
  • Page 4: Introduction

    1. Introduction AES-S32V-NXP-G enables designers to build ADAS, NCAP front camera, object detection and recognition, surround view, automotive and industrial image processing, and also machine learning and sensor fusion applications. This document provides guidelines for designing custom ADAS devlopment kit base on AES- S32V-NXP-G.
  • Page 5: Aes-S32V-Nxp-G (Core Board)

    2. AES-S32V-NXP-G (Core board) AES-S32V-NXP-G (Core board) is a high performance, full-featured, System-On-Module (SOM) based on the NXP ARM®-Based Processor and MCUs S32 MPU family of devices. Designed in a small form factor, the AES-S32V-NXP-G (Core board) packages all the necessary functions such as boot from external memory (SDcard/EMMC/SPI flash), JTAG debug, boot mode configuration, 2GB DDR3L SDRAM, and provides peripheral interfaces for carrier board such as 1Gb Ethernet, PCIe 2.0, 2 x MIPI CSI2, 2 x 16 bits VIU...
  • Page 6 industrial ADAS computing solution. The following sections describe the AES-S32V-NXP-G (Core board) on-board resources and external interfaces to the AES-S32V-NXP-G (Carrier Cards). Figure 1 – AES-S32V-NXP-G (Core board) diagram - 6 -...
  • Page 7: Aes-S32V-Nxp-G (Core Board) Resources

    DDR1 pins More information please refer to S32v234RM3.0 attachment, S32V234_IO_Signal_Description_Input_Multiplexing_Table.xlsx. The following table provide brief descriptions of how each S32v234 Soc resources is used on the Avnet AES-S32V-NXP-G (Core board) followed by detail descriptions in subsequent sections. - 7 -...
  • Page 8: Boot Config Pins

    Table 1 – Port bank assignments for function module Port Module PA0~15 BOOT_RCON[0:8], CAN, JTAG, UART PB0~15 BOOT_RCON[9:22], SPI0, SPI1, SPI2 PC0~15 BOOT_RCON[23:31], SPI2_CS, SPI3 PD0~15 RGMII, VIU0 PE0~15 VIU0 PF0~15 VIU1, eMMC PG0~15 VIU1 PH0~15 Display PJ0~15 Display PK0~15 Display, QSPI_A, QSPI_B, eMMC, SDIO PL0~15 QSPI_B, JTAG...
  • Page 9: Aes-S32V-Nxp-G (Core Board) Power Supply

    Boot Configuration Input 11 AC18 RCON11_I2C2_SDA Boot Configuration Input 12 AA18 RCON12_SPI0_SCK AB20 Boot Configuration Input 13 RCON13_SPI0_SOUT AB18 Boot Configuration Input 14 RCON14_SPI0_SIN AB19 Boot Configuration Input 15 RCON15_SPI0_CS0 Boot Configuration Input 16 AD20 Boot Configuration Input 0 RCON16_SPI1_SCK PB10 Boot Configuration Input 0 AD21...
  • Page 10: Reference Clock Input

    Figure 2 – Avnet AES-S32V-NXP-G (Core board) Power Supply Diagram 3.4. Reference Clock Input The AES-S32V-NXP-G (Core board) provides a 40 MHz single-ended 1.8V reference clock input to the S32v234 SoC. Figure 3 – Avnet AES-S32V-NXP-G (Core board) Reference Clock Input...
  • Page 11: Reset Interface

    3.5. Reset Interface The AES-S32V-NXP-G (Core board) exports power reset input and hard reset IO to J2 for customer carrier board control. Table 3 - Reset Interface Pad Assignment Signal Name Pad Type/Port # FCBGA # Note MCU_RESET Analog Power On Reset Input RESET_B Hard Reset Input/Ouput 3.6.
  • Page 12 SDRAM_256Mx16 S32v234 ADDR[0:14] DATA[0:15] DDR0 DATA[16:31] ADDR[0:14] SDRAM_256Mx16 DATA[0:15] ADDR[0:14] DATA[16:31] DATA[0:15] DATA[16:31] SDRAM_256Mx16 DDR1 ADDR[0:14] ADDR[0:14] DATA[0:15] DATA[0:15] DATA[16:31] DATA[16:31] SDRAM_256Mx16 ADDR[0:14] DATA[0:15] DATA[16:31] Figure 4 - DDR Block Diagram Table 4 – Pinout for DDR3L Interface DDR Port # FCBGA # Notes DDR3 DRAM 0 Addr 0...
  • Page 13 DDR3 DRAM 0 Addr 9 DDR0_A09 DDR3 DRAM 0 Addr 10 DDR0_A10 DDR3 DRAM 0 Addr 11 DDR0_A11 DDR3 DRAM 0 Addr 12 DDR0_A12 DDR3 DRAM 0 Addr 13 DDR0_A13 DDR3 DRAM 0 Addr 14 DDR0_A14 DDR3 DRAM 0 CAS DDR0_CAS_B DDR3 DRAM 0 Bank Addr 0 DDR0_BA0...
  • Page 14 DDR3 DRAM 0 DATA 29 DDR0_D29 DDR3 DRAM 0 DATA 30 DDR0_D30 DDR3 DRAM 0 DATA 31 DDR0_D31 DDR3 DRAM 0 DQS 0 Positive DDR0_DQS0_P DDR3 DRAM 0 DQS 0 Nagetive DDR0_DQS0_N DDR3 DRAM 0 DQS 1 Positive DDR0_DQS1_P DDR3 DRAM 0 DQS 1 Nagetive DDR0_DQS1_N DDR3 DRAM 0 DQS 2 Positive DDR0_DQS2_P...
  • Page 15 DDR3 DRAM 1 CAS DDR1_CAS_B DDR3 DRAM 1 Bank Addr 0 DDR1_BA0 DDR3 DRAM 1 Bank Addr 1 DDR1_BA1 DDR3 DRAM 1 Bank Addr 2 DDR1_BA2 DDR3 DRAM 1 DATA 0 DDR1_D00 DDR3 DRAM 1 DATA 1 DDR1_D01 DDR3 DRAM 1 DATA 2 DDR1_D02 DDR3 DRAM 1 DATA 3 DDR1_D03...
  • Page 16 DDR3 DRAM 1 DQS 1 Nagetive DDR1_DQS1_N DDR3 DRAM 1 DQS 2 Positive DDR1_DQS2_P DDR3 DRAM 1 DQS 2 Nagetive DDR1_DQS2_N DDR3 DRAM 1 DQS 3 Positive DDR1_DQS3_P DDR3 DRAM 1 DQS 3 Nagetive DDR1_DQS3_N DDR3 DRAM 1 CKE 0 DDR1_CKE0 DDR3 DRAM 1 CS 0 DDR1_CS0_B...
  • Page 17: Rgmii Interface

    3.7. RGMII Interface The AES-S32V-NXP-G (Core board) provides a single Gigabit Ethernet PHY interface for the Marvell 88E5050 RGMII PHY device in 56-pin QFN package located on the custom Carrier Board. The AES-S32V-NXP-G (Core board) Gigabit Ethernet PHY connector side (J1 connector) connected to Marvell 88E5050 on Carrier Board, which provides an RJ45 connector and four T1 connected located on the custom Carrier Card can be used to implement Gigabit Ethernet port and AVB applications.
  • Page 18: Spi Interfaces

    3.9. SPI Interfaces The S32v234 SoC has four channels SPI, SPI0~SPI3. TheAES-S32V-NXP-G (Core board) connects SPI0~SPI3 to J3 for custom Carrier Board. On Avnet Carrier Board, only SPI0 and SPI1 are implemented, connected to J14 and J15 via NX3DV2567HR (NC) switch on each channel.
  • Page 19: Micro Sd Card

    S32V234 NX3DV642GU SW Nor Flash QSPI_A D2+/- DATA[0:3] QSPI_A_CS0 CLK2+ QSPI_A_DATA[0:3] D+/- QSPI_A_DQS CLK- TF Card QSPI_A_SCK CLK+ D1+/- DATA[0:3] CLK1+/- CMD/CLK QSPI_EMMC_SW Figure 5 - QSPI_A to NOR Flash / SD Card Switch Table 8 - QSPI Flash Pin Assignments Signal Name Port # FCBGA #...
  • Page 20: Qspi Interface

    QSPI_A_DATA2 PK10 SD Data 2 QSPI_A_DATA3 PK11 SD Data 3 PK11 QSPI_A_DQS SD Command QSPI_A_SCK SD Clock 3.12. QSPI Interface AES-S32V-NXP-G (Core board) connect QSPI_B ports to external connector J1 [57:62] for custom Carrier Board use. Table 10 - QSPI Interface Assignments Signal Name Port # FCBGA #...
  • Page 21: Uart Interface

    Figure 6 - SAR_ADC High-level interface Diagram Table 12 - ADC Interface Pads Assigment Signal Name Pad Type FCBGA # Notes Analog ADC_SE0 ADC Single Ended Input 0 Analog ADC_SE1 ADC Single Ended Input 1 Analog ADC_SE2 ADC Single Ended Input 2 Analog ADC_SE3 ADC Single Ended Input 3...
  • Page 22: Jtag Interface

    UART 1 Transmit Output RCON6_UART1_TXD PA14 AA21 3.16. JTAG Interface The S32v234 SoC contains JTAG Controller. The AES-S32V-NXP-G (Core board) exports JTAG interface to on-board 10-pin JTAG connector J4. Table 14 - JTAG Interface Pads Assignment Signal Name Port # FCBGA # Notes JTAG_TDI...
  • Page 23: Mipi Csi Interface

    alternate pin-muxing details. The AES-S32V-NXP-G (Core board) exports Trace interface to J3 [22:38] for Custom Carrier Board. Table 15 - Trace Port Pads Assignment Signal Name Port # FCBGA # Notes TRACE_D00 AD18 Trace Port Data 0 Output TRACE_D01 Trace Port Data 1 Output TRACE_D02 PG10 AB17...
  • Page 24: Display Interface

    Table 17 - MIPI-CSI1 port mapping Signal Name Pad Type FCBGA # Notes MIPI_PAD CSI1_CLK_P MIPI CSI-2 Clock Positive Input MIPI_PAD CSI1_CLK_N MIPI CSI-2 Clock Negative Input MIPI_PAD CSI1_DATA0_P MIPI CSI-2 Positive Input Data Lane 0 MIPI_PAD CSI1_DATA0_N MIPI CSI-2 Negative Input Data Lane 0 CSI1_DATA1_P MIPI_PAD MIPI CSI-2 Positive Input Data Lane 1...
  • Page 25: Lfast Interface

    DISP0_DAT16 PH13 DCU Red 0 Output DISP0_DAT17 PH14 DCU Red 1 Output DISP0_DAT18 PH15 DCU Red 2 Output DISP0_DAT19 DCU Red 3 Output DISP0_DAT20 DCU Red 4 Output DISP0_DAT21 DCU Red 5 Output DISP0_DAT22 DCU Red 6 Output DISP0_DAT23 DCU Red 7 Output DISP0_VSYNC DCU Vertical Sync Output DISP0_HSYNC...
  • Page 26: Flexray Interface

    Table 20 – FlexTimer Features Feature FTM0 FTM1 Number of channels Channel input filter Channel 0, 1, 2 and 3 Channel 0, 1, 2 and 3 Number of fault inputs Initial counting value Input capture mode The AES-S32V-NXP-G (Core board) exports FTM0 channel0~3 to J3 for customer carrier board.
  • Page 27: Fccu Outputs

    Figure 9 – FlexRay Block Diagram The AES-S32V-NXP-G (Core board) exports following FlexRay interface to J2 [7:10] for customer carrier board. Table 22 - FlexRay Interface Pads Assignment Signal Name Port # FCBGA # Notes RCON2_FLXR_RXD_A FlexRay Receive Data Channel A Input RCON1_FLXR_TXD_A FlexRay Transmit Data Channel A Output FLXR_TXEN_A...
  • Page 28: Pcie Interface

    Figure 10 - FCCU block diagram The AES-S32V-NXP-G (Core board) exports FCCU_F0 and FCCU_F1 to J2 for customer carrier board. Table 23 - FCCU Output Pads Assignment Signal Name FCBGA # Notes FCCU_F0 FCCU Fault 0 FCCU_F1 FCCU Fault 1 3.24.
  • Page 29: Emmc Memory

    system memory via its own master bus interface. The device contains two instances of VIULite - VIU0 and VIU1. VIU0 supports upto 20 bit pixel data inputs and VIU1 supports upto 16 bit pixel data inputs with lower 4 bits multiplexed. Please refer to I/O Signal Description and Input Multiplexing Tables (Excel files) of chapter "Signal Description"...
  • Page 30: J1~J3 Micro Connectors

    The S32v234 SoC supports one ultra Secure Digital Host Controller (uSDHC) module. The uSDHC provides the interface between the host system and the SD/SDIO/MMC cards. The AES-S32V-NXP-G (Core board) provides a 32GB eMMC memory as one of booting devices. The EMMC device connect to multiplexing IO ports PF [1:11], and PK14 as eMMC data strobe input.
  • Page 31: Boot Configuration Switches

    Figure 11 - J1, J2, J3 Exporting Module Diagram 3.28. Boot Configuration Switches The AES-S32V-NXP-G (Core board) provides 2 switches to select boot configurations, S1 and S2. Picture 2 - Boot Configuration Switches, S1, S2 Table 28 - Boot Configuration Signal to Switch Pin Mapping Signal Name Switch # Switch Pos #...
  • Page 32: Aes-S32V-Nxp-G (Carrier Board) Resources

    4.1. Power Input The Avnet AES-S32V-NXP-G (Carrier board) requires 12V-DC power input from P1.Voltage regulators are used on the Avnet AES-S32V-NXP-G (Carrier board) to provide power to all components/interfaces used on the Avnet AES-S32V-NXP-G (Carrier board), and provide voltages, VDD_1V8, VDD_3V3, PMIC_FEED_5V0, to the AES-S32V-NXP-G (Core board) via J9.
  • Page 33: Soc Heat Fan Power Input

    Users can use either a 5V or a 12V fan with the AES-S32V-NXP-G (Core board) heat sink (The AES-S32V-NXP-G (Core board) is shipped with a 12V fan). The fan header are located on the Avnet AES-S32V-NXP-G (Carrier board) and must be designed to match the fan voltage used on the SOM.
  • Page 34: Can Connector

    Figure 13 - CAN Block Diagram 4.4. 2 x SPI Connectors The Avnet AES-S32V-NXP-G (Carrier board) contains two SPI connectors. Between the SPI connector and each channel of SPI signals from AES-S32V-NXP-G (Core board), there is a four-pole double-throw analog switch NX3DV2567HR.
  • Page 35: Debug Uart Port

    Figure 14 - SPI Block Diagram 4.5. Debug UART Port The Avnet AES-S32V-NXP-G (Carrier board) provide a debug uart via Micro-USB port.The TX/RX signals come from AES-S32V-NXP-G (Core board) LinFlexD0 controller. Figure 15 - Debug UART Block Diagram 4.6. PWM Output The AES-S32V-NXP-G (Carrier board) provides a PWM header intended for DMS camera LED.
  • Page 36: Phy Connectors

    Figure 16 - PWM Interface block diagram 4.7. PHY connectors The Avnet AES-S32V-NXP-G (Carrier board) provides following kinds of PHY connectors: 1 x RJ45 for DEBUG 5 x 100MB T1 for video in (one for front view, other four for surround view)
  • Page 37: Introduction Of 88Q5050

    4.7.1 Introduction of 88Q5050 The Ethernet switch, 88Q5050, is an 8-port Ethernet gigabit capacity switch that is fully compliant with IEEE802.3 automotive standard and utilizes advanced security features to guard against hacking and denial of service (DoS) attacks. The 8-port Ethernet switch offers 4 fixed IEEE 100BASE-T1 ports, and a configurable selection of an additional 4 ports from 1x IEEE 100BASE-T1 port, 1x IEEE 100BASE- TX, 2x MII/RMII/RGMII ports, 1 GMII port, and 1 SGMII port.
  • Page 38: Hdmi

    DCU_DE DCU_R[0:7], DCU_G[0:7], DCU_B[0:7] On the Avnet AES-S32V-NXP-G (Carrier board), above signals are sent to HDMI Transmitter Sil9022A which transform DCU signals to HDMI signals. Then the HDMI signals were sent to level shifter and ESD protection TPD12S521DBTR. The final HDMI signals were connected with HDMI input device via HDMI-TYPE-A-19 connector.
  • Page 39: Camera Inputs

    Figure 19 - HDMI Interface diagram 4.9. Camera Inputs The Avnet AES-S32V-NXP-G (Carrier board) provides 5 coax cable connectors for 720P camera inputs, which can fulfill most ADAS applications, one for front view, other four for surround view. Camera data will be deserialized by MAX9286 and MAX96705, and transfer to S32v234 SoC via MIPI-CSI2 and VIU0 interface on the AES-S32V-NXP-G (Core board).
  • Page 40: Introduction Of Max9286

    Figure 20 - Camera Inputs Block Diagram 4.9.1 Introduction of MAX9286 The MAX9286 Gigabit multimedia serial link (GMSL) deserializer receives data from up to four GMSL serializers over 50Ω coax or 100Ω shielded twisted-pair (STP) cables and output data on four CSI-2 lanes. Each serial link has an embedded control channel operating from 9.6kbps to 1Mbps in UART-to-UART, UART-to-I²C, and I²C-to-I²C mode.
  • Page 41: Introduction Of Max96706

     Ideal for Multicamera Stream Applications Works with Low-Cost 50Ω Coax Cable and FAKRA Connectors or 100Ω STP Data from Image Sensors Are Synchronized to the Same Pixel Automatic Internal/External Generation of Camera Sync Equalization Allows 15m Length Cable Operation at Full Speed ...
  • Page 42: Pcie To Usb3.0

    9.6kbps to 1Mbps Control Channel in UART, I2C (with Clock Stretch), or UART-to-I2C Modes 2:1 Input Mux for Camera Selection 15 Hardware-Selectable I2C-Device Addresses Pairs with Any Maxim GMSL Serializer Crosspoint Switch Maps Data to any Output  Reduces EMI and Shielding Requirements Spread-Spectrum Serial-Input Tracking and Transfer to the Parallel Output 1.7V to 1.9V Core and 1.7V to 3.6V I/O Supply...
  • Page 43: J9~J11 Micro Connector

    Ta:-40 ~ 85°C (μPD720201K8-711-BAC-A) 4.11. J9~J11 Micro Connector The Avnet AES-S32V-NXP-G (Carrier board) utilizes 3 micro headers to provide connections to AES-S32V-NXP-G (Core board). These connectors will carry the following signals and power/ground pins (signal directions are with respect to the...
  • Page 44 Figure 22 - AES-S32V-NXP-G (Core board) Signals to Avnet Carrier Board via Connector (80-pin IMSA-9827S-80ZXX-GF) o CAN pins (CAN_FD0_RXD/RXD, CAN_FD1_RXD/TXD) o System LED pin (SYS_LED) o Debug Uart pins (RCON3_UART0_TXD, RCON4_UART0_RXD) o Test points (MCU_RESET, RESET_B) o MIPI-CSI0 pins (CSI0_DATA[0:3]_N/P, CSI0_CLK_N/P)
  • Page 45 Figure 23 - AES-S32V-NXP-G (Core board) Signals to Avnet Carrier Board via J11 Connector (80-pin IMSA-9827S-80ZXX-GF) o PCIE pins (PCIE_RX_P/N, PCIE_TX_P/N, PCIE_CK1_P/N, PCIE_CK2_P/N, PCIE_PWR_ON, PCIE_CLKREQ, PCIE_WAKEn, PCIE_RESET) o I2C pins (I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA) o SPI pins (SPI0/1_SW, SPI0/1_CS0, SPI0/1_SCK, SPI0/1_SIN,...
  • Page 46: Aes-S32V-Nxp-G Pcb Layout Notes

    Figure 24 - AES-S32V-NXP-G (Core board) Signals to Avnet Carrier Board via 5. AES-S32V-NXP-G PCB Layout Notes The PCB layout of AES-S32V-NXP-G (Core board) and Carrier board is designed with following rules: PCIE - For the two traces in a differential pair equal lengths to 10 mil, ground impedance is 85 Ω...
  • Page 47: S32V234 Ddr3L Pcb Layout

    Figure 25 - AES-S32V-NXP-G DDR3L Control Diagram 6. Getting Help and Support If additional support is required, Avnet has many avenues to search depending on your needs.For general question regarding AES-S32V-NXP-G (Core board) and Carrier Card or accessories, please visit our website athttp://to-be-referenced .
  • Page 48: Avnet Aes-S32V-Nxp-G (Carrier Board) Schematics

    8. Avnet AES-S32V-NXP-G (Carrier board) Schematics The Avnet AES-S32V-NXP-G (Carrier board) schematics are located on the documentation page. You can locate that here: http://to-be-referenced 9. Release Note Version Release date Author Note Rev-1.0 03-May-2019 Air.Xu First version Rev-1.1 20-Sept-2019 Air.Xu...

Table of Contents