Download
Share
Print this page
Atmel AT86RF233 Data Sheet / Manual
  1. Manuals
  2. Brands
  3. Atmel Manuals
  4. Transceiver
  5. AT86RF233
  6. Data sheet / manual
Atmel AT86RF233 Data Sheet / Manual

Atmel AT86RF233 Data Sheet / Manual

Low power, 2.4ghz transceiver for zigbee, rf4ce, ieee 802.15.4, 6lowpan, and ism applications
Hide thumbs

Advertisement

Quick Links

Download this manual
Features
• High Performance RF-CMOS 2.4GHz radio transceiver targeted for
®
IEEE
802.15.4, ZigBee
• Industry leading link budget:
- Receiver sensitivity -101dBm
- Programmable output power from -17dBm up to +4dBm
• Ultra-low current consumption:
- DEEP_SLEEP
- TRX_OFF
- RX_ON
- RX_ON
- BUSY_TX
• Ultra-low supply voltage (1.8V to 3.6V) with internal regulator
• Support for coin cell operation
• Optimized for low BoM Cost and ease of production:
- Few external components necessary (crystal, capacitors and antenna)
• Easy to use interface:
- Registers, frame buffer and AES accessible through fast SPI
- Only two microcontroller GPIO lines necessary
- One interrupt pin from radio transceiver
- Clock output with prescaler from radio transceiver
• Radio transceiver features:
- 128-byte FIFO (SRAM) for data buffering
- Fully integrated, fast settling PLL to support Frequency Hopping
- Supports 500kHz channel spacing
- Battery monitor
- Fast Wake-Up Time < 0.4msec
• Special IEEE 802.15.4
- FCS computation and Clear Channel Assessment
- RSSI measurement, Energy Detection and Link Quality Indication
• MAC hardware accelerator:
- Automated acknowledgement, CSMA-CA and retransmission
- Automatic address filtering
- Automated FCS check
• Extended feature set hardware support:
- AES 128-bit hardware accelerator
- Antenna Diversity and RX/TX indication
- Supported PSDU data rates: 250kb/s, 500kb/s, 1000kb/s and 2000kb/s
- True Random Number Generation for security application
- Reduced Power Consumption modes (patent pending)
• Industrial temperature range:
- -40°C to +85°C
• I/O and packages:
- 32-pin Low-Profile QFN Package 5 x 5 x 0.9mm³
- RoHS/Fully Green
• Compliant to IEEE 802.15.4-2003/2006/2011
• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210
8351A–MCU Wireless–02/12
®
, RF4CE, 6LoWPAN, and ISM applications
= 0.02µA
= 300µA
= 11.8mA
=
mA
6.0
= 13.8mA
™
-2011 hardware support:
(LISTEN w/o Smart Receiving)
(LISTEN w/ Smart Receiving)
(at max. transmit power)
AT86RF233
Low Power,
2.4GHz
Transceiver for
ZigBee, RF4CE,
IEEE 802.15.4,
6LoWPAN, and
ISM
Applications
AT86RF233
PRELIMINARY
Rev. 8351A–MCU Wireless–02/12
1

Advertisement

loading
Need help?

Need help?

Do you have a question about the AT86RF233 and is the answer not in the manual?

Questions and answers

Related Manuals for Atmel AT86RF233

Summary of Contents for Atmel AT86RF233

  • Page 1 AT86RF233 Features • High Performance RF-CMOS 2.4GHz radio transceiver targeted for ® ® IEEE 802.15.4, ZigBee , RF4CE, 6LoWPAN, and ISM applications • Industry leading link budget: - Receiver sensitivity -101dBm - Programmable output power from -17dBm up to +4dBm •...

  • Page 2: Pin-Out Diagram

    1 Pin-out Diagram Figure 1-1. Atmel AT86RF233 Pin-out Diagram. 31 30 29 28 27 26 25 DIG3 exposed paddle DIG4 /SEL AVSS AVSS MOSI DVSS AT86RF233 MISO AVSS SCLK DVSS DVSS /RST CLKM 9 10 11 12 13 14 15 16 Note: The exposed paddle is electrically connected to the die inside the package.

  • Page 3: Pin Descriptions

    AT86RF233 1.1 Pin Descriptions Table 1-1. Atmel AT86RF233 Pin Description. Pins Name Type Description DIG3 Digital output (Ground) 1. RX/TX Indicator, see Section 11.5 2. If disabled, pull-down enabled (AVSS) DIG4 Digital output (Ground) 1. RX/TX Indicator (DIG3 inverted), see Section 11.5...

  • Page 4: Analog And Rf Pins

    1.2 Analog and RF Pins 1.2.1 Supply and Ground Pins EVDD, DEVDD ® EVDD and DEVDD are analog and digital supply voltage pins of the Atmel AT86RF233 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation.

  • Page 5: Crystal Oscillator Pins

    1.2.3 Crystal Oscillator Pins XTAL1, XTAL2 The pin 26 (XTAL1) of Atmel AT86RF233 is the input of the reference oscillator amplifier (XOSC), the pin 25 (XTAL2) is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.6.

  • Page 6: Digital Pins

    1.3 Digital Pins The Atmel AT86RF233 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Chapter Additional digital output signals DIG1, …, DIG4 are provided to control external blocks,...

  • Page 7: Disclaimer

     Health care  Consumer electronics  PC peripherals ® The AT86RF233 can be operated by using an external microcontroller like Atmel AVR microcontrollers. A comprehensive software programming description can be found in reference [7], AT86RF233 Software Programming Model. 8351A–MCU Wireless–02/12...

  • Page 8: General Circuit Description

    4 General Circuit Description The Atmel AT86RF233 single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation demodulation including time frequency synchronization and data buffering. The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required.
  • Page 9 An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the Atmel AT86RF233, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines.

  • Page 10: Application Schematic

    5 Application Schematic 5.1 Basic Application Schematic A basic application schematic of the Atmel AT86RF233 with a single-ended RF connector is shown in Figure 5-1. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required.
  • Page 11 Therefore, a low-pass filter (C3, R1) is placed close to the Atmel AT86RF233 CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the pin 17 (CLKM) is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization.

  • Page 12: Extended Feature Set Application Schematic

    Section 11.8  Alternate Start-Of-Frame Delimiter Section 11.9  Reduced Power Consumption Mode (RPC) Section 11.10 An extended feature set application schematic illustrating the use of the AT86RF233 Extended Feature Set, see Chapter 11, is shown in Figure 5-2. Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations.
  • Page 13 AT86RF233 In this example, a balun (B1) transforms the differential RF signal at the Atmel AT86RF233 radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 5-1. During receive mode the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm.

  • Page 14: Microcontroller Interface

    DIG2 Microcontrollers with a master SPI such as Atmel AVR family interface directly to the AT86RF233. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller.

  • Page 15: Spi Timing Description

    An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.3. /SEL = L enables the MISO output driver of the Atmel AT86RF233. The MSB of MISO is valid after t (see Section 12.4 parameter) and is updated at each falling edge of SCLK.

  • Page 16: Spi Protocol

    Figure 6-2 Figure 6-3 Atmel AT86RF233 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t...

  • Page 17: Frame Buffer Access Mode

    READ DATA 6.3.2 Frame Buffer Access Mode The Atmel AT86RF233 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in Section 9.3.
  • Page 18 (/SEL = H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field. The content of the Atmel AT86RF233 Frame Buffer is overwritten by a new received frame or a Frame Buffer write access.

  • Page 19: Sram Access Mode

    Atmel AT86RF233 Frame Buffer or AES address space, refer to Section 11.1. During frame receive after occurrence of interrupt IRQ_2 (RX_START) an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer...
  • Page 20 Figure 6-13 Figure 6-14 illustrate an example SPI sequence of an Atmel AT86RF233 SRAM access to read and write a data package of 5-byte length respectively. Figure 6-13. Example SPI Sequence – SRAM Read Access of a 5-byte Data Package.

  • Page 21: Radio Transceiver Status Information

    AT86RF233 6.4 Radio Transceiver Status information Each Atmel AT86RF233 SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1).

  • Page 22: Radio Transceiver Identification

    6.5 Radio Transceiver Identification The Atmel AT86RF233 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Additional two registers contain the JEDEC manufacture ID. 6.5.1 Register Description Register 0x1C (PART_NUM): The register PART_NUM can be used for the radio transceiver identification and includes the device part number.
  • Page 23 Value Description MAN_ID_0 0x1F Atmel JEDEC manufacturer ID, bits[7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The higher 16 bits of the ID are not stored in registers.

  • Page 24: Sleep/Wake-Up And Transmit Signal (Slp_Tr)

    SLEEP state The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF233 can be powered down to reduce the overall power consumption. A power-down scenario is shown in Figure 6-20. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF233 to SLEEP by setting SLP_TR = H.
  • Page 25 When the radio transceiver is in PREP_DEEP_SLEEP state the microcontroller forces the AT86RF233 to DEEP_SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations.

  • Page 26: Interrupt Logic

    7.1.3 TX: Indicates the completion of a frame transmission. 7.1.3 IRQ_2 (RX_START) Indicates the start of an PSDU reception; the AT86RF233 state changed to BUSY_RX; 7.1.3 the PHR can be read from Frame Buffer. IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, 9.7.5...

  • Page 27: Interrupt Mask Modes And Pin Polarity

    IRQ_MASK (register 0x0F) (register 0x0E) The Atmel AT86RF233 IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin 24 (IRQ) = H issues an interrupt request. If the “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access, the IRQ pin has an alternative functionality, refer to Section 11.7...

  • Page 28: Register Description

    IRQ_4_CCA_ED_ IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_STATUS DONE Read/Write Reset value 0x0F IRQ_2_RX_ IRQ_1_PLL_ IRQ_0_PLL_ IRQ_3_TRX_END IRQ_STATUS START UNLOCK LOCK Read/Write Reset value For more information to meanings of interrupts, see Table 6-10 Interrupt Description in Basic Operating Mode. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 29 AT86RF233 By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register. Notes:...
  • Page 30 A modification on IRQ_POLARITY bit has no influence to RX_BL_CTRL behavior. This setting does not affect the polarity of the “Frame Buffer Empty Indicator”, refer to Section 11.7. The Frame Buffer Empty Indicator is always active high. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 31: Operating Modes

    7.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the Atmel AT86RF233, such as receiving and transmitting frames, the power-on sequence, sleep and deep sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and general ISM band applications;...

  • Page 32: State Control

    (register 0x01, TRX_STATUS). TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) Atmel AT86RF233 is in a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin 11 (SLP_TR) is a multifunctional pin, refer to Section 6.6.
  • Page 33 DIG3/DIG4 are pulled-down to analog ground, unless their configuration is changed. Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF233 pins to the default operating values: pin 11 (SLP_TR) = L, pin 8 (/RST) = H and pin 23 (/SEL) = H.
  • Page 34 7.1.2.7 RX_ON and BUSY_RX – RX Listen and Receive State In RX_ON state the receiver module and the PLL frequency synthesizer are enabled. The Atmel AT86RF233 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on.
  • Page 35 PLL_ON state. 7.1.2.9 RESET State The RESET state is to reset all registers and state machines of the AT86RF233 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4.

  • Page 36: Interrupt Handling

    7.1.3 Interrupt Handling All interrupts provided by the Atmel AT86RF233 (see Table 6-10) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. On reception IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception.

  • Page 37: Basic Operating Mode Timing

    AT86RF233 7.1.4 Basic Operating Mode Timing The following paragraphs depict Atmel AT86RF233 state transitions and their timing properties. Timing figures are explained in Table 7-1, Table 7-2, and Section 12.4. 7.1.4.1 Power-on Procedure The power-on procedure to P_ON state is shown in Figure 7-3.
  • Page 38 XOSC, DVREG XOSC, DVREG Time TR18 The Atmel AT86RF233 radio transceiver’s DEEP_SLEEP state is left by releasing SLP_TR pin to logic low. This restarts the XOSC and DVREG. After t = 360µs (typ.) TR18 the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided default rate of 1MHz clock to pin 17 (CLKM).
  • Page 39 Starting from PLL_ON state it is further assumed that the PLL is already locked. A transmission is initiated either by a rising edge of pin 11 (SLP_TR) or by command TX_START, the Atmel AT86RF233 changes into BUSY_TX state. The PLL settles to the transmit frequency and the PA is enabled. t = 16µs after...
  • Page 40 TRX_OFF state. If register bits TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the Atmel AT86RF233 reaches TRX_OFF state, do not try to initiate a further state change while the radio transceiver is in this state. Notes:...
  • Page 41 AT86RF233 7.1.4.7 State Transition Timing Summary The Atmel AT86RF233 transition numbers correspond to Figure 7-1 and do not include SPI access time unless otherwise stated. See measurement setup in Figure 5-1. Table 7-1. State Transition Timing. Symbol Parameter Condition Min.
  • Page 42 RSSI update period in receive µs RSSI states. ED measurement ED measurement period is eight µs symbols. CCA measurement CCA measurement period is eight µs symbols. Random value, update Random value update period. µs AES core cycle time 23.4 µs AT86RF233 8351A–MCU Wireless–02/12...

  • Page 43: Register Description

    AT86RF233 7.1.5 Register Description Register 0x01 (TRX_STATUS): The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 7-9. Register TRX_STATUS. 0x01 CCA_DONE CCA_STATUS reserved TRX_STATUS TRX_STATUS Read/Write Reset value...
  • Page 44 RESET, as well as STATE_TRANSITION_IN_PROGRESS towards these states. Extended Operating Mode only. A write access to register bits TRX_CMD initiates a radio transceiver state transition towards the new state. These register bits are used for Basic and Extended Operating Mode, see Section 7.2. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 45: Extended Operating Mode

    TRAC_STATUS, Section 7.2.7. An Atmel AT86RF233 state diagram, including the Extended Operating Mode states is shown in Figure 7-11. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode.
  • Page 46 SLP_TR=H Detected TX_START RX_AACK_ON RX_AACK_ON TX_ARET_ON BUSY_RX_AACK BUSY_TX_ARET TX_ARET_ON Trans- Frame action Finished Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States Extended Operating Mode States AT86RF233 8351A–MCU Wireless–02/12...

  • Page 47: State Control

    TX_START to register bits TRX_CMD. The TX_ARET state is left by writing a new command to the register bits TRX_CMD. If the AT86RF233 is within a CSMA-CA transaction, a frame transmission or an acknowledgment procedure (BUSY_TX_ARET), the state change is executed after finishing.

  • Page 48: Configuration

    CSMA-CA retries after a busy channel is detected. The register bits CSMA_SEED (registers 0x2D, 0x2E) define a random seed for the backoff-time random-number generator in the Atmel AT86RF233. The register bits MAX_BE and MIN_BE (register 0x2F, CSMA_BE) set the maximum and minimum CSMA backoff exponent (see [2]), respectively.

  • Page 49: Rx_Aack_On - Receive With Automatic Ack

    7.2.3.2, in that case an IRQ_3 (TRX_END) interrupt is issued, even if the FCS fails. During reception the Atmel AT86RF233 parses bit[5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected.
  • Page 50 FCS valid Slotted Operation == 0 Generate IRQ_3 Generate IRQ_3 (TRX_END) (TRX_END) AACK_ACK_TIME == 0 Wait 2 symbol Wait 12 symbol Wait 2 symbol periods periods periods pin 11 (SLP_TR) rising edge Transmit ACK TRX_STATE = RX_AACK_ON AT86RF233 8351A–MCU Wireless–02/12...
  • Page 51 14-2. All registers mentioned in Table 7-5 are described in Section 7.2.6. The general behavior of the “Atmel AT86RF233 Extended Feature Set”, Chapter settings: o OQPSK_DATA_RATE (PSDU data rate) o OQPSK_SCRAM_EN (Scrambler for 2000kb/s data rate) o SFD_VALUE (alternative SFD value)
  • Page 52 7.2.3.2 Configuration of IEEE Scenarios Normal Device Table 7-6 shows a typical Atmel AT86RF233 RX_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 7-6. Configuration of IEEE 802.15.4 Devices.
  • Page 53 AT86RF233 PAN-Coordinator Table 7-7 shows the Atmel AT86RF233 RX_AACK configuration for a PAN coordinator. Table 7-7. Configuration of a PAN Coordinator. Register Register Register Name Description Address Bits 0x20,0x21 SHORT_ADDR_0/1 Set node addresses. 0x22,0x23 PAN_ADDR_0/1 0x24 IEEE_ADDR_0 … … 0x2B...
  • Page 54 FCF frame version number. If the Atmel AT86RF233 radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, is applied to a received frame. However, an IRQ_3 (TRX_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the reception of a frame with a valid FCS.
  • Page 55 AT86RF233 7.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios Sniffer Table 7-9 shows an Atmel AT86RF233 RX_AACK configuration to setup a sniffer device. Other RX_AACK configuration bits, refer to Table 7-5, should be set to their reset values. All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END).
  • Page 56 An acknowledgment is only send, when the ACK request subfield was set in the received frame and an IRQ_3 (TRX_END) interrupt occurred. 3. AACK_UPLD_RES_FT = 0: Any received frame with a reserved frame type is discarded. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 57 To accept a received frame and to generate an address match interrupt IRQ_5 (AMI) a filtering procedure as described in IEEE 802.15.4-2006 Section 7.5.6.2. (Third level of filtering) is applied to the frame. The Atmel AT86RF233 RX_AACK mode accepts only frames that satisfy all of the following requirements (quote from IEEE 802.15.4-2006, Section 7.5.6.2):...
  • Page 58 AACK_UPLD_RES_FT, Section 7.2.7. Filter rule two is affected by register bits AACK_FVN_MODE, Section 7.2.7. 7.2.3.5 RX_AACK Slotted Operation – Slotted Acknowledgement Atmel AT86RF233 supports slotted acknowledgement operation, refer IEEE 802.15.4-2006, Section 7.5.6.4.2, in conjunction with the microcontroller. In RX_AACK mode with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set, the transmission of an acknowledgement frame has to be controlled by the microcontroller.
  • Page 59 A timing example of an RX_AACK transaction is shown in Figure 7-14. In this example a data frame of length 10 with an ACK request is received. The Atmel AT86RF233 changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception...

  • Page 60: Tx_Aret_On - Transmit With Automatic Frame Retransmission And Csma-Ca Retry

    = frame_rctr + 1 ACK requested Receive ACK until timeout ACK valid frame_rctr > Data Pending MAX_FRAME_RETRIES TRAC_STATUS = TRAC_STATUS = TRAC_STATUS = TRAC_STATUS = NO_ACK SUCCESS_DATA_PENDING SUCCESS CHANNEL_ACCESS_FAILURE Issue IRQ_3 (TRX_END) interrupt TRX_STATE = TX_ARET_ON AT86RF233 8351A–MCU Wireless–02/12...
  • Page 61 Figure 7-15. In TX_ARET mode, the Atmel AT86RF233 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, Section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply.
  • Page 62 Here an example data frame of length 10 with an ACK request is transmitted. After that the Atmel AT86RF233 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register bits TRX_STATUS (register 0x01, TRX_STATUS) signals BUSY_TX_ARET.

  • Page 63: Interrupt Handling

    TRAC_STATUS = SUCCESS_DATA_PENDING if the frame pending subfield of the received ACK frame was set to one. 7.2.5 Interrupt Handling The Atmel AT86RF233 interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to Section 7.1.3.

  • Page 64: Register Summary

    7.2.6 Register Summary The following Atmel AT86RF233 registers are to be configured to control the Extended Operating Mode: Table 7-14. Register Summary. Reg.-Addr. Register Name Description 0x01 TRX_STATUS Radio transceiver status, CCA result 0x02 TRX_STATE Radio transceiver state control, TX_ARET status...
  • Page 65 AT86RF233 Register Bits Value Description 0x09 PLL_ON (TX_ON) 0x0F SLEEP 0x10 PREP_DEEP_SLEEP 0x11 BUSY_RX_AACK 0x12 BUSY_TX_ARET 0x16 RX_AACK_ON 0x19 TX_ARET_ON 0x1F STATE_TRANSITION_IN_PROGRESS All other values are reserved Notes: 1. In SLEEP or DEEP_SLEEP state register not accessible. Extended Operating Mode only.
  • Page 66 A write access to register bits TRX_CMD initiates a radio transceiver state transition. Table 7-17. TRX_CMD. Register Bits Value Description TRX_CMD 0x00 0x02 TX_START 0x03 FORCE_TRX_OFF 0x04 FORCE_PLL_ON 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) AT86RF233 8351A–MCU Wireless–02/12...

  • Page 67: Value Description

    AT86RF233 Register Bits Value Description 0x10 PREP_DEEP_SLEEP 0x16 RX_AACK_ON 0x19 TX_ARET_ON All other values are reserved Notes: 1. TRX_CMD = “0” after power on reset (POR). The frame transmission starts one symbol after TX_START command. FORCE_PLL_ON is not valid for states P_ON, SLEEP, DEEP_SLEEP, and RESET, as well as STATE_TRANSITION_IN_PROGRESS towards these states.
  • Page 68 If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4–2006. Reserved frame types are explained in IEEE 802.15.4 Section 7.2.1.1.1. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 69 AT86RF233  Bit 4 - AACK_UPLD_RES_FT Upload reserved frame types within RX_AACK mode. Table 7-21. AACK_UPLD_RES_FT. Register Bits Value Description AACK_UPLD_RES_FT Upload of reserved frame types is disabled Upload of reserved frame types is enabled Note: If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed.
  • Page 70 Retrieves current CSMA-CA retry counter value. Table 7-25. ARET_CSMA_RETRIES. Register Bits Value Description ARET_CSMA_RETRIES Minimum possible CSMA-CA retry counter value Maximum possible CSMA-CA retry counter value Note: A new CCA_BACKOFF cycle or new frame transmit cycle changed these value. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 71 AT86RF233 Register 0x2C (XAH_CTRL_0): The XAH_CTRL_0 register is a control register for Extended Operating Mode. Figure 7-22. Register XAH_CTRL_0. 0x2C MAX_FRAME_RETRIES XAH_CTRL_0 Read/Write Reset value 0x2C SLOTTED_ MAX_CSMA_RETRIES XAH_CTRL_0 OPERATION Read/Write Reset value  Bit 7:4 - MAX_FRAME_RETRIES Number of retransmission attempts in TX_ARET mode before the transaction gets cancelled.
  • Page 72 This register contains the lower 8-bit of the CSMA_SEED, bits[7:0]. The higher 3-bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that determines the length of the backoff period in the CSMA-CA algorithm. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 73 The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF233. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number.
  • Page 74 If AACK_I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six). AT86RF233 8351A–MCU Wireless–02/12...
  • Page 75 AT86RF233  Bit 2:0 - CSMA_SEED_1 Higher 3-bit of CSMA_SEED, bits[10:8]. Seed for random number generation in the CSMA-CA algorithm. Table 7-34. CSMA_SEED_1. Register Bits Value Description CSMA_SEED_1 These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details.

  • Page 76: Register Description - Address Registers

    Reset value Register 0x22 (PAN_ID_0): This register contains the lower 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[7:0]. Figure 7-28. Register PAN_ID_0. 0x22 PAN_ID_0 PAN_ID_0 Read/Write Reset value 0x22 PAN_ID_0 PAN_ID_0 Read/Write Reset value AT86RF233 8351A–MCU Wireless–02/12...
  • Page 77 AT86RF233 Register 0x23 (PAN_ID_1): This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8]. Figure 7-29. Register PAN_ID_1. 0x23 PAN_ID_1 PAN_ID_1 Read/Write Reset value 0x23 PAN_ID_1 PAN_ID_1 Read/Write Reset value Register 0x24 (IEEE_ADDR_0): This register contains the lower 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[7:0].
  • Page 78 Read/Write Reset value Register 0x28 (IEEE_ADDR_4): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[39:32]. Figure 7-34. Register IEEE_ADDR_4. 0x28 IEEE_ADDR_4 IEEE_ADDR_4 Read/Write Reset value 0x28 IEEE_ADDR_4 IEEE_ADDR_4 Read/Write Reset value AT86RF233 8351A–MCU Wireless–02/12...
  • Page 79 AT86RF233 Register 0x29 (IEEE_ADDR_5): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40]. Figure 7-35. Register IEEE_ADDR_5. 0x29 IEEE_ADDR_5 IEEE_ADDR_5 Read/Write Reset value 0x29 IEEE_ADDR_5 IEEE_ADDR_5 Read/Write Reset value Register 0x2A (IEEE_ADDR_6): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[55:48].

  • Page 80: Functional Description

    On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006 standard declares bit seven of the PHR octet as being reserved, the AT86RF233 preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not considered to be part of the frame length, so only frames between one and 127 octets are possible.

  • Page 81: Mac Protocol Layer Data Unit (Mpdu)

    AT86RF233 8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU) The PSDU has a variable length between zero and aMaxPHYPacketSize (127, maximum PSDU size in octets). The length of the PSDU is signaled by the frame length field (PHR), refer to Table 8-1.
  • Page 82 This subfield is used for address filtering by the third level filter rules. By default, only frame types 0 – 3 pass the third level filter rules, refer to Section 7.2.3.4. Automatic address filtering by the Atmel AT86RF233 is enabled when using the RX_AACK mode, refer to Section 7.2.3.
  • Page 83 AT86RF233 is omitted. In RX_AACK mode, this bit is evaluated by the address filter logic of the Atmel AT86RF233. This subfield was previously named “Intra-PAN”. Bit [11:10]: the “Destination Addressing Mode” subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 8-3, according to IEEE 802.15.4:...
  • Page 84 8.1.2.5 Addressing Fields The addressing fields of the MPDU are used by the Atmel AT86RF233 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID and a device address.

  • Page 85: Frame Check Sequence (Fcs)

    16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2). The Atmel AT86RF233 applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID (register 0x06, PHY_RSSI). On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission.

  • Page 86: Automatic Fcs Generation

    The automatic FCS generation is activated with register bit TX_AUTO_CRC_ON = 1. This allows the Atmel AT86RF233 to compute the FCS autonomously. For a frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer.
  • Page 87 AT86RF233 Figure 8-4. Register TRX_CTRL_1. 0x04 TX_AUTO_CRC_ PA_EXT_EN IRQ_2_EXT_EN RX_BL_CTRL TRX_CTRL_1 Read/Write Reset value 0x04 SPI_CMD_MODE IRQ_MASK_MODE IRQ_POLARITY TRX_CTRL_1 Read/Write Reset value  Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. Table 8-6. TX_AUTO_CRC_ON.

  • Page 88: Received Signal Strength Indicator (Rssi)

    RSSI value in the range of one to 28, the RF input power can be calculated as follows: [dBm] = RSSI + 3 x RSSI BASE_VAL Figure 8-6. Mapping between RSSI Value and Received Input Power. Measured Ideal -100 RSSI AT86RF233 8351A–MCU Wireless–02/12...

  • Page 89: Register Description

    AT86RF233 8.3.4 Register Description Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and an RSSI value. Figure 8-7. Register PHY_RSSI. 0x06 RX_CRC_VALID RND_VALUE RSSI PHY_RSSI Read/Write Reset value 0x06 RSSI...

  • Page 90: Energy Detection (Ed)

    This is important for time critical applications or if interrupt IRQ_2 (RX_START) is not used to indicate the reception of a frame. Note: It is not recommended to manually initiate an ED measurement when using the Extended Operating Mode. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 91: Data Interpretation

    ED_LEVEL value Atmel AT86RF233 has a valid range from 0x00 to 0x53 with a resolution of 1dB. A value of 0xFF indicates the reset value. All other values do not occur. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED_LEVEL value has a maximum tolerance of ±5 dB, this is to be...

  • Page 92: Register Description

    For High Data Rate Modes the automated measurement duration is reduced to 32µs, refer to Section 11.3. For manually initiated ED measurements in these modes the measurement period is still 128µs as long as the receiver is in RX_ON state. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 93: Clear Channel Assessment (Cca)

    The CCA modes are configurable via register 0x08 (PHY_CC_CCA). When being in Basic Operating Mode, an CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the Atmel AT86RF233 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS).

  • Page 94: Data Interpretation

    8.5.3 Data Interpretation The Atmel AT86RF233 current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). Note, register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detected no signal (idle channel) during the measurement cycle, the CCA_STATUS bit is set to one.

  • Page 95: Register Description

    AT86RF233 Table 8-11. CCA Measurement Period and Access in BUSY_RX state. CCA Mode Request within ED measurement Request after ED measurement Energy above threshold. CCA result is available after finishing CCA result is immediately available automated ED measurement period. after request.
  • Page 96 The read value returns always with zero. If a CCA request is initiated in states others than RX_ON or RX_BUSY the PHY generates an IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE, however no CCA was carried out. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 97 AT86RF233 A manual CCA measurement is initiated with setting CCA_REQUEST = 1. The end of the CCA measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE). Register bits CCA_DONE and CCA_STATUS (register 0x01, TRX_STATUS) are updated after a CCA_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1.

  • Page 98: Link Quality Indication (Lqi)

    8.6.1 Overview The LQI measurement of the Atmel AT86RF233 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames.

  • Page 99: Request An Lqi Measurement

    Note: The received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the Atmel AT86RF233 do not characterize the signal quality and the ability to decode a signal. As an example, a received signal with an input power of about 6dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions.

  • Page 100: Module Description

    9 Module Description 9.1 Receiver (RX) 9.1.1 Overview The Atmel AT86RF233 receiver is split into an analog radio front-end and a digital base band processor (RX BBP), see Figure 9-1. Figure 9-1. Receiver Block Diagram. Analog Domain Digital Domain Frame...

  • Page 101: Register Description

    Atmel AT86RF233 Extended Operating Mode requires further register configurations, for details refer to Section 7.2. The AT86RF233 receiver has an outstanding sensitivity performance of -101dBm. At certain environmental conditions or for High Data Rate Modes, refer to Section 11.3, it may be useful to manually decrease this sensitivity.
  • Page 102 If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in all RX listening states is reduced to I = 11.3mA (typ.), refer to Section 12.8. RX_ON_L0 Additional power saving techniques in receive modes are specified in Section 11.10. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 103: Transmitter (Tx)

    AT86RF233 9.2 Transmitter (TX) 9.2.1 Overview The Atmel AT86RF233 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-3. Figure 9-3. Transmitter Block Diagram. µC Ext. RF front-end and Control, Registers...

  • Page 104: Tx Power Ramping

    Read/Write Reset value  Bit 3:0 – TX_PWR The register bits TX_PWR determine the TX output power of the radio transceiver. Table 9-4. TX Output Power. Register Bits Value TX Output Power [dBm] TX_PWR +3.7 +3.4 +2.5 AT86RF233 8351A–MCU Wireless–02/12...
  • Page 105 AT86RF233 1. If the extended operating mode is used with RPC enabled (that is Note: XAH_TX_RPC_EN is set to one), the read value of the TX_PWR field provides the used transmit power for last transmitted frame including acknowledgement frame. The TX_PWR field contains only the value of the RPC-controlled transmission if a frame has already been sent.

  • Page 106: Frame Buffer

    9.3 Frame Buffer The Atmel AT86RF233 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other one to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible.

  • Page 107: User Accessible Frame Content

    SLEEP or DEEP_SLEEP, the Frame Buffer is powered off and the stored data gets lost. 9.3.2 User accessible Frame Content The Atmel AT86RF233 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-6. Figure 9-6. AT86RF233 Frame Structure.
  • Page 108 The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete, which takes 176µs (16µs PA ramp-up + 160µs SHR) from the rising edge of pin 11 (SLP_TR) (see Figure 7-2). AT86RF233 8351A–MCU Wireless–02/12...

  • Page 109: Voltage Regulators (Avreg, Dvreg)

     Configurable for usage of an external voltage regulator 9.4.1 Overview The internal voltage regulators supply a stabilized voltage to the Atmel AT86RF233. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section.

  • Page 110: Register Description

    If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for the digital building blocks. Table 9-7. DVREG_EXT. Register Bits Value Description DVREG_EXT Internal voltage regulator enabled, digital section Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section AT86RF233 8351A–MCU Wireless–02/12...
  • Page 111 AT86RF233  Bit 2 - DVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG_EXT = 1. Table 9-8. DVDD_OK. Register Bits Value Description DVDD_OK Digital voltage regulator is disabled or supply voltage not...

  • Page 112: Battery Monitor (Batmon)

     Current state can be monitored in a register bit 9.5.1 Overview The Atmel AT86RF233 battery monitor (BATMON) detects and indicates a low supply voltage of the external supply voltage at pin 28 (EVDD). This is done by comparing the voltage on the external supply pin 28 (EVDD) with a configurable internal threshold voltage.

  • Page 113: Interrupt Handling

    IRQ_7 (BAT_LOW), see Section 6.7. Note: The Atmel AT86RF233 IRQ_7 (BAT_LOW) interrupt is issued only if BATMON_OK changes from one to zero. No interrupt is generated when:  The battery voltage is under the default 1.8V threshold at power-on (BATMON_OK was never one), or ...
  • Page 114 BATMON_HR = 1 BATMON_HR = 0 2.550 1.70 2.625 1.75 2.700 1.80 2.775 1.85 2.850 1.90 2.925 1.95 3.000 2.00 3.075 2.05 3.150 2.10 3.225 2.15 3.300 2.20 3.375 2.25 3.450 2.30 3.525 2.35 3.600 2.40 3.675 2.45 AT86RF233 8351A–MCU Wireless–02/12...

  • Page 115: Crystal Oscillator (Xosc)

     Configurable clock output (CLKM) 9.6.1 Overview The crystal oscillator generates the reference frequency for the Atmel AT86RF233. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency.

  • Page 116: External Reference Frequency Setup

    [pF] = 0.5 x (CX + C TRIM The Atmel AT86RF233 trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance.

  • Page 117: Register Description

    AT86RF233 register bits CLKM_CTRL (register 0x03, TRX_CTRL_0) immediately affects a glitch free the CLKM clock rate change. Otherwise (CLKM_SHA_SEL = 1) the new clock rate is supplied when leaving the SLEEP state the next time. To reduced power consumption and spurious emissions, it is recommended to turn off the CLKM clock when not in use.
  • Page 118 Internal crystal oscillator enabled and XOSC voltage regulator enabled All other values are reserved For normal operation the default value is set to XTAL_MODE = 0xF after reset. Using an external clock source it is recommended to set XTAL_MODE = 0x5. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 119 AT86RF233  Bit 3:0 - XTAL_TRIM The register bits XTAL_TRIM controls internal capacitance arrays connected to pin 26 (XTAL1) and pin 25 (XTAL2). Table 9-15. XTAL_TRIM. Register Bits Value Description XTAL_TRIM A capacitance value in the range from 0pF to 4.5pF is selectable with a resolution of 0.3pF.

  • Page 120: Frequency Synthesizer (Pll)

     Fast PLL settling to support frequency hopping 9.7.1 Overview The PLL generates the RF frequencies for the Atmel AT86RF233. During receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal.

  • Page 121: Frequency Agility

    Both Atmel AT86RF233 calibration loops can be initiated manually by setting PLL_CF_START = 1 (register 0x1A, PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B, PLL_DCU). To start the calibration the device must be in PLL_ON or RX_ON state.

  • Page 122: Register Description

    2455 0x16 2460 0x17 2465 0x18 2470 0x19 2475 0x1A 2480 All other values are reserved Register 0x13 (CC_CTRL_0): The CC_CTRL_0 register controls the frequency selection, if the selection by CHANNEL (register 0x08, PHY_CC_CCA) is not used. AT86RF233 8351A–MCU Wireless–02/12...
  • Page 123 AT86RF233 Figure 9-16. Register CC_CTRL_0. 0x13 CC_NUMBER CC_CTRL_0 Read/Write Reset value 0x13 CC_NUMBER CC_CTRL_0 Read/Write Reset value  Bit 7:0 - CC_NUMBER Table 9-18. CC_NUMBER. Register Bits Value Description CC_NUMBER 0x00 Alternative frequency selection with 500kHz frequency spacing. CC_BAND = 0x0: Not used.
  • Page 124 Delay cell calibration cycle is finished Initiates delay cell calibration cycle PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after t = 6µs. The register bit is cleared immediately after finishing the PLL_DCU calibration. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 125: Automatic Filter Tuning (Ftn)

    9.8 Automatic Filter Tuning (FTN) 9.8.1 Overview The Atmel AT86RF233 FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter transfer...

  • Page 126: Radio Transceiver Usage

    10 Radio Transceiver Usage This section describes basic procedures to receive and transmit frames using the Atmel AT86RF233. For a detailed programming description refer to reference [7]. 10.1 Frame Receive Procedure A frame reception comprises of two actions: The PHY listens for, receives and demodulates the frame to the Frame Buffer and signalizes the reception to the microcontroller.

  • Page 127: Frame Transmit Procedure

    Figure 10-2 illustrates the Atmel AT86RF233 frame transmit procedure, when writing and transmitting the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by asserting pin 11 (SLP_TR) or writing command TX_START to register bits TRX_CMD (register 0x02, TRX_STATE), while the radio transceiver is in state PLL_ON or TX_ARET_ON.

  • Page 128: At86Rf233 Extended Feature Set

    The security module is based on an AES-128 core according to FIPS197 standard, refer to [6]. The security module works independent of other building blocks of the Atmel AT86RF233, encryption and decryption can be performed in parallel to a frame transmission or reception.

  • Page 129: Security Key Setup

    AES operation. This initial key is used for the next AES run even it cannot be read from AES_KEY. Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The Atmel AT86RF233 provides this functionality as an additional feature. 11.1.4 Security Operation Modes 11.1.4.1 Electronic Code Book (ECB) ECB is the basic operating mode of the security module.
  • Page 130 0x83 ECB, encryption AES start Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF233 SPI access: Configure SPI access a) SRAM write, refer to Section 6.3.3 b) Start address 0x83 Configure AES operation...
  • Page 131 After preparing the AES key and defining the AES operation direction using Atmel AT86RF233 SRAM register bit AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller).

  • Page 132: Data Transfer - Fast Sram Access

    SPI interface. To reduce the overall processing time the Atmel AT86RF233 provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 11-5. Packet Structure – Fast SRAM Access Mode.

  • Page 133: Start Of Security Operation And Status

    AT86RF233 The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94. 11.1.6 Start of Security Operation and Status A security operation is started within one Atmel AT86RF233 SRAM access by appending start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence.
  • Page 134 AES_STATUS).  Bit 7 - AES_REQUEST A write access with AES_REQUEST = 1 initiates the AES operation. Table 11-5. AES_REQUEST. Register Bits Value Description AES_REQUEST Security module, AES core idle A write access starts the AES operation AT86RF233 8351A–MCU Wireless–02/12...
  • Page 135 AT86RF233  Bit 6:4 - AES_MODE This register bit sets the AES operation mode. Table 11-6. AES_MODE. Register Bits Value Description AES_MODE ECB mode KEY mode CBC mode All other values are reserved  Bit 3 - AES_DIR The register bit AES_DIR sets the AES operation direction, either encryption or decryption.

  • Page 136: Random Number Generator

    11.2 Random Number Generator 11.2.1 Overview The Atmel AT86RF233 incorporates a two bit truly random number generator by observation of noise. This random number can be used to:  Generate random seeds for CSMA-CA algorithm Section 7.2  Generate random values for AES key generation Section 11.1...

  • Page 137: High Data Rate Modes

     Support of other features of the Extended Feature Set 11.3.1 Overview The Atmel AT86RF233 also supports alternative data rates, higher than 250kb/s for applications beyond IEEE 802.15.4 compliant networks. The selection of a data rate does not affect the remaining functionality. Thus it is possible to run all features and operating modes of the radio transceiver in various combinations.

  • Page 138: High Data Rate Packet Structure

    11.3.2 High Data Rate Packet Structure In order to allow appropriate frame synchronization, Atmel AT86RF233 higher data rate modulation is restricted to the payload octets only. The SHR and the PHR field are transmitted with the IEEE 802.15.4 compliant data rate of 250kb/s, refer to Section 8.1.1.

  • Page 139: High Data Rate Frame Buffer Access

    Data Rate Modes the active on-air time is significantly reduced. 11.3.3 High Data Rate Frame Buffer Access The Atmel AT86RF233 Frame Buffer access to read or write frames for High Data Rate transmission is similar to the procedure described in Section 6.3.2.
  • Page 140 Scrambler For data rate 2000kb/s, additional chip scrambling is applied per default, in order to mitigate data dependent spectral properties. Scrambling can be disabled if Atmel AT86RF233 register bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is set to zero. Carrier Sense For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may either apply Energy above threshold or Carrier sense (CS) or a combination of both.

  • Page 141: Register Description

    AT86RF233 11.3.6 Register Description Register 0x0C (TRX_CTRL_2): The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver. Figure 11-13. Register TRX_CTRL_2. 0x0C OQPSK_SCRAM_ RX_SAFE_MODE reserved reserved TRX_CTRL_2 Read/Write Reset value 0x0C reserved OQPSK_DATA_RATE TRX_CTRL_2...
  • Page 142  Bit 2 - AACK_ACK_TIME The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode. Table 11-13. AACK_ACK_TIME. Register Bits Value Description AACK_ACK_TIME Acknowledgment time is 12 symbol periods (aTurnaroundTime) Acknowledgment time is two symbol periods AT86RF233 8351A–MCU Wireless–02/12...
  • Page 143 AT86RF233 According IEEE 802.15.4-2006, Section 7.5.6.4.2 transmission acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME.

  • Page 144: Antenna Diversity

    11.4 Antenna Diversity The Antenna Diversity implementation is characterized by:  Improves signal path robustness between nodes  Atmel AT86RF233 self-contained antenna diversity algorithm  Direct register based antenna selection 11.4.1 Overview Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location.

  • Page 145: Antenna Diversity Sensitivity Control

    AT86RF233 If the Atmel AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP or DEEP_SLEEP state.

  • Page 146: Register Description

    PDT_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the hardware. Register 0x0D (ANT_DIV): The ANT_DIV register controls Antenna Diversity. Figure 11-18. Register ANT_DIV. 0x0D ANT_SEL reserved ANT_DIV Read/Write Reset value 0x0D ANT_DIV_EN ANT_EXT_SW_EN ANT_CTRL ANT_DIV Read/Write Reset value AT86RF233 8351A–MCU Wireless–02/12...
  • Page 147 Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to register bits ANT_CTRL if Antenna Diversity algorithm is disabled. If the Atmel AT86RF233 is not in receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP or DEEP_SLEEP state.
  • Page 148 ANT_CTRL Mandatory setting for applications not using Antenna Diversity and if autonomous antenna selection is enabled Antenna 0 DIG1 = L DIG2 = H Antenna 1 DIG1 = H DIG2 = L Same behaviour as value zero AT86RF233 8351A–MCU Wireless–02/12...

  • Page 149: Rx/Tx Indicator

    The control of an external RF front-end is done via digital control pins DIG3/DIG4, enabled with register bit PA_EXT_EN set. If the AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to avoid unintended power consumption of the external RF front-end, especially during SLEEP or DEEP_SLEEP state.

  • Page 150: Register Description

    1. It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP or DEEP_SLEEP state. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 151: Rx And Tx Frame Time Stamping (Tx_Aret)

    11.6 RX and TX Frame Time Stamping (TX_ARET) 11.6.1 Overview An exact timing of received and transmitted frames is signaled by Atmel AT86RF233 pin 10 (DIG2). A valid PHR reception or start of frame transmission is indicated by a DIG2 posedge. The pin remains high during frame reception or transmission. TX Frame Time Stamping is limited to TX_ARET, whereas the RX Frame Time Stamping is available for all receive modes.
  • Page 152 Table 11-21. ARET_TX_TS_EN. Register Bits Value Description ARET_TX_TS_EN TX_ARET time stamping via pin 10 (DIG2) is disabled TX_ARET time stamping via pin 10 (DIG2) is enabled Note: It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1). AT86RF233 8351A–MCU Wireless–02/12...

  • Page 153: Frame Buffer Empty Indicator

    For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF233 Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing.

  • Page 154: Register Description

    6.3, pin 24 (IRQ) indicates to the microcontroller that an access to the Frame Buffer is not possible as long as valid PSDU data are missing. The pin 24 (IRQ) does not indicate any interrupts during this time. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 155: Dynamic Frame Buffer Protection

    11.8 Dynamic Frame Buffer Protection 11.8.1 Overview The Atmel AT86RF233 continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again.

  • Page 156: Alternate Start-Of-Frame Delimiter

    11.9.1 Overview The SFD indicates the end of the SHR and the start of the PSDU field. The octet is used for byte synchronization only and is not included in the Atmel AT86RF233 Frame Buffer. The SFD value can be changed to operate non IEEE 802.15.4 compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to frames with a different...

  • Page 157: Reduced Power Consumption Mode (Rpc)

     Significant power reduction for several operating modes  Self-contained, self-calibrating and adaptive power reduction schemes 11.10.1 Overview Atmel AT86RF233 RPC offers a variety independent techniques and methods to significantly reduce the power consumption. RPC is applicable to several operating modes and transparent to other extended features.
  • Page 158 11.10.2.3 ERD – Extended Receiver Desensitizing Atmel AT86RF233 ERD is activated with register bit PDT_RPC_EN (register TRX_RPC) set to one. Applicable to states: RX, RX_AACK and TX_ARET In combination with RX_PDT_LEVEL settings, the average RX current is further significantly reduced, for details refer to Section 12.8.
  • Page 159 Table 11-25. 11.10.2.5 PAM – PAN Address Match Recognition Atmel AT86RF233 PAM is activated with register bit IPAN_RPC_EN (register TRX_RPC) set to one. Applicable to states: RX_AACK Address match fail indication of the IEEE 802.15.4 frame filtering causes stopping of the receive procedure in two ways: 1.

  • Page 160: Register Summary

    The register bit PDT_RPC_EN controls in combination with the RX_PDT_LEVEL value the reduced sensitivity behaviour under the RPC mode. Table 11-28. PDT_RPC_EN. Register Bits Value Description PDT_RPC_EN The reduced sensitivity RPC mode is disabled The reduced sensitivity RPC mode is enabled AT86RF233 8351A–MCU Wireless–02/12...
  • Page 161 AT86RF233  Bit 3 - PLL_RPC_EN The register bit PLL_RPC_EN controls the extended PLL behaviour within PLL_ON and TX_ARET_ON modes. Table 11-29. PLL_RPC_EN. Register Bits Value Description PLL_RPC_EN The extended PLL behaviour is disabled The extended PLL behaviour is enabled ...

  • Page 162: Electrical Characteristics

    Even if an implementation uses the external 1.8V voltage supply V it is required to connect V DD1.8 Register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to Section 9.4. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 163: Digital Pin Characteristics

    AT86RF233 12.3 Digital Pin Characteristics Test Conditions: T = +25°C (unless otherwise stated). Symbol Parameter Condition Min. Typ. Max. Unit High level input voltage -0.4 Low level input voltage High level output voltage -0.4 Low level output voltage Capacitive load...

  • Page 164: General Rf Specifications

    CHIP Crystal oscillator frequency Reference oscillator Symbol rate deviation PSDU bit rate Reference frequency accuracy for 250kb/s correct functionality 500kb/s 1000kb/s 2000kb/s 20dB bandwidth 20dB Note: A reference frequency accuracy of ±40ppm is required by [1], [2]. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 165: Transmitter Characteristics

    AT86RF233 12.6 Transmitter Characteristics Test Conditions (unless otherwise stated): = 3.0V, f = 2445MHz, T = +25°C, Measurement setup see Figure 5-1. Symbol Parameter Condition Min. Typ. Max. Unit TX Output power Maximum configurable TX output TX_MAX power value Register bit TX_PWR = 0...

  • Page 166: Current Consumption Specifications

    RX_PDT_LEVEL = [0x0] Supply current RX_ON state receiver desensitize 11.3 RX_ON_L0 with active receiver desensitize RX_PDT_LEVEL = [0x1, ..., 0xE, 0xF] with active RPC mode 5.9, ..., receiver desensitize RX_PDT_LEVEL = [0x1, ..., 0x6, 0x7] AT86RF233 8351A–MCU Wireless–02/12...

  • Page 167: Crystal Parameter Requirements

    AT86RF233 Symbol Parameter Condition Min. Typ. Max. Unit with active RPC mode 5.1, ..., receiver desensitize RX_PDT_LEVEL = [0x8] with active RPC mode 5.0, ..., receiver desensitize RX_PDT_LEVEL = [0x9, ..., 0xE, 0xF] Supply current PLL_ON state PLL_ON with active RPC mode µA...

  • Page 168: Typical Characteristics

    13 Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the Atmel AT86RF233. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement...

  • Page 169: Pll_On State

    AT86RF233 Figure 13-2. Current Consumption in TRX_OFF State. 13.1.2 PLL_ON state Figure 13-3. Current Consumption in PLL_ON State. 8351A–MCU Wireless–02/12...

  • Page 170: Rx_On State

    13.1.3 RX_ON state Figure 13-4. Current Consumption in RX_ON State – High Sensitivity. Figure 13-5. Current Consumption in RX_ON State – High Input Level. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 171: Tx_Busy State

    AT86RF233 Figure 13-6. Current Consumption in RX_ON State – Reduced Sensitivity. 13.1.4 TX_BUSY state Figure 13-7. Current Consumption in TX_BUSY State – Minimum Output Power. 8351A–MCU Wireless–02/12...
  • Page 172 Figure 13-8. Current Consumption in TX_BUSY State – Output Power 0dBm. Figure 13-9. Current Consumption in TX_BUSY State – Maximum Output Power. AT86RF233 8351A–MCU Wireless–02/12...

  • Page 173: Sleep

    AT86RF233 13.1.5 SLEEP Figure 13-10. Current Consumption in SLEEP. 13.1.6 DEEP_SLEEP Figure 13-11. Current Consumption in DEEP_SLEEP. 8351A–MCU Wireless–02/12...

  • Page 174: State Transition Timing

    13.2 State Transition Timing Figure 13-12. Transition Time from EVDD to P_ON (CLKM available). Figure 13-13. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)). AT86RF233 8351A–MCU Wireless–02/12...
  • Page 175 AT86RF233 Figure 13-14. Transition Time from TRX_OFF to PLL_ON. 8351A–MCU Wireless–02/12...

  • Page 176: Register Reference

    14 Register Reference The Atmel AT86RF233 provides a register space of 64 8-bit registers used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value.
  • Page 177 AT86RF233 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x29 IEEE_ADDR_5 IEEE_ADDR_5 0x2A IEEE_ADDR_6 IEEE_ADDR_6 0x2B IEEE_ADDR_7 IEEE_ADDR_7 0x2C XAH_CTRL_0 MAX_FRAME_RETRIES MAX_CSMA_RETRIES SLOTTED_OPERATION 0x2D CSMA_SEED_0 CSMA_SEED_0 0x2E CSMA_SEED_1 AACK_FVN_MODE...
  • Page 178 (1, 2, 3) The reset values of the Atmel AT86RF233 registers in state P_ON are shown in Table 14-2. Note: All reset values in Table 14-2 are only valid after a power on reset. After a reset procedure (/RST = L) as described in Section 7.1.4.6, the reset values of...

  • Page 179: Abbreviations

    AT86RF233 15 Abbreviations AACK Automatic acknowledgement Acknowledgement Analog-to-digital converter Antenna diversity Automated gain control Advanced encryption standard ARET Automatic retransmission AVREG Voltage regulator for analog building blocks AWGN Additive White Gaussian Noise BATMON Battery monitor Base band processor Band pass filter...
  • Page 180 SCLK SPI Interface: SPI clock /SEL SPI Interface: SPI select Start-of-frame delimiter Synchronization header Serial peripheral interface SRAM Static random access memory SSBF Single side band filter Transmitter Voltage controlled oscillator VREG Voltage regulator XOSC Crystal oscillator AT86RF233 8351A–MCU Wireless–02/12...

  • Page 181: Ordering Information

    32QN2, 32-lead 5.0x5.0mm Body, 0.50mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. 17 Soldering Information Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C.

  • Page 182: Package Drawing - 32Qn2

    19 Package Drawing – 32QN2 SYMBOL MIN. NOM. MAX. NOTE AT86RF233 8351A–MCU Wireless–02/12...

  • Page 183: Appendix A - Continuous Transmission Test Mode

    Appendix A - Continuous Transmission Test Mode A.1 - Overview The Atmel AT86RF233 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode).

  • Page 184: Step Action

    0x00 Disable Continuous Transmission Test Mode RESET Reset AT86RF233 Notes: Only required for CW mode, do not configure for PRBS mode. Frame Buffer content varies for different modulation schemes. The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode.

  • Page 185: Register Description

    AT86RF233 A.3 – Register Description Register 0x36 (TST_CTRL_DIGI): The TST_CTRL_DIG register enables the continuous transmission test mode. Figure 0-1. Register TST_CTRL_DIGI. 0x36 reserved TST_CTRL_DIGI Read/Write Reset value 0x36 TST_CTRL_DIG TST_CTRL_DIGI Read/Write Reset value  Bit 3:0 - TST_CTRL_DIG The register bits TST_CTRL_DIG with value 0xF enables continuous transmission.

  • Page 186: Appendix B - Errata

    Appendix B - Errata AT86RF233 Rev. A Potential long PLL settling duration In very rare cases a PLL_LOCK interrupt is not generated within the specified maximum t = 250µs PLL lock duration. PLL_INIT Problem Fix/Workaround In such a case perform the following action:...

  • Page 187: References

    ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM). NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001. AT86RF233 Software Programming Model. 8351A–MCU Wireless–02/12...

  • Page 188: Data Sheet Revision History

    Data Sheet Revision History Rev. 8351A–MCU Wireless–02/12 Initial release AT86RF233 8351A–MCU Wireless–02/12...

  • Page 189: Table Of Contents

    AT86RF233 Table of Contents 1 Pin-out Diagram .................. 2 1.1 Pin Descriptions...................... 3 1.2 Analog and RF Pins ....................4 1.2.1 Supply and Ground Pins....................4 1.2.2 RF Pins .......................... 4 1.2.3 Crystal Oscillator Pins ....................5 1.2.4 Analog Pin Summary ..................... 5 1.3 Digital Pins ......................
  • Page 190 9.1.1 Overview ........................100 9.1.2 Frame Receive Procedure ..................100 9.1.3 Configuration ......................100 9.1.4 Register Description ....................101 9.2 Transmitter (TX) ....................103 9.2.1 Overview ........................103 9.2.2 Frame Transmit Procedure ..................103 9.2.3 Configuration ......................103 AT86RF233 8351A–MCU Wireless–02/12...
  • Page 191 10 Radio Transceiver Usage ............. 126 10.1 Frame Receive Procedure ................126 10.2 Frame Transmit Procedure ................127 11 AT86RF233 Extended Feature Set ..........128 11.1 Security Module (AES) ..................128 11.1.1 Overview ......................... 128 11.1.2 Security Module Preparation ................... 128 11.1.3 Security Key Setup ....................
  • Page 192 12.4 Digital Interface Timing Characteristics ............163 12.5 General RF Specifications ................164 12.6 Transmitter Characteristics ................165 12.7 Receiver Characteristics .................. 165 12.8 Current Consumption Specifications ..............166 12.9 Crystal Parameter Requirements ..............167 13 Typical Characteristics ..............168 AT86RF233 8351A–MCU Wireless–02/12...
  • Page 193 A.1 - Overview ......................183 A.2 - Configuration....................183 A.3 – Register Description ..................185 Appendix B - Errata ................186 AT86RF233 Rev. A ....................186 References..................187 Data Sheet Revision History ............. 188 Rev. 8351A–MCU Wireless–02/12 ................188 Table of Contents ................189...
  • Page 194 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL...