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Atmel AT86RF212B Manual

Atmel AT86RF212B Manual

Low power, 700/800/900mhz transceiver for zigbee, ieee 802.15.4, 6lowpan, and ism applications
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Features

• Fully integrated 769 – 935MHz transceiver including:
- Chinese WPAN band from 779 to 787MHz
- European SRD band from 863 to 870MHz
- North American ISM band from 902 to 928MHz
- Japanese band from 915 to 930MHz
• Direct Sequence Spread Spectrum with different modulation and data rates:
- BPSK with 20 and 40kb/s, compliant to IEEE
- O-QPSK with 100 and 250kb/s, compliant to IEEE 802.15.4-2006/2011
- O-QPSK with 250kb/s, compliant to IEEE 802.15.4-2011
- O-QPSK with 200, 400, 500, and 1000kb/s PSDU data rate
• Flexible combination of frequency bands and data rates
• Industry leading link budget:
- Receiver sensitivity up to -110dBm
- Programmable TX output power up to +11dBm
• Ultra-low current consumption:
- SLEEP
= 0.2µA
- TRX_OFF = 450µA
- RX_ON
= 9.2mA
- BUSY_TX = 18.0mA
• Ultra-low supply voltage (1.8V to 3.6V) with internal regulator
• Easy to use interface:
- Registers, frame buffer, and AES accessible through fast SPI
- Clock output with prescaler from radio transceiver
• Radio transceiver features:
- 128-byte FIFO (SRAM) for data buffering
- Fully integrated, fast settling PLL to support Frequency Hopping
- Battery monitor
- Adjustable receiver sensitivity
- Integrated TX/RX switch, LNA, and PLL loop filter
- Automatic VCO and filter calibration
- Integrated 16MHz crystal oscillator
• Special IEEE 802.15.4
- FCS computation and Clear Channel Assessment
- RSSI measurement, Energy Detection and Link Quality Indication
• MAC hardware accelerator:
- Automated acknowledgement and retransmission
- CSMA-CA and Listen Before Talk (LBT)
- Automatic address filtering and automated FCS check
• Extended feature set hardware support:
- AES 128-bit hardware accelerator
- Antenna Diversity
- RX/TX indication for external RF front end control
- True Random Number Generation for security application
• Optimized for low BoM Cost and ease of production:
- Few external components necessary (crystal, capacitors and antenna)
- Excellent ESD robustness
- Industrial temperature range from -40°C to +85°C
• I/O and packages:
- 32-pin Low-Profile QFN Package 5 x 5 x 0.9mm³
- RoHS/Fully Green
• Compliant to IEEE 802.15.4-2003/2006/2011
• Compliant to ETSI EN 300 220-1, and FCC 47 CFR Section 15.247
42002E–MCU Wireless–02/2015
Arrow.com.
Downloaded from
at TX output power +5dBm
™
-2011 hardware support:
®
802.15.4-2003/2006/2011

AT86RF212B

Low Power,

700/800/900MHz
Transceiver for
ZigBee,

IEEE 802.15.4,

6LoWPAN, and
ISM

Applications

AT86RF212B
Rev. 42002E–MCU Wireless–02/2015
1

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Summary of Contents for Atmel AT86RF212B

  • Page 1: Features

    AT86RF212B Features • Fully integrated 769 – 935MHz transceiver including: - Chinese WPAN band from 779 to 787MHz - European SRD band from 863 to 870MHz - North American ISM band from 902 to 928MHz - Japanese band from 915 to 930MHz •...

  • Page 2: Pin-Out Diagram

    1 Pin-out Diagram Figure 1-1. Atmel AT86RF212B Pin-out Diagram. 31 30 29 28 27 26 25 DIG3 exposed paddle DIG4 /SEL AVSS AVSS MOSI DVSS AT86RF212B MISO AVSS SCLK DVSS DVSS /RST CLKM 9 10 11 12 13 14 15 16 Note: The exposed paddle is electrically connected to the die inside the package.

  • Page 3: Pin Descriptions

    AT86RF212B 1.1 Pin Descriptions Table 1-1. Atmel AT86RF212B Pin Description. Pins Name Type Description DIG3 Digital output (Ground) 1. RX/TX Indication, see Section 11.4 2. If disabled, pull-down enabled (AVSS) DIG4 Digital output (Ground) 1. RX/TX Indication (DIG3 inverted), see Section 11.4...

  • Page 4: Analog And Rf Pins

    ® Atmel AT86RF212B radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation. The voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio transceiver state.
  • Page 5 1.2.3 Crystal Oscillator Pins XTAL1, XTAL2 The pin 26 (XTAL1) of Atmel AT86RF212B is the input of the reference oscillator amplifier (XOSC), the pin 25 (XTAL2) is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.7.

  • Page 6: Digital Pins

    1.3 Digital Pins The Atmel AT86RF212B provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI, and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST, and DIG2). The microcontroller interface is described in detail in Chapter Additional digital output signals DIG1, …, DIG4 are provided to control external blocks,...
  • Page 7 AT86RF212B 1.3.3 Register Description Note: Throughout this datasheet, underlined values indicate reset settings. Register 0x03 (TRX_CTRL_0): The TRX_CTRL_0 register controls the driver current of the digital output pads and the CLKM clock rate. Figure 1-3. Register TRX_CTRL_0. 0x03 PAD_IO PAD_IO_CLKM...

  • Page 8: Disclaimer

    • Residential and commercial automation • Health care • Consumer electronics • PC peripherals The AT86RF212B can be operated by using an external microcontroller like Atmel ® microcontrollers. A comprehensive software programming description can be found in reference [11]. AT86RF212B 42002E–MCU Wireless–02/2015...

  • Page 9: General Circuit Description

    AT86RF212B 4 General Circuit Description The Atmel AT86RF212B single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation demodulation including time frequency synchronization, as well as data buffering. A single 128-byte TRX buffer stores receive or transmit data.
  • Page 10 The Atmel AT86RF212B features hardware supported 128-bit security operation. The standalone AES encryption/decryption engine can be accessed in parallel to all PHY operational modes. Configuration of the AT86RF212B, reading and writing of data memory, as well as the AES hardware engine are controlled by the SPI interface and additional control signals.

  • Page 11: Application Schematic

    AT86RF212B 5 Application Schematic 5.1 Basic Application Schematic A basic application schematic of the Atmel AT86RF212B with a single-ended RF 5-1. The 50Ω single-ended RF input is transformed to the connector is shown in Figure 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port.
  • Page 12 Therefore, a low-pass filter (C3, R1) is placed close to the Atmel AT86RF212B CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if pin 17 (CLKM) is not used as a microcontroller clock source.

  • Page 13: Extended Feature Set Application Schematic

    Section 11.6 • Dynamic Frame Buffer Protection Section 11.7 • Alternate Start-Of-Frame Delimiter Section 11.8 An extended feature set application schematic illustrating the use of the AT86RF212B Extended Feature Set, see Chapter 11, is shown in Figure 5-2. Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations.
  • Page 14 The RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using an RX/TX switch (SW1). During transmit, the AT86RF212B TX signal is amplified using an external PA (N1), low pass filtered to suppress spurious harmonics emission, and fed to the antennas via an RF switch (SW2).

  • Page 15: Microcontroller Interface

    DIG2 Microcontrollers with a master SPI such as Atmel AVR family interface directly to the AT86RF212B. The SPI is used for register, Frame Buffer, SRAM, and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller.

  • Page 16: Spi Timing Description

    An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.3. /SEL = L enables the MISO output driver of the Atmel AT86RF212B. The MSB of MISO is valid after t (see Section 12.4) and is updated on each SCLK falling edge.

  • Page 17: Spi Protocol

    The different access modes are described within the following sections. 6.3.1 Register Access Mode Register Access Mode is used to read and write AT86RF212B regsisters (register address from 0x00 up to 0x3F). A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit[7] = 1), a read/write select bit (bit[6]), and a 6-bit register address.
  • Page 18 READ DATA 6.3.2 Frame Buffer Access Mode Frame Buffer Access Mode is used to read and write Atmel AT86RF212B frame buffer. The frame buffer address is always reset to zero and incremented to access PSDU, LQI, ED and RX_STATUS data.
  • Page 19 A successive Frame Buffer read operation starts again with the PHR field. The content of the Atmel AT86RF212B Frame Buffer is overwritten by a new received frame or a Frame Buffer write access.
  • Page 20 7.2.4. 6.3.3 SRAM Access Mode The SRAM access mode is used to read and write Atmel AT86RF212B frame buffer beginning with a specified byte address. It enables to access dedicated buffer data directly from a desired address without a need of incrementing the frame buffer from the top.
  • Page 21 Figure 6-13 Figure 6-14 illustrate an exemplary SPI sequence of an Atmel AT86RF212B SRAM access to read and write a data package of five byte length, respectively. Figure 6-13. Exemplary SPI Sequence – SRAM Read Access of a 5-byte Data Package.

  • Page 22: Radio Transceiver Status Information

    9.4.3. 6.4 Radio Transceiver Status Information Each Atmel AT86RF212B SPI access can return radio transceiver status information which is a first byte transmitted out of MISO output as the serial data is being shifted into MOSI input. Radio transceiver status information (PHY_STATUS) can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1) to return TRX_STATUS, PHY_RSSI or IRQ_STATUS register as shown in below.

  • Page 23: Radio Transceiver Identification

    AT86RF212B 6.5 Radio Transceiver Identification Atmel AT86RF212B can be identified by four registers. One 8-bit register contains a unique part number (PART_NUM) and one register contains the corresponding 8-bit version number (VERSION_NUM). Two additional 8-bit registers contain the JEDEC manufacture ID.
  • Page 24 Value Description MAN_ID_0 0x1F Atmel JEDEC manufacturer ID, bits[7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The higher 16 bits of the ID are not stored in registers.

  • Page 25: Sleep/Wake-Up And Transmit Signal (Slp_Tr)

    SLEEP state The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF212B can be powered down to reduce the overall power consumption. A power-down scenario is shown in Figure 6-20. When the radio transceiver is in TRX_OFF state, the microcontroller forces the AT86RF212B to SLEEP by setting SLP_TR = H.
  • Page 26 RX_ON and RX_AACK_ON states For synchronous systems where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the Atmel AT86RF212B supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON).

  • Page 27: Interrupt Logic

    7.1.3 TX: Indicates the completion of a frame transmission. 7.1.3 IRQ_2 (RX_START) Indicates the start of a PSDU reception; the AT86RF212B state changed to BUSY_RX; 7.1.3 the PHR can be read from Frame Buffer. IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, 9.8.5...
  • Page 28 IRQ_MASK (register 0x0F) (register 0x0E) The Atmel AT86RF212B IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin 24 (IRQ) = H issues an interrupt request. If the “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access, the IRQ pin has an alternative functionality, refer to Section 11.6...
  • Page 29 AT86RF212B 6.7.3 Register Description Register 0x0E (IRQ_MASK): The IRQ_MASK register controls the interrupt signaling via pin 24 (IRQ). Figure 6-24. Register IRQ_MASK. 0x0E IRQ_MASK IRQ_MASK Read/Write Reset value 0x0E IRQ_MASK IRQ_MASK Read/Write Reset value • Bit 7:0 - IRQ_MASK Mask register for interrupts. IRQ_MASK[7] correspondents to IRQ_7 (BAT_LOW).
  • Page 30 The timing of a received frame can be determined by a separate pin 10 (DIG2). If register bit IRQ_2_EXT_EN is set to one, the reception of a PHR field is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). For further details refer to Section 11.5. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 31 AT86RF212B • Bit 1 - IRQ_MASK_MODE The radio transceiver supports polling of interrupt events. Interrupt polling is enabled by setting register bit IRQ_MASK_MODE. Table 6-14. IRQ_MASK_MODE. Register Bits Value Description IRQ_MASK_MODE Interrupt polling is disabled. Masked off IRQ bits will not appear in IRQ_STATUS register.

  • Page 32: Operating Modes

    Atmel AT86RF212B, such as receiving and transmitting frames, the power-on sequence, and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and general ISM band applications; the corresponding radio transceiver states are shown in Figure 7-1.
  • Page 33 (register 0x01, TRX_STATUS). TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS), Atmel AT86RF212B is in a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin 11 (SLP_TR) is a multifunctional pin, refer to Section 6.6.
  • Page 34 DIG3/DIG4 are pulled-down to analog ground, unless their configuration is changed. Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF212B pins to the default operating values: pin 11 (SLP_TR) = L, pin 8 (/RST) = H and pin 23 (/SEL) = H.
  • Page 35 In RX_ON state the receiver is in the RX data polling mode and the PLL frequency synthesizer is locked to its preprogrammed frequency. The Atmel AT86RF212B receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on.
  • Page 36 11 (SLP_TR) occurs. If the AT86RF212B is in the RX_ON_NOCLK state and pin 11 (SLP_TR) is reset to logic low, it enters the RX_ON state and it starts to supply clock on pin 17 (CLKM) again.
  • Page 37 In case the PHR indicates a frame length of zero, the transmission is aborted immediately after the PHR field. After the frame transmission has been completed, the AT86RF212B automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt, and returns into PLL_ON state.
  • Page 38 7.1.3 Interrupt Handling All interrupts provided by the Atmel AT86RF212B (see Table 6-10) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. When being in receive mode, IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match, and IRQ_3 (TRX_END) the completion of the frame reception.
  • Page 39 AT86RF212B 7.1.4 Basic Operating Mode Timing This section depicts Atmel AT86RF212B state transitions and their timing properties. Timing figures are explained in Table 7-1, Table 7-2, and Section 12.4. 7.1.4.1 Power-on Procedure The power-on procedure to P_ON state is shown in Figure 7-3.
  • Page 40 A transmission is initiated either by a rising edge of pin 11 (SLP_TR) or by command TX_START. The PLL settles to the transmit frequency and the PA is enabled. After the duration of t (one symbol period), the Atmel AT86RF212B TR10 AT86RF212B 42002E–MCU Wireless–02/2015...
  • Page 41 If the radio transceiver was in SLEEP state, the XOSC and DVREG are enabled before entering TRX_OFF state. If register bits TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the Atmel AT86RF212B reaches TRX_OFF state, do not try to initiate a further state change while the radio transceiver is in this state. Notes:...
  • Page 42 7.1.4.6 State Transition Timing Summary The Atmel AT86RF212B transition numbers correspond to Figure 7-1 and do not include SPI access time if not otherwise stated. See measurement setup in Figure 5-1. Table 7-1. State Transition Timing. Symbol Parameter Condition Min.
  • Page 43 AT86RF212B Symbol Parameter Condition Min. Typ. Max. Unit states SLEEP, P_ON, RESET, TRX_OFF, and *_NOCLK. The state transition timing is calculated based on the timing of the individual blocks shown in Figure 7-3 Figure 7-7. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations.
  • Page 44 TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state transitions can be initiated by the rising edge of pin 11 (SLP_TR) in the appropriate state. These register bits are used for Basic and Extended Operating Mode, see Section 7.2. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.
  • Page 45 AT86RF212B If the requested state transition has not been completed, the TRX_STATUS returns STATE_TRANSITION_IN_PROGRESS value. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. State transition timings are defined in Table 7-1.

  • Page 46: Extended Operating Mode

    TRAC_STATUS (register 0x02, TRX_STATE), Section 7.2.7. An Atmel AT86RF212B state diagram, including the Extended Operating Mode states, is shown in Figure 7-10. Orange marked states represent the Basic Operating Mode;...
  • Page 47 AT86RF212B Figure 7-10. Extended Operating Mode State Diagram. P_ON SLEEP (Power-on after V (Sleep State) XOSC=ON XOSC=OFF Pull=ON Pull=OFF (from all states) /RST = L TRX_OFF /RST = H FORCE_TRX_OFF (Clock State) RESET (all modes except SLEEP) (all modes except P_ON)
  • Page 48 The RX_AACK Extended Operating Mode is terminated by writing command PLL_ON to the register bits TRX_CMD. If the Atmel AT86RF212B is within a frame receive or acknowledgment procedure (BUSY_RX_AACK), the state change is executed after finishing. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the RX_AACK transaction and switch to TRX_OFF or PLL_ON state respectively.
  • Page 49 CSMA-CA retries after a busy channel is detected. The register bits CSMA_SEED (registers 0x2D, 0x2E) define a random seed for the backoff-time random-number generator in the Atmel AT86RF212B. The register bits MAX_BE and MIN_BE (register 0x2F, CSMA_BE) set the maximum and minimum CSMA backoff exponent (see [2]), respectively.
  • Page 50 7.2.3.2. In this case, an interrupt IRQ_3 (TRX_END) is issued for all frames. During reception AT86RF212B parses bit[5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an acknowledgement (ACK) reply is expected.
  • Page 51 AT86RF212B Figure 7-11. Flow Diagram of RX_AACK. TRX_STATE = RX_AACK_ON Detect SHR TRX_STATE = BUSY_RX_AACK Issue IRQ_2 (RX_START) Scan MHR Promiscuous Mode Reserved Frames Note 1 (Address match, Promiscuous Mode and Reserved Frames) : - A radio transceiver in promiscuous...
  • Page 52 Table 14-2. All registers mentioned in Table 7-5 are described in Section 7.2.6. The general behavior of the “Atmel AT86RF212B Extended Feature Set”, Chapter settings: o SFD_VALUE (alternative SFD value) o ANT_DIV (Antenna Diversity) o RX_PDT_LEVEL (blocking frame reception of lower power signals) are completely independent from RX_AACK mode and can be arbitrarily combined.
  • Page 53 7.2.3.2 Configuration of IEEE Compliant Scenarios Device not operating as a PAN Coordinator Table 7-6 shows a typical Atmel AT86RF212B RX_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 7-6. Configuration of IEEE 802.15.4 Devices.
  • Page 54 PAN Coordinator Table 7-7 shows the Atmel AT86RF212B RX_AACK configuration for a PAN coordinator. Table 7-7. Configuration of a PAN Coordinator. Register Register Register Name Description Address Bits 0x20,0x21 SHORT_ADDR_0/1 Setup Frame Filter, see Section 8.2.1. 0x22,0x23 PAN_ADDR_0/1 0x24 IEEE_ADDR_0 …...
  • Page 55 FCF frame version number. If the Atmel AT86RF212B radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, is applied to a received frame. However, an IRQ_3 (TRX_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the reception of a frame with a valid FCS.
  • Page 56 7.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios Sniffer Table 7-9 shows an Atmel AT86RF212B RX_AACK configuration to setup a sniffer device. Other RX_AACK configuration bits, refer to Table 7-5, should be set to their reset values. All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END).
  • Page 57 In slotted operation mode, the acknowledgment transmission is actually started by pin 11 (SLP_TR). Table 7-12 shows that the Atmel AT86RF212B enables the trigger pin with an appropriate delay. Thus, a transmission cannot be started earlier. Table 7-12. ACK Start Timing for Slotted Operation.
  • Page 58 7.2.3.4 RX_AACK_NOCLK – RX_AACK_ON without CLKM If the AT86RF212B is listening for an incoming frame and the microcontroller is not running an application, the microcontroller can be powered down to decrease the total system power consumption. This special power-down scenario for systems running in...
  • Page 59 Figure 7-13. In this example, a data frame with an ACK request is received. The Atmel AT86RF212B changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by an IRQ_3 (TRX_END) interrupt. The interrupts IRQ_2 (RX_START) and IRQ_5 (AMI) are disabled in this example.
  • Page 60 ACK valid frame_rctr > Data Pending MAX_FRAME_RETRIES TRAC_STATUS = TRAC_STATUS = TRAC_STATUS = TRAC_STATUS = NO_ACK SUCCESS_DATA_PENDING SUCCESS CHANNEL_ACCESS_FAILURE Issue IRQ_3 (TRX_END) interrupt TRX_STATE = TX_ARET_ON AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 61 TX_ARET_ON to register subfield TRX_CMD (register 0x02, TRX_STATE). If a transmission is initiated in TX_ARET mode, the Atmel AT86RF212B executes the CSMA-CA algorithm as defined by IEEE 802.15.4-2006, Section 7.5.1.4. If the CCA reports IDLE, the frame is transmitted from the Frame Buffer.
  • Page 62 7.2.4.1 Acknowledgment Timeout If an acknowledgment (ACK) frame is expected following the frame transmission, the Atmel AT86RF212B sets a timeout for the ACK frame to arrive. This timeout macAckWaitDuration is defined according to [2] as follows: macAckWaitDuration [symbol periods] =...
  • Page 63 CCA measurement period. If CCA returns IDLE (assumed here), the frame is transmitted. Upon frame transmission Atmel AT86RF212B switches to the receive mode and expects an acknowledgement response. This is indicated by register subfield TRAC_STATUS (register 0x02, TRX_STATE) set to SUCCESS_WAIT_FOR_ACK.
  • Page 64 7.2.5 Interrupt Handling The Atmel AT86RF212B interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to Section 7.1.3. Interrupts can be enabled by setting the appropriate bit in register 0x0E (IRQ_MASK). For RX_AACK and TX_ARET modes the following interrupts inform about the status of a frame reception and transmission: Table 7-14.
  • Page 65 AT86RF212B 7.2.6 Register Summary The following Atmel AT86RF212B registers are to be configured to control the Extended Operating Mode: Table 7-15. Register Summary. Reg.-Addr. Register Name Description 0x01 TRX_STATUS Radio transceiver status, CCA result 0x02 TRX_STATE Radio transceiver state control, TX_ARET status...
  • Page 66 TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Figure 7-17. Register TRX_STATE. 0x02 TRAC_STATUS TRX_CMD TRX_STATE Read/Write Reset value 0x02 TRX_CMD TRX_STATE Read/Write Reset value AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 67 AT86RF212B • Bit 7:5 – TRAC_STATUS Table 7-17. TRAC_STATUS. Register Bits Value Description RX_AACK TX_ARET TRAC_STATUS SUCCESS SUCCESS_DATA_PENDING SUCCESS_WAIT_FOR_ACK CHANNEL_ACCESS_FAILURE NO_ACK INVALID All other values are reserved Note: Even though the reset value for register bits TRAC_STATUS is zero, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when they are started.
  • Page 68 Automatic FCS generation is disabled Automatic FCS generation is enabled Note: The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes. For further details refer to Section 8.3. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 69 AT86RF212B Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for Extended Operating Mode. Figure 7-19. Register XAH_CTRL_1. 0x17 AACK_FLTR_RES_ AACK_UPLD_RES_ reserved CSMA_LBT_MODE XAH_CTRL_1 Read/Write Reset value 0x17 AACK_PROM_ reserved AACK_ACK_TIME reserved XAH_CTRL_1 MODE Read/Write Reset value • Bit 5 - AACK_FLTR_RES_FT Filter reserved frame types like data frame type.
  • Page 70 In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode instead. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.
  • Page 71 AT86RF212B Register 0x2C (XAH_CTRL_0): The XAH_CTRL_0 register is a control register for Extended Operating Mode. Figure 7-20. Register XAH_CTRL_0. 0x2C MAX_FRAME_RETRIES XAH_CTRL_0 Read/Write Reset value 0x2C SLOTTED_ MAX_CSMA_RETRIES XAH_CTRL_0 OPERATION Read/Write Reset value • Bit 7:4 - MAX_FRAME_RETRIES Number of retransmission attempts in TX_ARET mode before the transaction gets cancelled.
  • Page 72 If this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using the rising edge of pin 11 (SLP_TR). This waiting state is signaled in register bits TRAC_STATUS (register 0x02, TRX_STATE) with value SUCCESS_WAIT_FOR_ACK. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.
  • Page 73 AT86RF212B Register 0x2D (CSMA_SEED_0): The register CSMA_SEED_0 contains the lower 8-bit of CSMA_SEED. Figure 7-21. Register CSMA_SEED_0. 0x2D CSMA_SEED_0 CSMA_SEED_0 Read/Write Reset value 0x2D CSMA_SEED_0 CSMA_SEED_0 Read/Write Reset value • Bit 7:0 - CSMA_SEED_0 Lower 8-bit of CSMA_SEED, bits[7:0]. Used as seed for random number generation in the CSMA-CA algorithm.
  • Page 74 The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF212B. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number.
  • Page 75 AT86RF212B In addition, if register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) are configured to accept frames with a frame version other than zero or one, the content of register bit AACK_SET_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of two or three that have the security enabled subfield set to one.
  • Page 76 Register bits MIN_BE defines the minimum backoff exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA backoff. Valid values are [MAX_BE, (MAX_BE – 1), …, 0x0]. For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com.

  • Page 77: Functional Description

    On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006 standard declares bit seven of the PHR octet as being reserved, the AT86RF212B preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not considered to be a part of the frame length, so only frames between one and 127 octets are possible.
  • Page 78 O-QPSK 10.16 4.064 O-QPSK 5.08 2.54 2.032 1000 1.016 Notes: Compliant to IEEE 802.15.4 2006 [2]. High Data Rate Modes, see Section 9.1.4. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 79 AT86RF212B 8.1.2 MAC Protocol Data Unit (MPDU) Figure 8-2 shows the frame structure of the MAC layer. Figure 8-2. IEEE 802.15.4-2006 Frame Format – MAC Layer Frame Structure (MPDU). MAC Protocol Data Unit (MPDU) Sequence Addressing Fields MAC Payload Number...
  • Page 80 0 – 3 pass the third level filter rules, refer to Section 8.2. Automatic frame filtering by the Atmel AT86RF212B is enabled when using the RX_AACK mode, refer to Section 7.2.3. However, a reserved frame (frame type value > 3) can be received if register bit...
  • Page 81 “Destination Addressing Mode”, see Table 8-4. The addressing field description bits of the FCF (Bits 0–2, 3, 6, 10–15) affect the Atmel AT86RF212B Frame Filter, see Section 8.2. 8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator...
  • Page 82 8.1.2.5 Addressing Fields The addressing fields of the MPDU are used by the Atmel AT86RF212B for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID and a device address.

  • Page 83: Frame Filter

    IRQ_5 (AMI). The Atmel AT86RF212B Frame Filter passes only frames that satisfy all of the following requirements/rules (quote from IEEE 802.15.4-2006, Section 7.5.6.2): 1.
  • Page 84 Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address filtering is applied on those frames. An IRQ_5 (AMI) interrupt is never generated and the acknowledgment subfield is ignored. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.
  • Page 85 AT86RF212B 2. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 1: If AACK_FLT_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. This implies the generation IRQ_5 (AMI)
  • Page 86 In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode instead. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.
  • Page 87 The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF212B. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number.
  • Page 88 This register contains the higher 8-bit of the MAC short address for Frame Filter address recognition, bits[15:8]. Figure 8-7. Register SHORT_ADDR_1. 0x21 SHORT_ADDR_1 SHORT_ADDR_1 Read/Write Reset value 0x21 SHORT_ADDR_1 SHORT_ADDR_1 Read/Write Reset value AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 89 AT86RF212B Register 0x22 (PAN_ID_0): This register contains the lower 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[7:0]. Figure 8-8. Register PAN_ID_0. 0x22 PAN_ID_0 PAN_ID_0 Read/Write Reset value 0x22 PAN_ID_0 PAN_ID_0 Read/Write Reset value Register 0x23 (PAN_ID_1): This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8].
  • Page 90 This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[31:24]. Figure 8-13. Register IEEE_ADDR_3. 0x27 IEEE_ADDR_3 IEEE_ADDR_3 Read/Write Reset value 0x27 IEEE_ADDR_3 IEEE_ADDR_3 Read/Write Reset value AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 91 AT86RF212B Register 0x28 (IEEE_ADDR_4): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[39:32]. Figure 8-14. Register IEEE_ADDR_4. 0x28 IEEE_ADDR_4 IEEE_ADDR_4 Read/Write Reset value 0x28 IEEE_ADDR_4 IEEE_ADDR_4 Read/Write Reset value Register 0x29 (IEEE_ADDR_5): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40].
  • Page 92 This register contains the higher 8-bit of the MAC IEEE Frame Filter address for address recognition, bits[63:56]. Figure 8-17. Register IEEE_ADDR_7. 0x2B IEEE_ADDR_7 IEEE_ADDR_7 Read/Write Reset value 0x2B IEEE_ADDR_7 IEEE_ADDR_7 Read/Write Reset value AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 93: Frame Check Sequence (Fcs)

    16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2). The Atmel AT86RF212B applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID (register 0x06, PHY_RSSI). On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission.
  • Page 94 The automatic FCS generation is enabled with register bit TX_AUTO_CRC_ON = 1. This allows the Atmel AT86RF212B to compute the FCS autonomously. For a frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer.
  • Page 95 AT86RF212B • Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. Table 8-13. TX_AUTO_CRC_ON. Register Bits Value Description TX_AUTO_CRC_ON Automatic FCS generation is disabled Automatic FCS generation is enabled Note: The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes.

  • Page 96: Received Signal Strength Indicator (Rssi)

    BASE_VAL BPSK with 300kchip/s -100 BPSK with 600kchip/s O-QPSK with 400kchip/s, SIN and RC-0.2 shaping O-QPSK with 400kchip/s, RC-0.2 shaping O-QPSK with 1000kchip/s, SIN shaping O-QPSK with 1000kchip/s, RC-0.8 shaping AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 97 AT86RF212B Figure 8-20. Mapping between RSSI Value and Receiver Input Power. BPSK with 300 kchip/s BPSK with 600 kchip/s O-QPSK with 400 kchip/s O-QPSK with 1000 kchip/s (SIN) -100 Receiver Input Power [dBm] 8.4.4 Register Description Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI value.

  • Page 98: Energy Detection (Ed)

    8.5 Energy Detection (ED) The Atmel AT86RF212B Energy Detection (ED) module is characterized by • 85 unique energy levels defined • 1dB resolution • A measurement time of eight symbol periods for IEEE 802.15.4 compliant data rates 8.5.1 Overview The receiver ED measurement (ED scan procedure) can be used as a part of a channel selection algorithm.
  • Page 99 ED_LEVEL value Atmel AT86RF212B has a valid range from 0x00 to 0x54 with a resolution of 1.03dB. Values 0x55 to 0xFE do not occur and a value of 0xFF indicates the reset value. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED_LEVEL value has a maximum tolerance of ±6dB, this is to be...
  • Page 100 The measured ED value has a valid range from 0x00 to 0x54 (zero to 84). The value 0xFF signals that no measurement has been started yet (reset value). A manual ED measurement can be initiated by a write access to the register. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com.

  • Page 101: Clear Channel Assessment (Cca)

    The CCA modes are configurable via register 0x08 (PHY_CC_CCA). When in Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the Atmel AT86RF212B is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS).
  • Page 102 CCA_ED_THRES When using the “carrier sense” algorithm (that is CCA_MODE = 0, 2, and 3), the AT86RF212B reports a busy channel upon detection of a PHY mode specific IEEE 802.15.4 signal above RSSI (see Table 8-16).
  • Page 103 AT86RF212B Table 8-20. CCA Measurement Period and Access in BUSY_RX State. CCA Mode Request within ED measurement Request after ED measurement Energy above threshold. CCA result is available after finishing CCA result is immediately available automated ED measurement period. after request.
  • Page 104 CCA measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE). Register bits CCA_DONE and CCA_STATUS (register 0x01, TRX_STATUS) are updated after a CCA_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.
  • Page 105 AT86RF212B • Bit 6:5 - CCA_MODE The CCA mode can be selected using register bits CCA_MODE. Table 8-24. CCA_MODE. Register Bits Value Description CCA_MODE Mode 3a, Carrier sense OR energy above threshold Mode 1, Energy above threshold Mode 2, Carrier sense only Mode 3b, Carrier sense AND energy above threshold Notes: 1.
  • Page 106 P_THRES [dBm] = RSSI_BASE_VAL[dBm] + 2.07[dB] x CCA_ED_THRES. CCA modes 0 and 3 are logically related to this result. Note: If CSMA_LBT_MODE is enabled, CCA_ED_THRES is used for the LBT measurement. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 107: Listen Before Talk (Lbt)

    8.7 Listen Before Talk (LBT) 8.7.1 Overview Equipment using the Atmel AT86RF212B shall conform to the established regulations. With respect to the regulations in Europe, CSMA-CA based transmission according to IEEE 802.15.4 is not appropriate. In principle, transmission is subject to low duty cycles (0.1% to 1%).
  • Page 108 The CCA_THRES register sets the CS and ED threshold level for CCA. Figure 8-28. Register CCA_THRES. 0x09 CCA_CS_THRES CCA_THRES Read/Write Reset value 0x09 CCA_ED_THRES CCA_THRES Read/Write Reset value AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 109 AT86RF212B • Bit 3:0 - CCA_ED_THRES An ED value above the threshold signals the channel as busy during a CCA_ED measurement. Table 8-28. CCA_ED_THRES. Register Bits Value Description CCA_ED_THRES For CCA_MODE = 1, a busy channel is indicated if the measured received power is above P_THRES [dBm] = RSSI_BASE_VAL[dBm] + 2.07[dB] x CCA_ED_THRES.

  • Page 110: Link Quality Indication (Lqi)

    (ED) can be used to evaluate the signal strength and the link margin. The received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the Atmel AT86RF212B do not characterize the signal quality and the ability to decode a signal.

  • Page 111: Module Description

    Table 9-1. The AT86RF212B is fully compliant to the IEEE 802.15.4 low data rate modes of 20kb/s or 40kb/s, employing binary phase-shift keying (BPSK) and spreading with a fixed chip rate of 300kchip/s or 600kchip/s, respectively. The symbol rate is 20ksymbol/s or 40ksymbol/s, respectively.
  • Page 112 • Reduced ACK timing (optional) 9.1.4.1 Overview The Atmel AT86RF212B supports alternative data rates of 200, 400, 500, and 1000kb/s for applications not necessarily targeting IEEE 802.15.4 compliant networks. The High Data Rate Modes utilize the same RF channel bandwidth as the IEEE 802.15.4-2006 sub-1GHz O-QPSK modes.
  • Page 113 9.1.4.2 High Data Rate Frame Structure In order to allow robust frame synchronization, the Atmel AT86RF212B high data rate modulation is restricted to the PSDU part only. The PPDU header (the preamble, the SFD, and the PHR field) are transmitted with a rate of either 100kb/s or 250kb/s (basic...
  • Page 114 (PSDU) cause a different sensitivity between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level set, the Atmel AT86RF212B does not synchronize to frames with an RSSI level below that threshold. Refer to Section 9.2.4...
  • Page 115 AT86RF212B 9.1.5 Register Description Register 0x0C (TRX_CTRL_2): The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver. Figure 9-4. Register TRX_CTRL_2. 0x0C TRX_OFF_AVDD_ OQPSK_SCRAM_ RX_SAFE_MODE ALT_SPECTRUM TRX_CTRL_2 Read/Write Reset value 0x0C BPSK_OQPSK SUB_MODE OQPSK_DATA_RATE...
  • Page 116 The modulation BPSK-40 and modulation BPSK-40-ALT are interoperable together, with some performance degenerations. During reception, this bit is not evaluated within the Atmel AT86RF212B, so it is not explicitly required to align different transceivers with ALT_SPECTRUM in order to assure interoperability. It is very likely that this also holds for any IEEE 802.15.4-2006 compliant O-QPSK transceiver in the 915MHz band, since...
  • Page 117 AT86RF212B The Atmel AT86RF212B supports two different modes with an PSDU data rate of 500kb/s. Using OQPSK_DATA_RATE = 3 might be beneficial when using an external power amplifier and targeting high output power according to FCC 15.247 [5]. Table 9-8 all PHY modes supported by the AT86RF212B are summarized with the relevant setting for each bit of register TRX_CTRL_2.

  • Page 118: Receiver (Rx)

    9.2 Receiver (RX) 9.2.1 Overview The Atmel AT86RF212B transceiver is split into an analog radio front-end and a digital domain, see Figure 4-1. Referring to the receiver part of the analog domain, the differential RF signal is amplified by a low noise amplifier (LNA) and split into quadrature signals by a poly-phase filter (PPF).
  • Page 119 The synchronization to the potential new frame starts if the interference level does not allow for a reliable detection. The Atmel AT86RF212B receiver has an outstanding sensitivity performance. At certain environmental conditions or for High Data Rate Modes, refer to Section 9.1.4, it may be...
  • Page 120 If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in all RX listening states is reduced by 500µA, refer to parameter I Section 12.8. RX_ON AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 121: Transmitter (Tx)

    10.2. 9.3.3 Spectrum Masks The AT86RF212B can be operated in different frequency bands, using different power levels, modulation schemes, chip rates, and pulse shaping filters. The occupied bandwidth of the transmit signal depends on the chosen mode of operation. Values...
  • Page 122 Table 9-12. The spectra were captured using default settings of Atmel AT86RF212B. The resolution bandwidth of the spectrum analyzer was set to 30kHz; the video bandwidth was set to 10kHz. For the OQPSK-SIN-250 modulation and OQPSK-RC-250 modulation the resolution bandwidth of the spectrum analyzer was set to 100kHz;...
  • Page 123 AT86RF212B Figure 9-7. Spectrum of BPSK-40. Frequency [MHz] Figure 9-8. Spectrum of BPSK-40-ALT. Frequency [MHz] 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 124 Figure 9-9. Spectrum of OQPSK-SIN-RC-100. Frequency [MHz] Figure 9-10. Spectrum of OQPSK-RC-100. Frequency [MHz] AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 125 AT86RF212B Figure 9-11. Spectrum of OQPSK-SIN-250. Frequency [MHz] Figure 9-12. Spectrum of OQPSK-RC-250. Frequency [MHz] 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 126 Figure 9-12 illustrate typical spectra of the transmitted signals of the Atmel AT86RF212B and do not claim any limits. Refer to the local authority bodies (FCC, ETSI, etc.) for further details about definition of power spectral density masks, definition of spurious emission, allowed modulation bandwidth, transmit power, and its limits.
  • Page 127 AT86RF212B 9.3.6 Register Description Register 0x05 (PHY_TX_PWR): The PHY_TX_PWR register controls the output power of the transmitter. Figure 9-14. Register PHY_TX_PWR. 0x05 PA_BOOST GC_PA TX_PWR PHY_TX_PWR Read/Write Reset value 0x05 TX_PWR PHY_TX_PWR Read/Write Reset value • Bit 7 - PA_BOOST The register bit PA_BOOST increases transmit gain by 5dB.
  • Page 128 0xCC 0xCD 0x02 0xCD 0xCE 0x03 0xAD 0xCF 0x04 0x47 0xAF 0x27 0x48 0x26 0x05 0x49 0x27 0x07 0x29 AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 129 AT86RF212B PHY_TX_PWR (register 0x05) 0x28 0x08 0x90 0x29 0x91 0x91 0x09 0x93 0x07 0x0B 0x94 0x08 0x0C 0x2F 0x09 0x0D 0x30 0x0A 0x0E 0x31 0x0B 0x0F 0x0F 0x0C 0x10 0x10 0x0D 0x11 0x11 0x0E 0x12 0x12 0x0F 0x13 0x13 0x10...
  • Page 130 It can be used to compensate differences of the average TX power depending of the modulation format, see Table 9-18. Table 9-18. Mode-dependent setting of GC_TX_OFFS. Mode BPSK O-QPSK GC_TX_OFFS Exception for OQPSK-RC-{100,200,400}, see Table 9-15. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 131 AT86RF212B Figure 9-16 shows supply currents for O-QPSK modulation based on Table 9-15. Figure 9-16. Supply Currents for O-QPSK Modulation depending on TX Power Setting (according to Table 9-15). 26.0 24.0 22.0 20.0 18.0 16.0 14.0 North America 12.0 China 10.0...

  • Page 132: Frame Buffer

    9.4 Frame Buffer The Atmel AT86RF212B contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other one to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible.
  • Page 133 AT86RF212B 9.4.2 User accessible Frame Content The Atmel AT86RF212B supports an IEEE 802.15.4 compliant frame format as shown Figure 9-17. Figure 9-17. AT86RF212B Frame Structure. Length [octets] n + 3 n + 5 n + 6 n + 7 n + 8...
  • Page 134 When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.

  • Page 135: Voltage Regulators (Avreg, Dvreg)

    AVDD/DVDD pin 9.5.1 Overview The internal voltage regulators supply a stabilized voltage to the Atmel AT86RF212B. The AVREG provides the regulated 1.8V supply voltage for the analog domain and the DVREG supplies the 1.8V supply voltage for the digital domain.
  • Page 136 The block “Low power voltage regulator” within the “Digital voltage regulator” maintains the DVDD supply voltage at 1.5V (typical) when the Atmel AT86RF212B voltage regulator is disabled in sleep mode. All configuration register values are stored. The low power voltage regulator is always enabled. Therefore, its bias current contributes to the leakage current in sleep mode with about 100nA (typical).
  • Page 137 AT86RF212B • Bit 7 - AVREG_EXT If set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for the analog building blocks. Table 9-19. AVREG_EXT. Register Bits Value Description AVREG_EXT Internal voltage regulator enabled, analog section Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the analog section...
  • Page 138 This provides for a faster RX or TX turn-on time. It is especially useful when a short stopover is made in TRX_OFF state. The recharge time for capacitances is avoided in this case. The current consumption increases by 100µA (typical). AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.

  • Page 139: Battery Monitor (Batmon)

    • Continuous BATMON status monitor as a register flag 9.6.1 Overview The Atmel AT86RF212B battery monitor (BATMON) detects and flags a low external supply voltage level. provided on pin 28 (EVDD). The external voltage supply pin 28 (EVDD) is continuosly compared with the internal threshold voltage to detect a low voltage supply level.
  • Page 140 IRQ_7 (BAT_LOW), see Section 6.7. Note: The Atmel AT86RF212B IRQ_7 (BAT_LOW) interrupt is issued only if BATMON_OK changes from one to zero. IRQ_7 (BAT_LOW) interrupt is not generated under following conditions: • The battery voltage remained below 1.8V threshold value on power-on (BATMON_OK was never one), or •...
  • Page 141 AT86RF212B • Bit 4 - BATMON_HR The register bit BATMON_HR sets the range and resolution of the battery monitor. Table 9-25. BATMON_HR. Register Bits Value Description BATMON_HR Enables the low range, see BATMON_VTH Enables the high range, see BATMON_VTH • Bit 3:0 – BATMON_VTH The threshold values for the battery monitor are set by register bits BATMON_VTH.

  • Page 142: Crystal Oscillator (Xosc) And Clock Output (Clkm)

    • Configurable clock output (CLKM) 9.7.1 Overview The crystal oscillator generates the reference frequency for the Atmel AT86RF212B. All other internally generated frequencies of the radio transceiver are derived from this frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency.
  • Page 143 [pF] + C [pF]). TRIM The Atmel AT86RF212B trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of decreases with increasing crystal load capacitor values.
  • Page 144 AT86RF212B provides such a clock jitter as an optional feature. The jitter module is working for the receiver part and all I/O signals, for example CLKM if enabled. The transmitter part and RF frequency generation are not influenced.
  • Page 145 AT86RF212B • Bit 5:4 - PAD_IO_CLKM These register bits set the output driver current of pin CLKM. It is recommended to reduce the driver strength to 2mA (PAD_IO_CLKM = 0) if possible. This reduces power consumption and spurious emissions. Table 9-27. PAD_IO_CLKM.
  • Page 146 Table 9-31. JCM_EN. Register Bits Value Description JCM_EN Digital clock jitter module is disabled Digital clock jitter module is enabled Note: JCM_EN will be always disabled within transmitting and filter tuning. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 147 AT86RF212B Register 0x12 (XOSC_CTRL): The XOSC_CTRL register controls the operation of the crystal oscillator. Figure 9-28. Register XOSC_CTRL. 0x12 XTAL_MODE XOSC_CTRL Read/Write Reset value 0x12 XTAL_TRIM XOSC_CTRL Read/Write Reset value • Bit 7:4 - XTAL_MODE The register bits XTAL_MODE set the operating mode of the crystal oscillator.

  • Page 148: Frequency Synthesizer (Pll)

    • Fast PLL settling to support frequency hopping 9.8.1 Overview The PLL generates the RF frequencies for the Atmel AT86RF212B. During receive and transmit operations, the frequency synthesizer operates as a local oscillator. The frequency synthesizer is implemented as a fractional-N PLL with analog compensation of the fractional phase error.
  • Page 149 Both Atmel AT86RF212B calibration loops can be initiated manually by SPI command. To start the calibration, the device should be in state PLL_ON. The center frequency 42002E–MCU Wireless–02/2015...
  • Page 150 PLL_ON. During BUSY_RX and BUSY_RX_AACK, the transceiver returns to state RX_ON and RX_AACK_ON, respectively, once the PLL has locked. Notes: An Atmel AT86RF212B interrupt IRQ_0 (PLL_LOCK) clears any preceding IRQ_1 (PLL_UNLOCK) interrupt automatically and vice versa. state transition...
  • Page 151 AT86RF212B 9.8.6 Register Description Register 0x08 (PHY_CC_CCA): The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Figure 9-29. Register PHY_CC_CCA. 0x08 CCA_REQUEST CCA_MODE CHANNEL PHY_CC_CCA Read/Write Reset value 0x08 CHANNEL...
  • Page 152 CC_BAND = 0x3: Valid values are [0xFF, 0xFE, …,0x00] CC_BAND = 0x4: Valid values are [0x5E, 0x5D, …,0x00] CC_BAND = 0x5: Valid values are [0x66, 0x65, …,0x00] CC_BAND = 0x6: Valid values are [0xFF, 0xFE, …,0x00] All other values are reserved AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com.
  • Page 153 AT86RF212B Register 0x14 (CC_CTRL_1): The CC_CTRL_1 register controls the selection of the frequency bands. Figure 9-31. Register CC_CTRL_1. 0x14 reserved CC_CTRL_1 Read/Write Reset value 0x14 reserved CC_BAND CC_CTRL_1 Read/Write Reset value • Bit 2:0 - CC_BAND The register bits CC_BAND control the selection for IEEE 802.15.4 channel band and additional frequencies bands.
  • Page 154 Initiates delay cell calibration cycle PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after t = 10µs. The register bit is cleared immediately after finishing the PLL_DCU calibration. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 155 AT86RF212B Register 0x11 (BATMON): The BATMON register configures the battery monitor to compare the supply voltage at pin 28 (EVDD) to the threshold. Additionally, the supply voltage status at pin 28 (EVDD) can be read from register bit BATMON_OK according to the actual BATMON settings.

  • Page 156: Automatic Filter Tuning (Ftn)

    PLL_ON or RX_ON. This applies in particular for the High Data Rate Modes with a much higher sensitivity against BPF transfer function variations. The recommended calibration interval is five minutes or less, if the AT86RF212B operates always in an active state (PLL_ON, TX_ARET_ON, RX_ON, and RX_AACK_ON).

  • Page 157: Radio Transceiver Usage

    10 Radio Transceiver Usage This section describes basic procedures to receive and transmit frames using the Atmel AT86RF212B. For a detailed programming description refer to reference [11]. 10.1 Frame Receive Procedure A frame reception comprises of two actions: The transceiver listens for, receives, and demodulates the frame to the Frame Buffer and signals the reception to the microcontroller.

  • Page 158: Frame Transmit Procedure

    Both actions can be run in parallel if required by critical protocol timing. Figure 10-2 illustrates the Atmel AT86RF212B frame transmit procedure, when writing and transmitting the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by asserting pin 11 (SLP_TR) or writing command TX_START to register bits TRX_CMD (register 0x02, TRX_STATE).

  • Page 159: At86Rf212B Extended Feature Set

    The security module is based on an AES-128 core according to FIPS197 standard, refer to [10]. The security module works independently of other building blocks of the Atmel AT86RF212B. Encryption and decryption can be performed in parallel with a frame transmission or reception.
  • Page 160 AES_KEY. Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The Atmel AT86RF212B provides this functionality as an additional feature. 11.1.4 Security Operation Modes 11.1.4.1 Electronic Code Book (ECB) ECB is the basic operating mode of the security module.
  • Page 161 SRAM write 0x83 ECB, encryption AES start Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF212B SPI access: 1. Configure SPI access a) SRAM write, refer to Section 6.3.3 b) Start address 0x83 2.
  • Page 162 After preparing the AES key and defining the AES operation direction using Atmel AT86RF212B SRAM register bit AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller).
  • Page 163 SPI interface. To reduce the overall processing time, the AT86RF212B provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 11-5. Packet Structure – Fast SRAM Access Mode.
  • Page 164 The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94. 11.1.6 Start of Security Operation and Status A security operation is started within one Atmel AT86RF212B SRAM access by appending start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence.
  • Page 165 AT86RF212B • Bit 7 - AES_ER This SRAM register bit indicates an error of the AES module. An error may occur for instance after an access to SRAM register 0x83 (AES_CTRL) while an AES operation is running or after reading less than 128-bits from SRAM register space 0x84 – 0x93 (AES_STATE).
  • Page 166 Register 0x94 is a mirrored version of register 0x83 (AES_CTRL), for details refer to register 0x83 (AES_CTRL). This register could be used to start a security operation within a single SRAM access by appending it to the data stream and setting register bit AES_REQUEST = 1. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.

  • Page 167: Random Number Generator

    AT86RF212B 11.2 Random Number Generator 11.2.1 Overview The Atmel AT86RF212B incorporates a two bit truly random number generator by observation of noise. This random number can be used to: • Generate random seeds for CSMA-CA algorithm Section 7.2 • Generate random values for AES key generation Section 11.1...

  • Page 168: Antenna Diversity

    The AT86RF212B supports PHY controlled antenna diversity in TX_ARET mode and software controlled antenna diversity (that is the microcontroller controls which antenna is used for transmission and reception) in Basic and Extended Operating Modes.
  • Page 169 AT86RF212B 11.3.3 Register Description Register 0x0D (ANT_DIV): The ANT_DIV register controls Antenna Diversity. Figure 11-10. Register ANT_DIV. 0x0D ANT_SEL reserved ANT_DIV Read/Write Reset value 0x0D ANT_DIV_EN ANT_EXT_SW_EN ANT_CTRL ANT_DIV Read/Write Reset value • Bit 7 - ANT_SEL Signals status of antenna at the time of the last IRQ_2 (RX_START) interrupt, IRQ_3 (TRX_END) interrupt, or TX_START event.
  • Page 170 If the register bit is set, the control pins DIG1/DIG2 are activated in all radio transceiver states as long as register bit ANT_EXT_SW_EN is set. If the AT86RF212B is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state.

  • Page 171: Rx/Tx Indicator

    This differential pin pair can be used to control PA, LNA, and RF switches. If the AT86RF212B is not in a receive or transmit state, it is recommended to disable register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to reduce the power consumption or avoid leakage current of external RF switches and other building blocks, especially during SLEEP state.
  • Page 172 It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP state. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.

  • Page 173: Rx Frame Time Stamping

    Atmel AT86RF212B pin 10 (DIG2). The pin turns from L to H after detection of a valid PHR. When enabled, DIG2 is set to DIG2 = H at the same time as IRQ_2 (RX_START) occurs, even if IRQ_2 (RX_START) is disabled.
  • Page 174 If this register bit is set, the RX Frame Time Stamping Mode is enabled. An incoming frame with a valid PHR is signaled via pin 10 (DIG2). The pin remains at high level until the end of the frame receive procedure, see Figure 11-13. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com.

  • Page 175: Frame Buffer Empty Indicator

    For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF212B Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing.
  • Page 176 Section 6.3), pin 24 (IRQ) indicates that an access to the Frame Buffer is not possible since PSDU data are not available yet. The pin 24 (IRQ) does not indicate any interrupts during this time. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com.

  • Page 177: Dynamic Frame Buffer Protection

    11.7 Dynamic Frame Buffer Protection 11.7.1 Overview The Atmel AT86RF212B continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again.

  • Page 178: Alternate Start-Of-Frame Delimiter

    The length of the SFD is one octet (eight symbols for BPSK and two symbols for O-QPSK). The octet is used for byte synchronization only and is not included in the Atmel AT86RF212B Frame Buffer. The value of the SFD can be changed if it is needed to operate in non-IEEE 802.15.4 compliant networks.

  • Page 179: Electrical Characteristics

    AT86RF212B 12 Electrical Characteristics 12.1 Absolute Maximum Ratings Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied.

  • Page 180: Digital Pin Characteristics

    IRQ_2, IRQ_3, IRQ_4 latency Relative to the event to be µs indicated Output clock frequency at pin 17 (CLKM) Configurable in register 0x03 CLKM CLKM_CTRL = 0 CLKM_CTRL = 1 CLKM_CTRL = 2 AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 181 AT86RF212B Symbol Parameter Condition Min. Typ. Max. Unit CLKM_CTRL = 3 CLKM_CTRL = 4 CLKM_CTRL = 5 CLKM_CTRL = 6 CLKM_CTRL = 7 20.0 CLKM_CTRL = 7 40.0 CLKM_CTRL = 7 25.0 CLKM_CTRL = 7 62.5 Notes: 1. For Fast SRAM read/write accesses on address space 0x82 – 0x94 the time t (Min.) and t...

  • Page 182: General Rf Specifications

    200/400/500/1000kb/s Notes: 1. For register bit SUB_MODE = 0 (register 0x0C, TRX_CTRL_2). For register bit SUB_MODE = 1 (register 0x0C, TRX_CTRL_2). A reference frequency accuracy of ±40ppm is required by [1], [2], [3], [4]. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com.

  • Page 183: Transmitter Characteristics

    AT86RF212B 12.6 Transmitter Characteristics Test Conditions (unless otherwise stated): = 3.0V, f = 914MHz, T = +25°C, Measurement setup see Figure 5-1. Symbol Parameter Condition Min. Typ. Max. Unit TX Output power Maximum configurable TX output TX_MAX power value Normal mode...

  • Page 184: Receiver Characteristics

    +1MHz +2MHz Channel rejection/selectivity: = 868.3MHz CRSO100 OQPSK-SIN-RC-100 = -82dBm -2MHz -1MHz +1MHz +2MHz Adjacent channel rejection: = -89dBm ACRB40 BPSK-40 -2MHz AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 185 AT86RF212B Symbol Parameter Condition Min. Typ. Max. Unit +2MHz Alternate channel rejection: = -89dBm AACRB40 BPSK-40 -4MHz +4MHz Adjacent channel rejection: = -82dBm ACROS250 OQPSK-SIN-250 -2MHz +2MHz Alternate channel rejection: = -82dBm AACROS250 OQPSK-SIN-250 -4MHz +4MHz Adjacent channel rejection: = -82dBm...
  • Page 186 AWGN channel, PER ≤ 1%, PSDU length 20 octets. Notes: 1. AWGN channel, PER ≤ 1%, PSDU length 127 octets. Compliant to [1]. Compliant to [2]. Compliant to [4]. Channel rejection is limited by modulation side lobes of interfering signal. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 187: Current Consumption Specifications

    AT86RF212B 12.8 Current Consumption Specifications Test Conditions (unless otherwise stated): = 3.0V, f = 914MHz, T = +25°C, Measurement setup see Figure 5-1. Symbol Parameter Condition Min. Typ. Max. Unit Supply current transmit state North American band, O-QPSK BUSY_TX modulation = +10dBm (boost mode) 26.5...

  • Page 188: Typical Characteristics

    13 Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the Atmel AT86RF212B. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement...
  • Page 189 AT86RF212B Figure 13-2. Current Consumption in TRX_OFF State. 13.1.2 PLL_ON state Figure 13-3. Current Consumption in PLL_ON State. 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 190 13.1.3 RX_ON state Figure 13-4. Current Consumption in RX_ON State – High Sensitivity. Figure 13-5. Current Consumption in RX_ON State – High Input Level. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 191 AT86RF212B Figure 13-6. Current Consumption in RX_ON State – Reduced Sensitivity. 13.1.4 TX_BUSY state Figure 13-7. Current Consumption in TX_BUSY State – Minimum Output Power. 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 192 Figure 13-8. Current Consumption in TX_BUSY State – Output Power 0dBm. Figure 13-9. Current Consumption in TX_BUSY State – Output Power 5dBm. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 193 AT86RF212B Figure 13-10. Current Consumption in TX_BUSY State – Maximum Output Power. 13.1.5 SLEEP Figure 13-11. Current Consumption in SLEEP. 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 194: State Transition Timing

    13.2 State Transition Timing Figure 13-12. Transition Time from EVDD to P_ON (CLKM available). Figure 13-13. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)). AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 195 AT86RF212B Figure 13-14. Transition Time from TRX_OFF to PLL_ON. 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 196: Register Reference

    14 Register Reference The Atmel AT86RF212B provides a register space of 64 8-bit registers used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value.
  • Page 197 AT86RF212B Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x2A IEEE_ADDR_6 IEEE_ADDR_6 0x2B IEEE_ADDR_7 IEEE_ADDR_7 0x2C XAH_CTRL_0 MAX_FRAME_RETRIES MAX_CSMA_RETRIES SLOTTED_OPERATION 0x2D CSMA_SEED_0 CSMA_SEED_0 0x2E CSMA_SEED_1 AACK_FVN_MODE AACK_SET_PD AACK_DIS_ACK AACK_I_AM_COORD...
  • Page 198 (1, 2, 3) The reset values of the Atmel AT86RF212B registers in state P_ON are shown in Table 14-2. Note: All reset values in Table 14-2 are only valid after a power on reset. After a reset procedure (/RST = L) as described in Section 7.1.4.5, the reset values of...

  • Page 199: Abbreviations

    AT86RF212B 15 Abbreviations AACK — Automatic Acknowledgement — Acknowledgement — Analog-to-Digital Converter — Antenna Diversity — Advanced Encryption Standard — Automatic Gain Control ARET — Automatic Retransmission AVREG — Analog Voltage Regulator AWGN — Additive White Gaussian Noise BATMON —...
  • Page 200 Transceiver — Transmitter — Video Bandwidth — Voltage Controlled Oscillator WPAN — Wireless Personal Area Network XOSC — Crystal Oscillator XTAL — Crystal AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 201: Ordering Information

    32QN2, 32-lead 5.0x5.0mm Body, 0.50mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. 17 Soldering Information Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C.

  • Page 202: Package Drawing - 32Qn2

    19 Package Drawing – 32QN2 SYMBOL MIN. NOM. MAX. NOTE AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 203: Appendix A - Continuous Transmission Test Mode

    (PRBS mode) or a continuous wave signal (CW mode). The AT86RF212B uses I/Q modulation for both, PRBS mode and CW mode. In CW mode, this results in a signal which is not placed at the selected channel center...
  • Page 204 Wait for IRQ_0 (PLL_LOCK) Register access 0x02 0x02 Initiate transmission, enter BUSY_TX state Measurement Perform measurement Register access 0x1C 0x00 Disable Continuous Transmission Test Mode Reset Reset AT86RF212B AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 205 AT86RF212B Table A-2. Additional CW Mode Programming Sequence. Step Action Register Value Description Reset Reset AT86RF212B rev. C Register access 0x0E 0x01 Set IRQ mask register, enable IRQ_0 (PLL_LOCK) Register access 0x02 0x03 Set radio transceiver state TRX_OFF Register access...

  • Page 206: Appendix B - Errata

    Appendix B – Errata AT86RF212B Rev. C No known errata. AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 207: References

    – Charged Device Model (CDM). [10] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001. [11] AT86RF212B Software Programming Model. 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 208: Data Sheet Revision History

    1. Remove content PRELIMINARY 2. Editorial update: a. Page 105: update note 1. On register 0x09 b. Page 203: update overview section 42002B 04/2013 Editorial updates 42002A 02/2013 Initial release AT86RF212B 42002E–MCU Wireless–02/2015 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 209: Table Of Contents

    700/800/900MHz Transceiver for ZigBee, ..........1 IEEE 802.15.4, ..................1 6LoWPAN, and ISM ................1 Applications ................... 1 AT86RF212B ................... 1 1 Pin-out Diagram .................. 2 1.1 Pin Descriptions...................... 3 1.2 Analog and RF Pins ....................4 1.3 Digital Pins ......................6 2 Disclaimer ....................
  • Page 210 10 Radio Transceiver Usage ............. 157 10.1 Frame Receive Procedure ................157 10.2 Frame Transmit Procedure ................158 11 AT86RF212B Extended Feature Set ..........159 11.1 Security Module (AES) ..................159 11.2 Random Number Generator ................167 11.3 Antenna Diversity ..................... 168 11.4 RX/TX Indicator ....................
  • Page 211 Appendix A – Continuous Transmission Test Mode ...... 203 A.1 – Overview ......................203 A.2 – Configuration ....................203 Appendix B – Errata ................206 AT86RF212B Rev. C ....................206 References..................207 Data Sheet Revision History ............. 208 Table of Contents ................209 42002E–MCU Wireless–02/2015...
  • Page 212 DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.