NEC startWARE-GHS-VR4131 Manuals

Manuals and User Guides for NEC startWARE-GHS-VR4131. We have 1 NEC startWARE-GHS-VR4131 manual available for free PDF download: Preliminary User's Manual

NEC startWARE-GHS-VR4131 Preliminary User's Manual (96 pages)

Starter Kit VR4131

Brand: NEC | Category: Computer Hardware | Size: 1 MB

Regional Information
4
Preface
5
Table of Contents
7
Chapter 1 Introduction
13
System Requirements
13
Package Contents
13
Related Documents
13
Used Abbreviations
14
Chapter 2 Board Features
15
Figure 2-1: Simplified Block Diagram
16
Chapter 3 Functional Description
17
Flash Memory
17
Main Memory
17
FPGA Functions
17
Figure 3-1: FPGA Block Diagram - I/O Circuits
18
Figure 3-2: FPGA State Diagram - Power on Logic
19
Memory Mapping
20
Figure 3-3: Startware-GHS-VR4131 Address Map for Kseg1 (Unmapped, Uncached)
20
Chapter 4 Detailed Functional Description
21
Usage of VR4131 GPIO Pins
21
Table 4-1: VR4131 GPIO Pin Usage
21
Jumper Settings
22
Pipeline Clock Setting
22
Table 4-2: Example for Default Jumper Setting Marking
22
Table 4-3: Pipeline Clock Setting for VR4131
22
Table 4-4: Jumper Positions for Pipeline Clock Setting
23
Endianness Setting
24
Data Bus Width Setting
24
Table 4-5: Jumper Positions for Endianness Setting
24
Table 4-6: Jumper Positions for Data Bus Width Setting
24
MIPS16 Enable Setting
25
Other Jumper Settings
25
Table 4-7: Jumper Positions for MIPS16 Enable Setting
25
Table 4-8: Jumper Positions for Data Bus Width Setting
25
Jumpers for Power Supply Control
26
Table 4-9: Jumper Positions for Power Supply Control (1/2)
26
Jumpers for Debug SIU and Gpios
27
Table 4-10: Debug Serial Interface Usage
27
Figure 4-1: Jumper Positions
28
Switch Settings
29
DIP Switch Settings
29
Figure 4-2: DIP Switch Setting for SW1 and SW2
29
Table 4-11: DIP Switch Setting for SW1
29
Other Switch Settings
30
Connectors
30
Power Supply Connectors (CN21, 22 and 23)
30
Figure 4-3: Power Supply Connectors (Board Front View)
30
Usage of the N-Wire ICE Connector (CN1)
31
Figure 4-4: N-Wire Connector
31
Table 4-12: Jumper Setting to Enable N-Wire
31
Using the Serial Interface (CN16)
32
Figure 4-5: Serial Interface Connector CN16
32
Usage of Debug Serial Interface (CN17)
33
Figure 4-6: Serial Interface Connector CN17
33
Table 4-13: Debug Serial Interface Usage
33
Using the FIR Interface
34
Using the CSI Interface (CN3)
34
Table 4-14: FIR/N-Wire Interface Selection
34
Table 4-15: CSI Connector Pin Assignment (CN3)
34
General Purpose Ios at CN11
35
Table 4-16: GPIO and EPIO Pin Assignment at CN11
35
General Purpose Io's at CN12 and CN13
36
PCI Connector CN10
36
Table 4-17: Pin Assignment at CN12
36
Table 4-18: Pin Assignment at CN13
36
Figure 4-7: PCI Connector Pin Assignment
37
I/O Board Connector CN9
38
Figure 4-8: I/O Board Connector Pin Assignment
38
Ravin Board Connector CN8
39
Figure 4-9: Ravin Board Connector Pin Assignment
39
FPGA Register Set
40
Table 4-19: FPGA Register Set
40
REVREG (0X0A00 0000)
41
MODE_REG (0X0A00 0004)
42
LEDREG (0X0A00 0008)
43
DIPSWITCHREG (0X0A00 000C)
45
FLASHACCREG (0X0A00 0010)
46
CSICONTREG (0X0A00 0014)
47
FPGAINTREG (0X0A00 0018)
48
FPGAINTENREG (0X0A00 001C)
49
FPGAINTPOLREG (0X0A00 0020)
51
EPIO_MODEREG (0X0A00 0060)
53
EPIO_REG (0X0A00 0064)
54
FPIO_MODEREG (0X0A00 0068)
55
FPIO_REG (0X0A00 006C)
56
FPGA_I_O_MODEREGL (0X0A00 0070)
57
FPGA_I_O_REGL (0X0A00 0074)
58
FPGA_I_O_MODEREGH (0X0A00 0078)
59
FPGA_I_O_REGH (0X0A00 007C)
60
Chapter 5 Board Operation
61
Getting Started
61
S-Boot Operation
61
Features
61
S-Boot Startup Message
62
Figure 5-1: Startup Screen
62
Flash Monitor of Startware-GHS-VR4131
63
Figure 5-2: Startware-GHS-VR4131 Flash Monitor Boot Menu
63
FLASH Options
64
Figure 5-3: Startware-GHS-VR4131 Flash Menu
64
Figure 5-4: Startware-GHS-VR4131 Directory List
65
Reset Process Flow
66
Figure 5-5: Startware-GHS-VR4131 Boot Flow Chart
66
SBOOT Specification
67
Reprogramming the FPGA
68
Appendix A Circuit Diagrams
69
Appendix B FPGA Code
79

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