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MagnaChip MC80C0208Q User Manual

8-bit single-chip microcontrollers
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MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0208/16/24
MC80C0208/16/24
User's Manual
(Ver. 0.2)
Preliminary

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Summary of Contents for MagnaChip MC80C0208Q

  • Page 1 MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0208/16/24 MC80C0208/16/24 User’s Manual (Ver. 0.2) Preliminary...

  • Page 2: Revision History

    MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way re- sponsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 3: Table Of Contents

    MC80F0208/16/24 1. OVERVIEW ..............................1 Description ..............................1 Features ................................ 1 Ordering Information ..........................2 Development Tools ............................3 2. BLOCK DIAGRAM ............................4 3. PIN ASSIGNMENT ............................5 4. PACKAGE DIAGRAM ........................... 6 5. PIN FUNCTION .............................. 7 Pin Description .............................. 8 6.
  • Page 4 MC80F0208/16/24 Serial Interface Configuration ........................77 Communication operation ........................... 80 Relationship between main clock and baud rate ..................82 18. BUZZER FUNCTION ..........................83 19. INTERRUPTS ............................85 Interrupt Sequence ............................. 87 BRK Interrupt .............................. 89 Shared Interrupt Vector ..........................89 Multi Interrupt ..............................

  • Page 5: Overview

    I/O pins with typical 20mA. In addition, the MC80F0208/16/24 supports power saving modes to reduce power consumption. Device Name FLASH(ROM) I/O PORT Package Size FLASH MASK ROM MC80F0208Q MC80C0208Q 44MQFP 1024 8KByte 8 channel 1 channel 36 port Byte MC80F0208K...

  • Page 6: Ordering Information

    - Crystal, Ceramic resonator, External clock • 44MQFP, 42SDIP type • Operating Temperature : -40°C ~ 85°C 1.3 Ordering Information ROM Type Device name ROM Size RAM size Package MC80C0208Q 8K bytes 44MQFP 1024 bytes MC80C0208K 8K bytes 42SDIP MC80C0216Q 16K bytes...

  • Page 7: Development Tools

    There are two different type of programmers such as single type and gang type. For mode detail, Macro assembler op- erates under the MS-Windows 95 and upversioned Windows OS. Please contact sales part of MagnaChip semiconductor. - MS-Windows based assembler Software...

  • Page 8: Block Diagram

    MC80F0208/16/24 Preliminary 2. BLOCK DIAGRAM Power ADC Power Supply Supply R00~R07 Stack Pointer Data Memory (1024 bytes) Program Memory Interrupt Controller Data Table 8-bit Basic System controller Interval Timer System Clock Controller 8-bit Watch/ 8-bit serial 8-bit serial Instruction 10-bit 10-bit Timer/ Timing Generator...

  • Page 9: Pin Assignment

    Preliminary MC80F0208/16/24 3. PIN ASSIGNMENT R63 / AN3 42SDIP AN4 / R64 R62 / AN2 (Top View) AN5 / R65 R61 / AN1 AN6 / R66 R60 / AN0 AN7 / R67 R54 / PWM3O / T3O R51 / EC1 R50 / INT3 R47 / TxD0 R46 / RxD0...

  • Page 10: Package Diagram

    MC80F0208/16/24 Preliminary 4. PACKAGE DIAGRAM 42SDIP UNIT: INCH 1.470 1.450 0.600 BSC 0.550 0.530 0.070 BSC 0.020 0.045 0-15° 0.016 0.035 44MQFP UNIT: MM 13.45 12.95 10.10 9.90 0-7° SEE DETAIL “A” 1.03 0.73 2.35 max. 1.60 0.80 BSC 0.45 DETAIL “A”...

  • Page 11: Pin Function

    Preliminary MC80F0208/16/24 5. PIN FUNCTION : Supply voltage. port with typical 20mA at low level output. In addition, R3 serves the functions of the following special fea- : Circuit ground. tures such as ACLK1 (UART1 Asynchronous serial clock input), : Supply voltage to the ladder resistor of ADC circuit. RxD1 (UART1 data input), TxD1 (UART1 data output).

  • Page 12: Pin Description

    MC80F0208/16/24 Preliminary 5.1 Pin Description 5.1.1 Normal Function Pin Description Initial Alternate PIN NAME In/Out Function state Function Port0 8-bit I/O port. R00~R07 Input Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU0 can be used via software. INT0 Port 1.
  • Page 13 Preliminary MC80F0208/16/24 5.1.2 Alternate Function Pin Description Initial Shared PIN NAME In/Out Function state INT0 INT1 Valid edges(rising, falling, or both rising and falling) can be specified. Input External Interrupt request Input. INT2 INT3 BUZO Buzzer Output Input Timer0 Event Counter Input Input Timer2 Event Counter Input Input...

  • Page 14: Port Structures

    MC80F0208/16/24 Preliminary 6. PORT STRUCTURES R00~R07, R40, R41 R13(BUZO), R47(TxD0) Pull-up Pull-up Pull-up Pull-up Reg. Reg. BUZO,TxD0 Data Reg. Data Reg. Direction Reg. Direction Reg. BUZO_EN,TxD0_EN Data Bus Data Bus R10(INT0)~ R12(INT2), R15(EC0), R43(SI), R45(ACLK0), R46(RxD0) Pull-up Pull-up Reg. Data Reg. Data Reg.
  • Page 15 Preliminary MC80F0208/16/24 R33(TxD1) R44(SO, IOSWIN) Pull-up Pull-up Reg. TxD1 Data Reg. Data Reg. Direction Direction Reg. Reg. TxD1_EN SO_EN Data Bus Data Bus IOSWIN_EN Noise Filter IOSWIN_EN R42(SCK) R31(ACLK1), R32(RxD1), R50(INT3), R51(EC1) Pull-up Pull-up Reg. Data Reg. Direction Data Reg. Reg.
  • Page 16 MC80F0208/16/24 Preliminary R54(PWM3O/T3O) PWM3O Data Reg. STOP Direction Reg. PWM3_EN Data Bus MAIN CLOCK R60~R67(AN0~AN7) RESET Data Reg. Mask only Direction Reg. Internal Reset Data Bus AN[7:0] ADC_EN & CH_SEL MAR. 2005 Ver 0.2...

  • Page 17: Electrical Characteristics

    Preliminary MC80F0208/16/24 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Note -0.3 ~ +6.5 Supply Voltage - 0.3 ~ V +0.3 -0.3 ~ V +0.3 Voltage on any pin with respect to Ground (V -0.3 ~ V +0.3 Maximum output current sourced by (I per I/O Pin)

  • Page 18: Dc Electrical Characteristics

    MC80F0208/16/24 Preliminary Parameter Symbol Conditions Min. Typ. Max. Unit Analog Input Voltage Analog Power Supply +0.3 Analog Ground µA =5.12V Analog Input Current ADIN µA =5.12V Analog Block Current Note : 4MHz(f ) / 2 X 13Cycle = 13uS 7.4 DC Electrical Characteristics =-40~85°C, V =5.0V±10%, V =0V, f...
  • Page 19 Preliminary MC80F0208/16/24 Parameter Symbol Pin/Condition Min. Typ. Max. Unit Active Mode, X =8MHz Sleep Mode, X =8MHz SLEEP Power Supply Current µA Stop Mode, Oscillator Stop, X =4MHz STOP µA Stop Mode, Oscillator Stop, X =8MHz RCWDT MAR. 2005 Ver 0.2...

  • Page 20: Ac Characteristics

    MC80F0208/16/24 Preliminary 7.5 AC Characteristics =-40~85°C, V =5V±10%, V =0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Operating Frequency Oscillation Stabilizing Time (4MHz) External Clock Pulse Width External Clock Transi- RCP, tion Time Interrupt Pulse Width INT0, INT1, INT2, INT3 RESET Input Width RESET Event Counter Input...

  • Page 21: Serial Interface Timing Characteristics

    Preliminary MC80F0208/16/24 7.6 Serial Interface Timing Characteristics =-40~+85°C, V =5V±10%, V =0V, f =8MHz) Specifications Parameter Symbol Pins Unit Min. Typ. Max. +200 Serial Input Clock Pulse SCYC Serial Input Clock Pulse Width SCKW FSCK Serial Input Clock Pulse Transition Time RSCK FSIN Serial Input Pulse Transition Time...

  • Page 22: Typical Characteristic Curves

    MC80F0208/16/24 Preliminary 7.7 Typical Characteristic Curves This graphs and tables provided in this section are for design The data presented in this section is a statistical summary of data guidance only and are not tested or guaranteed. collected on units from different lots over a period of time. “Typ- ical”...

  • Page 23: Operating Area

    Preliminary MC80F0208/16/24 −V −V −V SLEEP Main Active Mode Main Active Mode STOP Main Active Mode (mA) (mA) (µA) =25°C =25°C =25°C = 12MHz 8MHz 8MHz = 12MHz = 12MHz, 8MHz, 4MHz 4MHz 4MHz Operating Area (MHz) = -40~85°C Actual Operating Area 2.1~7.0V @ (0.2~8MHz) 2.6~7.0V @ (0.2~16MHz) Spec Operating Area...

  • Page 24: Memory Organization

    MC80F0208/16/24 Preliminary 8. MEMORY ORGANIZATION The MC80F0208/16/24 has separate address spaces for Program Data memory can be read and written to up to 1024 bytes includ- memory and Data Memory. Program memory can only be read, ing the stack area. not written to.
  • Page 25 Preliminary MC80F0208/16/24 V G B H RESET VALUE: 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE INTERRUPT ENABLE FLAG when G=1, page is selected to “page 1” HALF CARRY FLAG RECEIVES BRK FLAG CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 8-3 PSW (Program Status Word) Register...

  • Page 26: Program Memory

    MC80F0208/16/24 Preliminary At execution of At acceptance At execution At execution a CALL/TCALL/PCALL of interrupt of RET instruction of RET instruction Push 01FF 01FF 01FF 01FF down Push 01FE 01FE 01FE 01FE down 01FD 01FD 01FD 01FD 01FC 01FC 01FC 01FC SP before 01FF...
  • Page 27 Preliminary MC80F0208/16/24 The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFC . The in- A000 terrupt service locations spaces 2-byte interval: 0FFFA 0FFFB for External Interrupt 1, 0FFFC and 0FFFD...
  • Page 28 MC80F0208/16/24 Preliminary Address Program Memory PCALL Area Memory Address 0FFC0 0FF00 TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 PCALL Area (256 Bytes) TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *...
  • Page 29 Preliminary MC80F0208/16/24 Example: The usage software example of Vector address for MC80F0208/16/24 . ;Interrupt Vector Table 0FFE0H BIT_TIMER ; BIT WATCH_WDT ; WDT & WT ; AD Converter TIMER4 ; Timer-4 TIMER3 ; Timer-3 TIMER2 ; Timer-2 TIMER1 ; Timer-1 TIMER0 ;...

  • Page 30: Data Memory

    MC80F0208/16/24 Preliminary 8.3 Data Memory Control Registers Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user RAM, control regis- The control registers are used by the CPU and Peripheral function ters, and Stack memory. blocks for controlling the desired operation of the device.

  • Page 31: Addressing Mode

    Preliminary MC80F0208/16/24 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00C0 R0 port data register 0 0 0 0 0 0 0 0 byte, bit 00C1 R0 port I/O direction register R0IO 0 0 0 0 0 0 0 0 byte 00C2...
  • Page 32 MC80F0208/16/24 Preliminary Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 Timer 3 register 0 0 0 0 0 0 0 0 00DA Timer 3 PWM duty register T3PDR 0 0 0 0 0 0 0 0 byte Timer 3 capture data register CDR3...
  • Page 33 Preliminary MC80F0208/16/24 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 Watch dog timer register WDTR 0 1 1 1 1 1 1 1 00F4 byte Watch dog timer data register WDTDR Undefined 00F5 Stop &...
  • Page 34 MC80F0208/16/24 Preliminary Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0C0H R0 Port Data Register 0C1H R0IO R0 Port Direction Register 0C2H R1 Port Data Register 0C3H R1IO R1 Port Direction Register 0C4H Reserved 0C5H...
  • Page 35 Preliminary MC80F0208/16/24 Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T4H/ 0DEH TDR4H/ Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High CDR4H 0DFH RX0IOF TX0IOF RX1IOF TX1IOF...

  • Page 36: Addressing Mode

    MC80F0208/16/24 Preliminary Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0FFH Reserved ASIMR1 TXE1 RXE1 PS11 PS10 ISRM1 EE6H ASISR1 OVE1 EE7H BRGCR1 TPS12 TPS11 TPS10 MLD13 MLD12 MLD11 MLD10 EE8H RXR1 UART1 Receive Buffer Register...

  • Page 37: Indexed Addressing

    Preliminary MC80F0208/16/24 ;A ←RAM[35H] ;A ←ROM[135H] C535 983501 !0135H data 135H data → data → data+1 data 0E550H 0F100H 0E551H 0F101H address: 0135 0F102H 8.4.4 Absolute Addressing → !abs 8.4.5 Indexed Addressing Absolute addressing sets corresponding memory data to Data, i.e. X indexed direct page (no offset) →...

  • Page 38: Indirect Addressing

    MC80F0208/16/24 Preliminary D500FA !0FA00H+Y data 0F100H → data 0F101H → 0F102H 0FA00H+55H=0FA55H 0FA55H data → data X indexed direct page (8 bit offset) → dp+X 8.4.6 Indirect Addressing This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. Direct page indirect →...
  • Page 39 Preliminary MC80F0208/16/24 Absolute indirect → [!abs] 1625 [25H+X] The program jumps to address specified by 16-bit absolute ad- dress. Example; G=0 0E005H 1F25E0 [!0C025H] 25 + X(10) = 35H 0E005H data PROGRAM MEMORY 0FA00H 0E025H → A + data + C 0E026H jump to Y indexed indirect →...

  • Page 40: I/O Ports

    MC80F0208/16/24 Preliminary 9. I/O PORTS The MC80F0208/16/24 has six ports (R0, R1, R3, R4, R5 and R6). These ports pins may be multiplexed with an alternate func- tion for the peripheral features on the device. R3 port can drive ADDRESS: 0C0 R0 Data Register RESET VALUE: 00 maximum 20mA of high current in output low state, so it can di-...
  • Page 41 Preliminary MC80F0208/16/24 port (address 0C6 ). Each I/O pin can independently used as an input or an output through the R3IO register (address 0C7 In addition, Port R3 is multiplexed with various special features. ADDRESS: 0C2 R1 Data Register After reset, this value is “0”, port may be used as normal I/O port. RESET VALUE: 00 R13 R12 R11 R10 Input / Output data...
  • Page 42 MC80F0208/16/24 Preliminary ADDRESS: 0CA ADDRESS: 0C8 R5 Data Register R4 Data Register RESET VALUE: ---00000 RESET VALUE: 00 R51 R50 R47 R46 R45 R44 R43 R42 R41 R40 Input / Output data Input / Output data ADDRESS: 0CB ADDRESS: 0C9 R5 Direction Register R4 Direction Register RESET VALUE: ---00000...
  • Page 43 Preliminary MC80F0208/16/24 channel selection ADDRESS: 0CC R6 Data Register RESET VALUE: 00 R67 R66 R65 R64 R63 R62 R61 R60 Input / Output data ADDRESS: 0CD R6 Direction Register RESET VALUE: 00 R6IO Port Direction 0: Input 1: Output MAR. 2005 Ver 0.2...

  • Page 44: Clock Generator

    MC80F0208/16/24 Preliminary 10. CLOCK GENERATOR As shown in Figure 10-1, the clock generator produces the basic through a divide-by-two flip-flop, but minimum and maximum clock pulses which provide the system clock to be supplied to the high and low times specified on the data sheet must be observed. CPU and the peripheral hardware.

  • Page 45: Basic Interval Timer

    Preliminary MC80F0208/16/24 11. BASIC INTERVAL TIMER The MC80F0208/16/24 has one 8-bit Basic Interval Timer that is cleared to "0" and restart to count-up. The bit BTCL becomes "0" free-run and can not stop. Block diagram is shown in Figure 11- after one machine cycle by hardware.
  • Page 46 MC80F0208/16/24 Preliminary ADDRESS: 0F2 CKCTLR BTCL ADRST RCWDT WDTON BTCL BTS2 BTS1 BTS0 INITIAL VALUE: 0-01 0111 Basic Interval Timer source clock select ÷ 000: f ÷ 001: f ÷ 010: f ÷ 011: f ÷ 100: f ÷ 101: f ÷...

  • Page 47: Watchdog Timer

    Preliminary MC80F0208/16/24 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as The RC oscillated watchdog timer is activated by setting the bit endless looping caused by noise or the like, and resumes the CPU RCWDT as shown below. to the normal state.
  • Page 48 MC80F0208/16/24 Preliminary Watchdog Timer Control counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to Figure 12-2 shows the watchdog timer control register. The low to reset the internal hardware. When WDTON=0, a watchdog watchdog timer is automatically disabled after reset.
  • Page 49 Preliminary MC80F0208/16/24 Source clock BIT overflow Binary-counter Counter Counter Clear Clear WDTR Match Detect WDTIF interrupt WDTR ← “1000_0011 ” WDT reset reset Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, reset is generated in sub clock mode. which drives the RESET pin low to reset the internal hardware.

  • Page 50: Watch Timer

    MC80F0208/16/24 Preliminary 13. WATCH TIMER ÷2 The watch timer generates interrupt for watch operation. The nized. In f clock source, if the CPU enters into stop mode, watch timer consists of the clock selector, 15-bit binary counter, the main-clock is stopped and then watch timer is also stopped. interval selector and watch timer mode register.

  • Page 51: Timer/Event Counter

    Preliminary MC80F0208/16/24 14. TIMER/EVENT COUNTER The MC80F0208/16/24 has five Timer/Counter registers. Each external clock edge input, the count register is captured into cap- module can generate an interrupt to indicate that an event has oc- ture data register CDRx. curred (i.e. timer match). Timer 0 and Timer 1 has four operating modes: "8-bit timer/ Timer 0 and Timer 1 are can be used either two 8-bit Timer/ counter", "16-bit timer/counter", "8-bit capture"...
  • Page 52 MC80F0208/16/24 Preliminary CAP4 T4CK[2:0] TIMER 4 16-bit Timer 16-bit Capture (internal clock) Table 14-3 Operating Modes of Timer 4 MAR. 2005 Ver 0.2...
  • Page 53 Preliminary MC80F0208/16/24 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag ÷ T0CK2 TM0.4 000: 8-bit Timer, Clock source is f T0CK1 TM0.3 ÷...
  • Page 54 MC80F0208/16/24 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP2 TM2.5 0: Timer/Counter mode 1: Capture mode selection flag ÷ T2CK2 TM2.4 000: 8-bit Timer, Clock source is f T2CK1 TM2.3 ÷...

  • Page 55: 8-Bit Timer / Counter Mode

    Preliminary MC80F0208/16/24 ADDRESS: 0DC CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP4 TM4.5 0: Timer/Counter mode 1: Capture mode selection flag ÷ T4CK2 TM4.4 000: 8-bit Timer, Clock source is f T4CK1 TM4.3 ÷...
  • Page 56 MC80F0208/16/24 Preliminary ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D2 16BIT CAP1 T1CK1 BTCL T1CK0 T1CN T1ST INITIAL VALUE: -0-0 0000 X means don’t care T0CK[2:0] EDGE DETECTOR EC0 PIN T0ST ÷...
  • Page 57 Preliminary MC80F0208/16/24 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] EDGE DETECTOR EC1 PIN T2ST ÷...

  • Page 58: 8-Bit Timer Mode

    MC80F0208/16/24 Preliminary Example 1: These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock in- Timer0 = 2ms 8-bit timer mode at 4MHz put. The internal clock has a prescaler divide ratio option of 2, 4, Timer1 = 0.5ms 8-bit timer mode at 4MHz 8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of reg- Timer2 = 1ms 8-bit timer mode at 4MHz...
  • Page 59 Preliminary MC80F0208/16/24 Example: Make 1ms interrupt using by Timer0 at 4MHz TM0,#0FH ; divide by 32 TDR0,#124 ; 8us x (124+1)= 1ms SET1 ; Enable Timer 0 Interrupt ; Enable Master Interrupt When TM0 = 0000 1111 (8-bit Timer mode, Prescaler divide ratio = 32) TDR0 = 124 = 7C = 4 MHz...
  • Page 60 MC80F0208/16/24 Preliminary TDR1 enable disable clear & start stop TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt T1ST T1ST = 1 Start & Stop T1ST = 0 T1CN T1CN = 1 Control count T1CN = 0 Figure 14-9 Count Operation of Timer / Event counter MAR.

  • Page 61: 16-Bit Timer / Counter Mode

    Preliminary MC80F0208/16/24 14.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit timer/ T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively counter register T0, T1 are incremented from 0000 until it as shown in Figure 14-11.

  • Page 62: 8-Bit Compare Output (16-Bit)

    MC80F0208/16/24 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] EDGE DETECTOR EC1 PIN T2ST ÷...

  • Page 63: 8-Bit Capture Mode

    Preliminary MC80F0208/16/24 ADDRESS: 0DC CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST INITIAL VALUE: 00 X means don’t care T4CK[2:0] ÷ 2 ÷ 4 T4ST 0: Stop ÷ 8 1: Clear and start ÷ 16 T4H + T4L ÷ 64 (16-bit) clear ÷...
  • Page 64 MC80F0208/16/24 Preliminary ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D2 16BIT CAP1 T1CK1 BTCL T1CK0 T1CN T1ST INITIAL VALUE: -0-0 0000 X means don’t care T0CK[2:0] Edge Detector EC0 PIN T0ST ÷...
  • Page 65 Preliminary MC80F0208/16/24 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] Edge Detector EC1 PIN T2ST ÷...
  • Page 66 MC80F0208/16/24 Preliminary This value is loaded to CDR0 TIME Ext. INT0 Pin Interrupt Request ( INT0IF ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0IF ) 20nS Delay Clear & Start Capture ( Timer Stop ) Figure 14-15 Input Capture Operation of Timer 0 Capture mode Ext.

  • Page 67: 16-Bit Capture Mode

    Preliminary MC80F0208/16/24 14.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits Timer register is being run will 16 bits. The clock source of the T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1"...
  • Page 68 MC80F0208/16/24 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] Edge Detector EC1 PIN T2ST ÷...
  • Page 69 Preliminary MC80F0208/16/24 ADDRESS: 0DC CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST INITIAL VALUE: 00 X means don’t care T4CK[2:0] ÷ 2 ÷ 4 T4ST ÷ 8 0: Stop 1: Clear and start ÷ 16 TDR4H + TDR4L ÷ 64 (16-bit) ÷...

  • Page 70: Pwm Mode

    MC80F0208/16/24 Preliminary 14.6 PWM Mode The MC80F0208/16/24 has a high speed PWM (Pulse Width The bit POL of TM3 decides the polarity of duty cycle. Modulation) functions which shared with Timer3. If the duty value is set same to the period value, the PWM output In PWM mode, pin R54/PWM3O outputs up to a 10-bit resolu- is determined by the bit POL (1: High, 0: Low).

  • Page 71: Initial Value

    Preliminary MC80F0208/16/24 ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X:The value "0" or "1" corresponding your operation. ADDRESS: 0DB T3PWHR BTCL T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 INITIAL VALUE: ---- 0000 Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation. Period High Duty High ADDRESS: 0D9...
  • Page 72 MC80F0208/16/24 Preliminary Source clock PWM3E T3ST T3CN PWM3O [POL=1] PWM3O [POL=0] Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ] T3CK[1:0] = 00 ( XIN ) T3PPR (8-bit) Period T3PWHR3 T3PWHR2 T3PWHR = 0CH T3PPR = FFH T3PDR (8-bit)

  • Page 73: Analog To Digital Converter

    Preliminary MC80F0208/16/24 15. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an ADCRH and ADCRL contains the results of the A/D conversion. analog input signal to a corresponding 10-bit digital value. The A/ When the conversion is completed, the result is loaded into the D module has sixteen analog inputs, which are multiplexed into ADCRH and ADCRL, the A/D conversion status bit ADSF is set one sample and hold.
  • Page 74 MC80F0208/16/24 Preliminary (4) AV pin input impedance parallel connection to the series resistor string between the AV pin and the AV pin, and there will be a large analog supply volt- A series resistor string of approximately 5KΩ is connected be- age error.
  • Page 75 Preliminary MC80F0208/16/24 ADDRESS: 0EF ADCM BTCL ADEN ADCK ADS2 ADS1 ADS0 ADST ADSF INITIAL VALUE: 00-0 0001 A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0”...

  • Page 76: Serial Input/Output (Sio)

    MC80F0208/16/24 Preliminary 16. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit data se- control circuit as illustrated in Figure 16-1. The SO pin is de- rially. The Serial Input/Output(SIO) module is a serial interface signed to input and output. So the Serial I/O(SIO) can be operated useful for communicating with other peripheral of microcontrol- with minimum two pin.

  • Page 77: Transmission/Receiving Timing

    Preliminary MC80F0208/16/24 Serial I/O Mode Register(SIOM) controls serial I/O function. Ac- Serial I/O Data Register(SIOR) is an 8-bit shift register. First cording to SCK1 and SCK0, the internal clock or external clock LSB is send or is received. can be selected. ADDRESS: 0E2 SIOM BTCL...
  • Page 78 MC80F0208/16/24 Preliminary SIOST SCK [R42] (POL=0) SO [P44] SI [R43] (IOSW=0) IOSWIN [P44] (IOSW=1) SIOSF (SIO Status) SIOIF (SIO Int. Req) Figure 16-3 Serial I/O Timing Diagram at POL=0 SIOST SCK [R42] (POL=1) SO [R44] SI [R43] (IOSW=0) IOSWIN [R44] (IOSW=1) SIOSF (SIO Status)

  • Page 79: The Method Of Serial I/O

    Preliminary MC80F0208/16/24 16.2 The method of Serial I/O 1. Select transmission/receiving mode. SIOR,#0AAh ;set tx data 2. In case of sending mode, write data to be send to SIOR. SIOM,#0011_1100b ;set SIO mode 3. Set SIOST to “1” to start serial transmission. SIOM,#0011_1110b ;SIO Start 4.

  • Page 80: Universal Asynchronous Receiver/Transmitter (Uart)

    MC80F0208/16/24 Preliminary 17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 17.1 UART Serial Interface Functions The Universal Asynchronous Receiver/Transmitter(UART) en- Note: The UART1 control register ASIMR1,ASISR1, ables full-duplex operation wherein one byte of data after the start BRGCR1, RXR1 and TXR1 are located at EE6H ~ EE9H bit is transmitted and received.
  • Page 81 Preliminary MC80F0208/16/24 RECEIVE ACLK PIN 5-bit counter /2 ~ f match Tx_Clock (Divider) Decoder match Rx_Clock (Divider) TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 (BRGCR) 5-bit counter Internal Data Bus SEND Figure 17-2 Baud Rate Generator Block Diagram ADDRESS: 0DF RX0IOF TX0IOF RX1IOF TX1IOF WTIOF...

  • Page 82: Serial Interface Configuration

    MC80F0208/16/24 Preliminary 17.2 Serial Interface Configuration The UART interface consists of the following hardware. receive shift register (RXSR). When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXR0. In this case, the MSB of RXR always becomes 0.
  • Page 83 Preliminary MC80F0208/16/24 Asynchronous serial interface status register0 (ASISR) When a receive error occurs during UART mode, this register in- 000B. Figure 17-5 shows the format of ASISR. dicates the type of error. ASISR can be read by an 8 bit memory manipulation instruction.
  • Page 84 MC80F0208/16/24 Preliminary Baud rate generator control register (BRGCR) This register sets the serial clock for serial interface. BRGCR is Figure 17-6 shows the format of BRGCR. set by an 8 bit memory manipulation instruction. The RESET in- put sets BRGCR to -001_0000B. ADDRESS: 0E8 BRGCR0 BTCL...

  • Page 85: Communication Operation

    Preliminary MC80F0208/16/24 17.3 Communication operation The transmit operation is enabled when bit 7 (TXE0) of the asyn- chronous serial interface mode register (ASIMR) is set to 1. The transmit operation is started when transmit data is written to the transmit shift register (TXR). The timing of the transmit comple- UART0(UART1) Interrupt Request tion interrupt request is shown in Figure 17-8.
  • Page 86 MC80F0208/16/24 Preliminary 1. Stop bit Length : 1 bit 1 data frame Start Parity Stop character bits INTERRUPT INTERRUPT 2. Stop bit Length : 2 bit 1 data frame Start Parity Stop character bits INTERRUPT INTERRUPT 3. Stop bit Length : 1 bit, No parity 1 data frame Start Stop...

  • Page 87: Relationship Between Main Clock And Baud Rate

    Preliminary MC80F0208/16/24 17.4 Relationship between main clock and baud rate The transmit/receive clock that is used to generate the baud rate clock which is divided. The baud rate generated from the main is obtained by dividing the main system clock. Transmit/Receive system clock is determined according to the following formula.

  • Page 88: Buzzer Function

    MC80F0208/16/24 Preliminary 18. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, buzzer The bit 0 to 5 of BUZR determines output frequency for buzzer register BUZR, and clock source selector. It generates square- driving. wave which has very wide range frequency (488Hz ~ 250kHz at Equation of frequency calculation is shown below.
  • Page 89 Preliminary MC80F0208/16/24 The 6-bit counter is cleared and starts the counting by writing sig- When main-frequency is 4MHz, buzzer frequency is shown as nal at BUZR register. It is incremental from 00 until it matches below Table 18-1. 6-bit BUR value. BUR[7:6] BUR[7:6] [5:0]...

  • Page 90: Interrupts

    MC80F0208/16/24 Preliminary 19. INTERRUPTS The MC80F0208/16/24 interrupt circuits consist of Interrupt en- The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF, able register (IENH, IENL), Interrupt request flags of IRQH, T2IF, T3IF and T4IF which is set by a match in their respective IRQL, Priority circuit, and Master enable flag (“I”...
  • Page 91 Preliminary MC80F0208/16/24 The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register. Reset/Interrupt Symbol Priority The UART0 receive/transmit interrupt is generated by UART0IF is set by completion of UART0 data reception or transmission. Hardware Reset RESET The IFR(Interrupt Flag Register) is used for discrimination of the...

  • Page 92: Interrupt Sequence

    MC80F0208/16/24 Preliminary ADDRESS: 0EC IRQH T0IF INT0IF INT1IF INT2IF INT3IF UART0IF UART1IF SIOIF INITIAL VALUE: 0000 0000 Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag UART1Tx/Rx interrupt request flag UART0 Tx/Rx interrupt request flag External interrupt 3 request flag External interrupt 2 request flag External interrupt 1 request flag External interrupt 0 request flag...
  • Page 93 Preliminary MC80F0208/16/24 19.1.1 Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to and the program status word are saved (pushed) onto the “0” to temporarily disable the acceptance of any follow- stack area. The stack pointer decreases 3 times. ing maskable interrupts.

  • Page 94: Brk Interrupt

    MC80F0208/16/24 Preliminary interrupt processing ;RESTORE Y REG. main task ;RESTORE X REG. acceptance of interrupt ;RESTORE ACC. interrupt service task RETI ;RETURN saving registers General-purpose register save/restore using push and pop instruc- tions; restoring registers interrupt return 19.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order.

  • Page 95: Multi Interrupt

    Preliminary MC80F0208/16/24 processing step is determined by IFR as shown in Figure 19-6. UART0(UART1) Interrupt Request WDT or WT Interrupt Request Tx0IOF(Tx1IOF) Tx0(Tx1) Interrupt WDTIF WTIF Routine Clear Tx0IOF(Tx1IOF) WDT Interrupt WDT Interrupt Routine Routine Clear WDTIF Clear WTIF Rx0IOF(Rx1IOF) Rx0(Rx1) Interrupt Routine RETI...

  • Page 96: External Interrupt

    MC80F0208/16/24 Preliminary Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH PUSH IENH,#0FFH ;Enable all interrupts PUSH ;Enable INT0 only IENH,#80H IENL,#0FFH ;Disable other int. IENL,#0 ;Enable Interrupt RETI 19.5 External Interrupt The external interrupt on INT0, INT1, INT2 and INT3 pins are The edge detection of external interrupt has three transition acti- edge triggered depending on the edge selection register IEDS (ad- vated mode: rising edge, falling edge, and both edge.
  • Page 97 Preliminary MC80F0208/16/24 max. 12 f Interrupt Interrupt Interrupt Interrupt goes latched processing routine active Figure 19-9 Interrupt Response Timing Diagram ADDRESS: 0EE IEDS IED3H IED3L IED2H IED2L IED1H BTCL IED1L IED0H IED0L INITIAL VALUE: 00 INT3 INT2 INT1 INT0 Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition)

  • Page 98: Operation Mode

    MC80F0208/16/24 Preliminary 20. OPERATION MODE SLEEP Mode The system clock controller starts or stops the main-frequency clock oscillator. The operating mode is generally divided into the In this mode, the CPU clock stops while peripherals and the os- main active mode. Figure 20-1 shows the operating mode transi- cillation source continues to operate normally.

  • Page 99: Power Saving Operation

    Preliminary MC80F0208/16/24 21. POWER SAVING OPERATION The MC80F0208/16/24 has two power-down modes. In power- SLEEP mode. Table 21-1 shows the status of each Power Saving down mode, power consumption is reduced considerably. For ap- Mode. SLEEP mode is entered by the SSCR register to “0Fh”., plications where power consumption is a critical factor, device and STOP mode is entered by STOP instruction after the SSCR provides two kinds of power saving functions, STOP mode and...

  • Page 100: Stop Mode

    MC80F0208/16/24 Preliminary Oscillator pin) Internal Clock External Interrupt SLEEP Instruction Executed Normal Operation SLEEP Operation Normal Operation Figure 21-2 SLEEP Mode Release Timing by External Interrupt Oscillator pin) Clock RESET Internal RESET SLEEP Instruction Stabilization Time Execution = 65.5mS @4MHz Normal Operation Normal Operation SLEEP Operation...
  • Page 101 Preliminary MC80F0208/16/24 The reset should not be activated before V is restored to its with the oscillator and the internal hardware is lowered; however, normal operating level, and must be held active long enough to the power dissipation associated with the pin interface (depend- allow the oscillator to restart and stabilize.
  • Page 102 MC80F0208/16/24 Preliminary eration. Therefore, before STOP instruction, user must be set its By reset, exit from Stop mode is shown in Figure 21-6. relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and sta- bilized.

  • Page 103: Stop Mode At Internal Rc-Oscillated Watchdog Timer Mode

    Preliminary MC80F0208/16/24 STOP Mode Oscillator (XI pin) Internal Clock RESET Internal RESET STOP Instruction Execution Stabilization Time Time can not be control by software = 65.5mS @4MHz Figure 21-6 Timing of STOP Mode Release by Reset 21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip (at RC-watchdog timer mode).
  • Page 104 MC80F0208/16/24 Preliminary Oscillator pin) Internal RC Clock Internal Clock External Interrupt ( or WDT Interrupt ) Clear Basic Interval Timer STOP Instruction Execution Counter Normal Operation Stabilization Time STOP mode Normal Operation at RC-WDT Mode > 20mS Figure 21-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt RCWDT Mode Oscillator pin)

  • Page 105: Minimizing Current Consumption

    Preliminary MC80F0208/16/24 21.4 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To off output drivers that are sourcing or sinking current, if it is prac- minimize current drawn during Stop mode, the user should turn- tical. INPUT PIN INPUT PIN internal...
  • Page 106 MC80F0208/16/24 Preliminary no current flow after considering its relationship with external If it is not appropriate to set as an input mode, then set to output circuit. In input mode, the pin impedance viewing from external mode considering there is no current flow. The port setting to MCU is very high that the current doesn’t flow.

  • Page 107: Oscillator Circuit

    Preliminary MC80F0208/16/24 22. OSCILLATOR CIRCUIT The MC80F0208/16/24 have oscillation circuits internally. X verting amplifier which can be configured for being used as an and X are input and output for frequency. Respectively, in- on-chip oscillator, as shown in Figure 22-1. 8MHz Open External Clock...

  • Page 108: Reset

    MC80F0208/16/24 Preliminary 23. RESET The MC80F0208/16/24 have four types of reset generation pro- power fail processor reset, and address fail reset. Table 23-1 cedures; they are an external reset input, a watch-dog timer reset, shows on-chip hardware initialization by reset action. On-chip Hardware Initial Value On-chip Hardware...

  • Page 109: Power Fail Processor

    Preliminary MC80F0208/16/24 24. POWER FAIL PROCESSOR The MC80F0208/16/24 has an on-chip power fail detection cir- Note: If power fail voltage is selected to 2.4V or 2.7V on cuitry to immunize against power noise. A configuration register, below 3V operation, MCU is freezed at all the times. PFDR, can enable or disable the power fail detect circuitry.
  • Page 110 MC80F0208/16/24 Preliminary RESET VECTOR PFDS =1 RAM Clear Initialize RAM Data PFDS = 0 Skip the Initialize All Ports initial routine Initialize Registers Function Execution Figure 24-2 Example S/W of Reset flow by Power fail 65.5mS Internal RESET When PFDM = 1 65.5mS Internal t <...

  • Page 111: Flash Programming

    Preliminary MC80F0208/16/24 25. FLASH PROGRAMMING The Device Configuration Area can be programmed or left un- able and writable during FLASH program / verify mode. The De- programmed to select device configuration such as security bit. vice Configuration Area register is located at the address 20FF This area is not accessible during normal execution but is read- ADDRESS: 20FF PFS1...

  • Page 112: Emulator Eva. Board Setting

    MC80F0208/16/24 Preliminary 26. Emulator EVA. Board Setting MAR. 2005 Ver 0.2...
  • Page 113 Preliminary MC80F0208/16/24 DIP Switch and VR Setting Before execute the user program, keep in your mind the below configuration DIP S/W Description ON/OFF Setting This connector is only used for a device over 32 PIN. For the MC80F0208/16/24. This connector is only used for a device under 32 PIN. For the MC80F0204.
  • Page 114 MC80F0208/16/24 Preliminary DIP S/W Description ON/OFF Setting This switch select the Normal I/O These switches select the R33 or X port(on&off) or special function select(off&on). These switches select the R34 or X It is reserved for the MC80F0204. ON & OFF : R33,R34,R35 Port selected. OFF &...

  • Page 115: In-System Programming (Isp)

    D must be configured to enter the ISP mode. 1. Connect the serial(RS-232C) cable between a target 4. Run the MagnaChip ISP software. board and the COM port of your PC. 5. Press the Reset Button in the ISP S/W. If the status win- 2.
  • Page 116 MC80F0208/16/24 Preliminary Function Description Load HEX File Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format.

  • Page 117: Hardware Conditions To Enter The Isp Mode

    Preliminary MC80F0208/16/24 27.3 Hardware Conditions to Enter the ISP Mode The In-System Programming (ISP) is performed without remov- minimum of additional expense in components and circuit board ing the microcontroller from the target system. The In-System area. The boot loader can be executed by holding ALEB high, Programming(ISP) facility consists of a series of internal hard- RST/V as +9V, and ACLK0 with the OSC.

  • Page 118: Reference Isp Circuit Diagram

    V For the ISP operation, power consumption required is less than 30mA. Figure 27-2 Reference ISP Circuit Diagram Figure 27-3 MagnaChip supplied ISP Board MAR. 2005 Ver 0.2...
  • Page 119 APPENDIX...

  • Page 120: Instruction

    GMS800 Series A. INSTRUCTION A.1 Terminology List Terminology Description Accumulator X - register Y - register Program Status Word #imm 8-bit Immediate data Direct Page Offset Address !abs Absolute Address Indirect expression Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit Bit Position A.bit...

  • Page 121: Instruction Map

    GMS800 Series A.2 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC #imm dp+X !abs .bit TCALL NOT1...

  • Page 122: Instruction Set

    GMS800 Series A.3 Instruction Set Arithmetic / Logic Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC ADC #imm Add with carry. A ← ( A ) + ( M ) + C ADC dp ADC dp + X ADC !abs NV--H-ZC ADC !abs + Y ADC [ dp + X ]...
  • Page 123 GMS800 Series Byte Cycle Flag Mnemonic Operation Code NVGBHIZC Divide : YA / X Q: A, R: Y NV--H-Z- EOR #imm Exclusive OR A ← ( A ) ⊕ ( M ) EOR dp EOR dp + X EOR !abs N-----Z- EOR !abs + Y EOR [ dp + X ]...
  • Page 124 GMS800 Series Register / Memory Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC LDA #imm Load accumulator A ← ( M ) LDA dp LDA dp + X LDA !abs LDA !abs + Y N-----Z- LDA [ dp + X ] LDA [ dp ] + Y LDA { X } X- register auto-increment : A ←...
  • Page 125 GMS800 Series 16-BIT operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC 16-Bits add without Carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : CMPW dp N-----ZC (YA) −...
  • Page 126 GMS800 Series Branch / Jump Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel Branch if bit set : -------- if ( bit ) = 1 , then pc ←...
  • Page 127 GMS800 Series Control Operation & Etc. Byte Cycle Flag Mnemonic Operation Code NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...

  • Page 128: Mask Order Sheet

    YYWW KOREA If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer’s part number 4. Delivery Schedule Date Quantity MagnaChip Confirmation YYYY Customer sample YYYY Risk order 5. ROM Code Verification Please confirm out verification data.

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