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MagnaChip MC80F0424 User Manual

8-bit single-chip microcontrollers
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查询MC80C0448K供应商
查询MC80C0448K供应商
MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0424/0432/0448
MC80C0424/0432/0448
User's Manual
(Ver. 0.2)

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Summary of Contents for MagnaChip MC80F0424

  • Page 1 查询MC80C0448K供应商 查询MC80C0448K供应商 MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0424/0432/0448 MC80C0424/0432/0448 User’s Manual (Ver. 0.2)
  • Page 2 MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way re- sponsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 3: Table Of Contents

    2. BLOCK DIAGRAM ............................4 3. PIN ASSIGNMENT ............................5 4. PACKAGE DIAGRAM ........................... 7 5. PIN FUNCTION .............................. 9 5.1 MC80F0424/0432/0448 Pin Description ....................10 6. PORT STRUCTURES ..........................13 7. ELECTRICAL CHARACTERISTICS ......................17 7.1 Absolute Maximum Ratings ........................17 7.2 Recommended Operating Conditions ....................
  • Page 4 27.1 Getting Started / Installation ......................117 27.2 Basic ISP S/W Information ........................ 117 27.3 Hardware Conditions to Enter the ISP Mode ..................119 27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board ..........120 INSTRUCTION MAP............................i INSTRUCTION SET............................ii MASK ORDER SHEET...........................

  • Page 5: Overview

    10-bit A/D converter, 8-bit Serial Input/Output, UART, 6-bit buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has 8 high current I/O pins with typical 20mA. In addition, the MC80F0424/0432/0448 supports power saving modes to reduce power consumption.

  • Page 6: Development Tools

    MC80F0424/0432/0448 Preliminary 1.3 Development Tools The MC80F0424/0432/0448 is supported by a full-featured mac- ro assembler, an in-circuit emulator CHOICE-Dr. and OTP programmers. There are two different type of programmers such as single type and gang type. For mode detail, Refer to “25.

  • Page 7: Ordering Information

    48K bytes K : 64SDIP MC80C0448L 1.5K bytes Q : 64QFP MC80F0424K L : 64LQFP MC80F0424Q 24K bytes MC80F0424L MC80F0432K FLASH version MC80F0432Q 32K bytes MC80F0432L MC80F0448K MC80F0448Q 48K bytes MC80F0448L Table 1-1 Ordering Information of MC80F0424/0432/0448 MAR. 2005 Ver 0.2...

  • Page 8: Block Diagram

    MC80F0424/0432/0448 Preliminary 2. BLOCK DIAGRAM R31 / ACLK1 R32 / RxD1 Power ADC Power R33 / TxD1 Supply Supply R00~R07 R20~R23 Data UART1 Memory (1.5K bytes) Program Memory Interrupt Controller Data Table 8-bit Basic System controller Interval Timer System Clock Controller...

  • Page 9: Pin Assignment

    Preliminary MC80F0424/0432/0448 3. PIN ASSIGNMENT AN8 / R70 64SDIP AN9 / R71 R67 / AN7 (Top View) AN10 / R72 R66 / AN6 AN11 / R73 R65 / AN5 AN12 / R74 R64 / AN4 AN13 / R75 R63 / AN3...
  • Page 10 MC80F0424/0432/0448 Preliminary 64LQFP (Top View) AN1 / R61 AN2 / R62 AN3 / R63 AN4 / R64 AN5 / R65 R33 / TxD1 AN7 / R67 R32 / RxD1 AN7 / R67 R31 / ACLK1 MC80F0424/0432/0448L AN8 / R70 AN9 / R71...

  • Page 11: Package Diagram

    Preliminary MC80F0424/0432/0448 4. PACKAGE DIAGRAM 64SDIP UNIT: INCH 2.280 2.260 0.750 Typ. 0.680 0.660 0.050 0.070 BSC 0.022 0-15° 0.016 0.030 64MQFP 24.15 UNIT: MM 23.65 20.10 19.90 0-7° SEE DETAIL “A” 1.03 0.73 3.18 max. 1.95 1.00 BSC 0.50 DETAIL “A”...
  • Page 12 MC80F0424/0432/0448 Preliminary 64LQFP 12.00 BSC 10.00 BSC UNIT: MM 0-7° SEE DETAIL "A" 0.75 0.45 1.60 max. 1.00 0.50 BSC 0.38 0.22 DETAIL "A" MAR. 2005 Ver 0.2...

  • Page 13: Pin Function

    Preliminary MC80F0424/0432/0448 5. PIN FUNCTION : Supply voltage. port with typical 20mA at low level output. In addition, R3 serves the functions of the various following spe- : Circuit ground. cial features such as ACLK1 (UART1 Asynchronous serial clock : Supply voltage to the ladder resistor of ADC circuit.

  • Page 14: Mc80F0424/0432/0448 Pin Description

    Internal pull-up resistor PU4 can be used via software. ACLK0 RxD0 TxD0 INT3 Port 5. 5-bit I/O port. Input Can be set in input or output mode in 1-bit units. PWM1O/T1O PWM3O/T3O Table 5-1 MC80F0424/0432/0448 Pin Description MAR. 2005 Ver 0.2...
  • Page 15 Crystal connection for main system clock oscillation. Output Analog power/reference voltage input to A/D converter. Set the same potential as VDD. Ground potential for A/D converter. Set the same potential as V Positive power supply. Ground potential. Table 5-1 MC80F0424/0432/0448 Pin Description MAR. 2005 Ver 0.2...
  • Page 16 Timer3 PWM Output / Timer 1 Compare Output Input AN0~AN7 Analog input Channel 0 ~ 7 for A/D converter. Input R60~R67 AN8~AN15 Analog input Channel 8 ~ 15 for A/D converter. Input R70~R77 Table 5-2 MC80F0424/0432/0448 Alternate Function Pin Description MAR. 2005 Ver 0.2...

  • Page 17: Port Structures

    Preliminary MC80F0424/0432/0448 6. PORT STRUCTURES R00~R07, R16, R17, R40, R41 R50(INT3),R51(EC1) Data Reg. Direction Pull-up Reg. Pull-up Reg. Data Reg. Data Bus Direction Reg. Noise INT3,EC1 Filter Data Bus INT3_EN,EC1_EN R33(TxD1) TxD1 R10(INT0), R11(INT1), R12(INT2), R15(EC0), Data Reg. R43(SI),R45(ACLK0),R46(RxD0) Direction Reg.
  • Page 18 MC80F0424/0432/0448 Preliminary R31(ACLK1), R32(RxD1) R52(T2O), R53(PWM1O), R54(PWM3O) T2O,PWM1O,PWM3O Data Reg. Data Reg. Direction Reg. Direction Reg. PWM1_EN,T2O_EN Data Bus PWM3_EN Data Bus Noise ACLK1,RxD1 Filter ACLK1_EN, RxD1_EN R13(BUZO), R14(T0O), R47(TxD0) R20, R23, R30~R37 Data Reg. Pull-up Pull-up Reg. Direction Reg.
  • Page 19 Preliminary MC80F0424/0432/0448 R42(SCK) R60~R67(AN0~AN7) Pull-up Pull-up Data Reg. Reg. Direction Reg. Data Reg. Direction Reg. Data Bus SCKO_EN Data Bus AN[7:0] ADC_EN & CH_SEL SCKI_EN Noise Filter R70~R77(AN8~AN15) R44(SO, IOSWIN(SI)) Pull-up Pull-up Reg. Pull-up Data Reg. Pull-up Reg. Direction Reg.
  • Page 20 MC80F0424/0432/0448 Preliminary RESET Mask only Internal Reset STOP MAIN CLOCK R21(SX ), R22(SX Data Reg. Direction Reg. Data Bus XT_EN Data Reg. Direction Reg. Data Bus MAR. 2005 Ver 0.2...

  • Page 21: Electrical Characteristics

    Preliminary MC80F0424/0432/0448 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage............-0.3 to +6.5 V Maximum current (ΣI ) ..........160 mA Storage Temperature ..........-40 to +125 °C Maximum current (ΣI )...........80 mA Voltage on any pin with respect to Ground (V Note: Stresses above those listed under “Absolute Maxi-...

  • Page 22: Dc Electrical Characteristics

    MC80F0424/0432/0448 Preliminary 7.4 DC Electrical Characteristics =-40~85°C, V =5.0V±10%, V =0V, f =8MHz) Parameter Symbol Pin/Condition Min. Typ. Max. Unit INT0, INT1, INT2, INT3, EC0, EC1, 0.8V +0.3 SI, SCK, ACLK0, RxD0, ACLK1, RxD1, RESET Input High Voltage 0.7V +0.3...

  • Page 23: Ac Characteristics

    Preliminary MC80F0424/0432/0448 7.5 AC Characteristics =-40~85°C, V =5V±10%, V =0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Operating Frequency System Clock Cycle 5000 Time Oscillation Stabilizing Time (4MHz) External Clock Pulse Width External Clock Transi- RCP, tion Time Interrupt Pulse Width...

  • Page 24: Serial Interface Timing Characteristics

    MC80F0424/0432/0448 Preliminary 7.6 Serial Interface Timing Characteristics =-40~+85°C, V =5V±10%, V =0V, f =8MHz) Specifications Parameter Symbol Pins Unit Min. Typ. Max. +200 Serial Input Clock Pulse SCYC Serial Input Clock Pulse Width SCKW FSCK Serial Input Clock Pulse Transition Time...

  • Page 25: Typical Characteristic Curves

    Preliminary MC80F0424/0432/0448 7.7 Typical Characteristic Curves This graphs and tables provided in this section are for design The data presented in this section is a statistical summary of data guidance only and are not tested or guaranteed. collected on units from different lots over a period of time. “Typ- ical”...
  • Page 26 MC80F0424/0432/0448 Preliminary −V −V −V SLEEP STOP Main Active Mode Main Active Mode Main Active Mode (mA) (mA) (µA) =25°C =25°C =25°C = 12MHz 8MHz 8MHz = 12MHz = 12MHz, 8MHz, 4MHz 4MHz 4MHz −V −V SLEEP Sub Active Mode1...
  • Page 27 Preliminary MC80F0424/0432/0448 Operating Area (MHz) = -40~85°C Actual Operating Area 2.2~6.5V @ (0.1~8MHz) 3.0~6.5V @ (0.1~16MHz) Spec Operating Area 2.7~5.5V @ (0.4~8MHz) 4.5~5.5V @ (0.4~12MHz) MAR. 2005 Ver 0.2...

  • Page 28: Memory Organization

    MC80F0424/0432/0448 Preliminary 8. MEMORY ORGANIZATION The MC80F0424/0432/0448 has separate address spaces for Pro- ry. Data memory can be read and written to up to 1024 bytes in- gram memory and Data Memory. Program memory can only be cluding the stack area.
  • Page 29 Preliminary MC80F0424/0432/0448 V G B H RESET VALUE: 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE INTERRUPT ENABLE FLAG when G=1, page is selected to “page 1” BRK FLAG HALF CARRY FLAG RECEIVES...

  • Page 30: Program Memory

    MC80F0424/0432/0448 Preliminary At execution of At acceptance At execution At execution a CALL/TCALL/PCALL of interrupt of RET instruction of RET instruction Push 01FF 01FF 01FF 01FF down Push 01FE 01FE 01FE 01FE down 01FD 01FD 01FD 01FD 01FC 01FC 01FC...
  • Page 31 Preliminary MC80F0424/0432/0448 Example: Usage of TCALL ;1BYTE INSTRUCTION TCALL 0FH ;INSTEAD OF 3 BYTES ;NORMAL CALL 4000 ;TABLE CALL ROUTINE 8000 FUNC_A: LDA LRG0 A000 FUNC_B: LDA LRG1 ;TABLE CALL ADD. AREA ;TCALL ADDRESS AREA 0FFC0H FEFF FF00 FUNC_A FUNC_B...
  • Page 32 MC80F0424/0432/0448 Preliminary Address Program Memory PCALL Area Memory Address 0FFC0 0FF00 TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 PCALL Area (256 Bytes) TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3...
  • Page 33 Preliminary MC80F0424/0432/0448 Example: The usage software example of Vector address for MC80F0448. ;Interrupt Vector Table 0FFE0H BIT_TIMER ; BIT WATCH_WDT ; WDT & WT ; AD Converter TIMER4 ; Timer-4 TIMER3 ; Timer-3 TIMER2 ; Timer-2 TIMER1 ; Timer-1 TIMER0 ;...

  • Page 34: Data Memory

    [RETI] restores the contents of the program counter User Memory and flags. The MC80F0424/0432/0448 has 1.5kbytes for the user memory The save/restore locations in the stack are determined by the (RAM). RAM pages are selected by RPR (See Figure 8-9).
  • Page 35 Preliminary MC80F0424/0432/0448 Initial Value Address Register Name Symbol Addressing mode 7 6 5 4 3 2 1 0 00C0 R0 port data register 0 0 0 0 0 0 0 0 byte, bit 00C1 R0 port I/O direction register R0IO...
  • Page 36 MC80F0424/0432/0448 Preliminary Initial Value Address Register Name Symbol Addressing mode 7 6 5 4 3 2 1 0 Timer 3 data register TDR3 1 1 1 1 1 1 1 1 00D9 byte Timer 3 PWM period register T3PPR 1 1 1 1 1 1 1 1...
  • Page 37 Preliminary MC80F0424/0432/0448 Initial Value Address Register Name Symbol Addressing mode 7 6 5 4 3 2 1 0 Basic interval timer register BITR Undefined 00F2 byte Clock control register CKCTLR 0 - 0 1 0 1 1 1 00F3 System clock mode register...
  • Page 38 MC80F0424/0432/0448 Preliminary Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R0 Port Data Register R0IO R0 Port Direction Register R1 Port Data Register R1IO R1 Port Direction Register R2 Port Data Register...
  • Page 39 Preliminary MC80F0424/0432/0448 Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T4H/ TDR4H/ Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High CDR4H IFRX0 IFTX0 IFRX1...

  • Page 40: Addressing Mode

    MC80F0424/0432/0448 Preliminary Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R4 Pull-up Selection Register EE6H ASIMR1 ISRM EE7H ASISR1 EE8H BRGCR1 TPS2 TPS1 TPS0 MLD3 MLD2 MLD1 MLD0 RXR1 UART1 Receive Buffer Register...
  • Page 41 Preliminary MC80F0424/0432/0448 ;A ←RAM[35H] ;A ←ROM[135H] C535 983501 !0135H data 135H data → data → data+1 data 0E550H 0F100H 0E551H 0F101H address: 0135 0F102H 8.4.4 Absolute Addressing → !abs 8.4.5 Indexed Addressing Absolute addressing sets corresponding memory data to Data, i.e.
  • Page 42 MC80F0424/0432/0448 Preliminary D500FA !0FA00H+Y data 0F100H → data 0F101H → 0F102H 0FA00H+55H=0FA55H data 0FA55H → data X indexed direct page (8 bit offset) → dp+X 8.4.6 Indirect Addressing This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page.
  • Page 43 Preliminary MC80F0424/0432/0448 Absolute indirect → [!abs] 1625 [25H+X] The program jumps to address specified by 16-bit absolute ad- dress. Example; G=0 0E005H 1F25E0 [!0C025H] 25 + X(10) = 35H 0E005H data PROGRAM MEMORY 0FA00H 0E025H → A + data + C...

  • Page 44: I/O Ports

    MC80F0424/0432/0448 Preliminary 9. I/O PORTS The MC80F0424/0432/0448 has eight ports (R0, R1, R2, R3, R4, R5, R6 and R7). These ports pins may be multiplexed with an al- ternate function for the peripheral features on the device. R3 port ADDRESS: 0C0...
  • Page 45 Preliminary MC80F0424/0432/0448 R2 and R2IO register: R2 is an 4-bit CMOS bidirectional I/O port (address 0C4 ). Each I/O pin can independently used as an input or an output through the R2IO register (address 0C5 ADDRESS: 0C2 R1 Data Register RESET VALUE: 00 In addition, Port R2 is multiplexed with various special features.
  • Page 46 MC80F0424/0432/0448 Preliminary ADDRESS: 0C8 ADDRESS: 0C6 R4 Data Register R3 Data Register RESET VALUE: 00 RESET VALUE: 00 R47 R46 R45 R44 R43 R42 R41 R40 R37 R36 R35 R34 R33 R32 R31 R30 Input / Output data Input / Output data...
  • Page 47 Preliminary MC80F0424/0432/0448 R6 and R6IO register: R6 is an 8-bit CMOS bidirectional I/O port (address 0CC ). Each I/O pin can independently used as an input or an output through the R6IO register (address 0CD Port Pin Alternate Function In addition, Port R6 is multiplexed with AD converter analog in- AN8 (ADC input channel 8) put AN0~AN7.

  • Page 48: Clock Generator

    MC80F0424/0432/0448 Preliminary 10. CLOCK GENERATOR As shown in Figure 10-1, the clock generator produces the basic system clock control register (SCMR). The registers are shown in clock pulses which provide the system clock to be supplied to the Figure 10-2. In case of selecting sub clock, to oscillate or stop the CPU and the peripheral hardware.
  • Page 49 Preliminary MC80F0424/0432/0448 SCMR (System Clock Mode Register) ADDRESS: 0F3 INITIAL VALUE: ----_-000B CS[1:0] (System clock control) 00: main clock on 01: main clock on 10: sub clock on 11: Setting prohibited MCC (Main System Clock Oscillation Control) 0: Oscillation possible 1: Oscillation stop Note 1.

  • Page 50: Basic Interval Timer

    MC80F0424/0432/0448 Preliminary 11. BASIC INTERVAL TIMER The MC80F0424/0432/0448 has one 8-bit Basic Interval Timer after one machine cycle by hardware. that is free-run and can not stop. Block diagram is shown in Fig- If the STOP instruction executed after writing "1" to bit RCWDT ure 11-1.
  • Page 51 Preliminary MC80F0424/0432/0448 ADDRESS: 0F2 CKCTLR BTCL BTS2 BTS1 BTS0 ADRST RCWDT WDTON BTCL INITIAL VALUE: 0-010111 Basic Interval Timer source clock select ÷ 000: f ÷ 001: f ÷ 010: f ÷ 011: f ÷ 100: f ÷ 101: f ÷...

  • Page 52: Watchdog Timer

    MC80F0424/0432/0448 Preliminary 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU The RC oscillated watchdog timer is activated by setting the bit to the normal state. The watchdog timer signal for detecting mal- RCWDT as shown below.
  • Page 53 Preliminary MC80F0424/0432/0448 Watchdog Timer Control counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to Figure 12-2 shows the watchdog timer control register. The low to reset the internal hardware. When WDTON=0, a watchdog watchdog timer is automatically disabled after reset.
  • Page 54 MC80F0424/0432/0448 Preliminary Source clock BIT overflow Binary-counter Counter Counter Clear Clear WDTR Match Detect WDTIF interrupt WDTR ← “1000_0011 ” WDT reset reset Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, reset is generated in sub clock mode.

  • Page 55: Watch Timer

    Preliminary MC80F0424/0432/0448 13. WATCH TIMER The watch timer generates interrupt for watch operation. The into stop mode, the main-clock is stopped and then watch timer is watch timer consists of the clock selector, 15-bit binary counter, also stopped. If the sub clock’s oscillation is enabled by XTEN interval selector and watch timer mode register.

  • Page 56: Timer/Event Counter

    MC80F0424/0432/0448 Preliminary 14. TIMER/EVENT COUNTER The MC80F0424/0432/0448 has five Timer/Counter registers. counter function. When external interrupt edge input, the count Each module can generate an interrupt to indicate that an event register is captured into capture data register CDRx. has occurred (i.e. timer match).
  • Page 57 Preliminary MC80F0424/0432/0448 CAP4 T4CK[2:0] TIMER 4 16-bit Timer 16-bit Capture Table 14-3 Operating Modes of Timer 4 1. X: The value “0” or “1” corresponding to user operation. MAR. 2005 Ver 0.2...
  • Page 58 MC80F0424/0432/0448 Preliminary ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --000000 Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag ÷ T0CK2 TM0.4 000: 8-bit Timer, Clock source is f T0CK1 TM0.3...
  • Page 59 Preliminary MC80F0424/0432/0448 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 Bit Name Bit Position Description CAP2 TM2.5 0: Timer/Counter mode 1: Capture mode selection flag ÷ T2CK2 TM2.4 000: 8-bit Timer, Clock source is f T2CK1 TM2.3...

  • Page 60: 8-Bit Timer / Counter Mode

    Figure 14-3 TM4 Registers 14.1 8-bit Timer / Counter Mode The MC80F0424/0432/0448 has four 8-bit Timer/Counters, Tim- be cleared to "0"(Figure 14-4). These timers have each 8-bit er 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown count register and data register.
  • Page 61 Preliminary MC80F0424/0432/0448 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --000000 X means the value of "0" or "1" corresponding to user operation ADDRESS: 0D2 16BIT CAP1 T1CK1 BTCL T1CK0 T1CN T1ST PWM1E INITIAL VALUE: 00 T0CK[2:0]...
  • Page 62 MC80F0424/0432/0448 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means the value of "0" or "1" corresponding to user operation ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 T2CK[2:0]...
  • Page 63 Preliminary MC80F0424/0432/0448 Example 1: These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock in- Timer0 = 2ms 8-bit timer mode at 4MHz put. The internal clock has a prescaler divide ratio option of 2, 4, Timer1 = 0.5ms 8-bit timer mode at 4MHz...
  • Page 64 MC80F0424/0432/0448 Preliminary Example: Make 1ms interrupt using by Timer0 at 4MHz TM0,#0FH ; divide by 32 TDR0,#124 ; 8us x (124+1)= 1ms SET1 ; Enable Timer 0 Interrupt ; Enable Master Interrupt When TM0 = 0000 1111 (8-bit Timer mode, Prescaler divide ratio = 32)
  • Page 65 Preliminary MC80F0424/0432/0448 TDR1 enable disable clear & start stop TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt T1ST T1ST = 1 Start & Stop T1ST = 0 T1CN T1CN = 1 Control count T1CN = 0 Figure 14-9 Count Operation of Timer / Event counter...

  • Page 66: 16-Bit Timer / Counter Mode

    MC80F0424/0432/0448 Preliminary 14.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit timer/ T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively counter register T0, T1 are incremented from 0000 until it as shown in Figure 14-11.

  • Page 67: 8-Bit Compare Output (16-Bit)

    Figure 14-11 16-bit Timer/Counter for Timer 2, 3 14.3 8-bit Compare Output (16-bit) The MC80F0424/0432/0448 has a function of Timer Compare These Compare output pins output the signal having a 50:50 duty Output. To pulse out, the timer match can goes to port pin(T0O, square wave, and output frequency is same as below equation.

  • Page 68: 8-Bit Capture Mode

    MC80F0424/0432/0448 Preliminary In addition, 16-bit Compare output mode is available, also. ADDRESS: 0DC CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST INITIAL VALUE: 00 X means the value of "0" or "1" corresponding to user operation T4CK[2:0] ÷ 2 ÷ 4...
  • Page 69 Preliminary MC80F0424/0432/0448 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --000000 X means the value of "0" or "1" corresponding to user operation ADDRESS: 0D2 16BIT CAP1 T1CK1 BTCL T1CK0 T1CN T1ST PWM1E INITIAL VALUE: 00 T0CK[2:0]...
  • Page 70 MC80F0424/0432/0448 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means the value of "0" or "1" corresponding to user operation ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 T2CK[2:0]...
  • Page 71 Preliminary MC80F0424/0432/0448 This value is loaded to CDR0 TIME Ext. INT0 Pin Interrupt Request ( INT0IF ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0IF ) 20nS Delay Clear & Start Capture ( Timer Stop ) Figure 14-15 Input Capture Operation of Timer 0 Capture mode Ext.

  • Page 72: 16-Bit Capture Mode

    MC80F0424/0432/0448 Preliminary 14.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits Timer register is being run will 16 bits. The clock source of the T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1"...
  • Page 73 Preliminary MC80F0424/0432/0448 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means the value of "0" or "1" corresponding to user operation ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 T2CK[2:0]...
  • Page 74 MC80F0424/0432/0448 Preliminary ADDRESS: 0DC CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST INITIAL VALUE: 00 X means the value of "0" or "1" corresponding to user operation T4CK[2:0] ÷ 2 ÷ 4 T4ST ÷ 8 0: Stop 1: Clear and start ÷...

  • Page 75: Pwm Mode

    Preliminary MC80F0424/0432/0448 14.6 PWM Mode The MC80F0424/0432/0448 has a high speed PWM (Pulse Table 14-4 shows the relation of PWM frequency vs. resolution. Width Modulation) functions which shared with Timer1 and If it needed more higher frequency of PWM, it should be reduced Timer3.
  • Page 76 MC80F0424/0432/0448 Preliminary ADDRESS : D2 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : 00000000 ADDRESS : D5 T1PWHR T1PWHR3 T1PWHR2 T1PWHR1 T1PWHR0 RESET VALUE : ----0000 Bit Manipulation Not Available Period High Duty High X : The value "0" or "1" corresponding to user operation.
  • Page 77 Preliminary MC80F0424/0432/0448 ADDRESS : D8H 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST RESET VALUE : 00000000 ADDRESS : DBH T3PWHR T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 RESET VALUE : ----0000 Bit Manipulation Not Available Period High Duty High X : The value "0" or "1" corresponding to user operation.
  • Page 78 MC80F0424/0432/0448 Preliminary Source clock PWM1E T1ST T1CN PWM1O [POL=1] PWM1O [POL=0] Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ] T1CK[1:0] = 00 ( XIN ) T1PWHR3 T1PWHR2 T1PPR (8-bit)

  • Page 79: Analog To Digital Converter

    Preliminary MC80F0424/0432/0448 15. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an ADCRH and ADCRL contains the results of the A/D conversion. analog input signal to a corresponding 10-bit digital value. The A/ When the conversion is completed, the result is loaded into the...
  • Page 80 MC80F0424/0432/0448 Preliminary (4) AV pin input impedance parallel connection to the series resistor string between the AV pin and the AV pin, and there will be a large analog supply volt- A series resistor string of approximately 5KΩ is connected be- age error.
  • Page 81 Preliminary MC80F0424/0432/0448 ADDRESS: 0EF ADCM BTCL ADEN ADCK ADS2 ADS2 ADS1 ADS0 ADST ADSF INITIAL VALUE: 00-0 0001 A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion.

  • Page 82: Serial Input/Output (Sio)

    MC80F0424/0432/0448 Preliminary 16. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit data se- control circuit as illustrated in Figure 16-1. The SO pin is de- rially. The Serial Input/Output(SIO) module is a serial interface signed to input and output. So the Serial I/O(SIO) can be operated useful for communicating with other peripheral of microcontrol- with minimum two pin.

  • Page 83: Transmission/Receiving Timing

    Preliminary MC80F0424/0432/0448 Serial I/O Mode Register(SIOM) controls serial I/O function. Ac- Serial I/O Data Register(SIOR) is an 8-bit shift register. First cording to SCK1 and SCK0, the internal clock or external clock LSB is send or is received. can be selected.
  • Page 84 MC80F0424/0432/0448 Preliminary SIOST SCK [R42] (POL=0) SO [P44] SI [R43] (IOSW=0) IOSWIN [P44] (IOSW=1) SIOSF (SIO Status) SIOIF (SIO Int. Req) Figure 16-3 Serial I/O Timing Diagram at POL=0 SIOST SCK [R42] (POL=1) SO [R44] SI [R43] (IOSW=0) IOSWIN [R44]...

  • Page 85: The Method Of Serial I/O

    Preliminary MC80F0424/0432/0448 16.2 The method of Serial I/O 1. Select transmission/receiving mode. SIOR,#0AAh ;set tx data 2. In case of sending mode, write data to be send to SIOR. SIOM,#0011_1100b ;set SIO mode 3. Set SIOST to “1” to start serial transmission.

  • Page 86: Universal Asynchronous Receiver/Transmitter (Uart)

    MC80F0424/0432/0448 Preliminary 17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 17.1 UART Serial Interface Functions The Universal Asynchronous Receiver/Transmitter(UART) en- In operation of UART0 and UART1, their operations are same as ables full-duplex operation wherein one byte of data after the start UART0 and UART1 bit is transmitted and received.

  • Page 87: Serial Interface Configuration

    Preliminary MC80F0424/0432/0448 RECEIVE ACLK0 PIN / ACLK1 PIN 5-bit counter /2 ~ f /128 match Tx_Clock (Divider) Decoder match Rx_Clock (Divider) TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 (BRGCR / BRGCR1) 5-bit counter Internal Data Bus SEND Figure 17-2 Baud Rate Generator Block Diagram 17.2 Serial Interface Configuration...
  • Page 88 MC80F0424/0432/0448 Preliminary Asynchronous serial interface mode register Asynchronous serial interface status register (ASIMR) (ASISR) This is an 8 bit register that controls UART serial transfer opera- When a receive error occurs during UART mode, this register in- tion. ASIMR is set by a 1 bit or 8 bit memory manipulation in- dicates the type of error.

  • Page 89: Communication Operation

    Preliminary MC80F0424/0432/0448 Address : 0E8H / EE8H Reset value : -0010000B BRGCR / TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 BRGCR1 TPS2 TPS1 TPS0 Source Clock Selection for 5 Bit count MDL3 MDL2 MDL1 MDL0 Input Clock Selection ACLK0 / ACLK1...

  • Page 90: Relationship Between Main Clock And Baud Rate

    MC80F0424/0432/0448 Preliminary s t i l l t r a n s f e r r e d t o R X R . W h e n b i t 1 ( I S R M ) o f ASIMR(ASIMR1) is cleared to 0 upon occurrence of an error, in- terrupt by Rx occurs.

  • Page 91: Communication Operation

    Preliminary MC80F0424/0432/0448 17.5 Communication operation The transmit operation is enabled when bit 7 (TXE) of the asyn- in Figure 17-1. chronous serial interface mode register (ASIMR/ASIMR1) is set to 1. The transmit operation is started when transmit data is writ- ten to the transmit shift register (TXR/TXR1).

  • Page 92: Buzzer Function

    MC80F0424/0432/0448 Preliminary 18. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, buzzer The bit 0 to 5 of BUZR determines output frequency for buzzer register BUZR, and clock source selector. It generates square- driving. wave which has very wide range frequency (488Hz ~ 250kHz at Equation of frequency calculation is shown below.
  • Page 93 Preliminary MC80F0424/0432/0448 The 6-bit counter is cleared and starts the counting by writing sig- nal at BUZR register. It is incremental from 00 until it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below Table 18-1.

  • Page 94: Interrupts

    MC80F0424/0432/0448 Preliminary 19. INTERRUPTS The MC80F0424/0432/0448 interrupt circuits consist of Interrupt T2IF, T3IF and T4IF which is set by a match in their respective enable register (IENH, IENL), Interrupt request flags of IRQH, timer/counter register. IRQL, Priority circuit, and Master enable flag (“I” flag of PSW).
  • Page 95 Preliminary MC80F0424/0432/0448 The UART receive/transmit interrupt is generated by UART0IF and UART1IF which are set by completion of UART data recep- tion or transmission. Reset/Interrupt Symbol Priority The SIO interrupt is generated by SIOIF which is set by comple- Hardware Reset RESET tion of SIO data reception or transmission.

  • Page 96: Interrupt Sequence

    MC80F0424/0432/0448 Preliminary ADDRESS: 0EC IRQH INT0IF INT1IF INT2IF INT3IF SIOIF T0IF UART0IF UART1IF INITIAL VALUE: 0000 0000 Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag UART1Tx/Rx interrupt request flag UART0 Tx/Rx interrupt request flag External interrupt 3 request flag...
  • Page 97 Preliminary MC80F0424/0432/0448 19.1.1 Interrupt acceptance and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any follow- 4.

  • Page 98: Brk Interrupt

    MC80F0424/0432/0448 Preliminary ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. main task RETI ;RETURN acceptance of interrupt interrupt service task General-purpose register save/restore using push and pop instruc- saving registers tions; restoring registers interrupt return 19.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order.

  • Page 99: Multi Interrupt

    Preliminary MC80F0424/0432/0448 UART0(UART1) Interrupt Request WDT or WT IFTX0(IFTX1) Interrupt Request TX0(TX1) Interrupt Routine IFWDT IFWT Clear IFTX0(IFTX1) WDT Interrupt WT Interrupt Routine Routine IFRX0(IFRX1) Clear IFWDT Clear IFWT RX0(RX1) Interrupt Routine RETI Clear IFRX0(IFRX1) RETI Figure 19-6 Software Flowchart of Shared Interrupt Vector 19.4 Multi Interrupt...

  • Page 100: External Interrupt

    MC80F0424/0432/0448 Preliminary Main Program service TIMER 1 service INT0 service enable INT0 disable other Occur Occur TIMER1 interrupt INT0 enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress.
  • Page 101 Preliminary MC80F0424/0432/0448 Response Time twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every first instruction of the service routine.

  • Page 102: Operation Mode

    MC80F0424/0432/0448 Preliminary 20. OPERATION MODE The system clock controller starts or stops the main-frequency Sub Active mode clock oscillator and switches between the main and sub frequency This mode is low-frequency operating mode. In this mode, the clock. The operating mode is generally divided into the main ac-...

  • Page 103: Operation Mode Switching

    SET pin to low, which immediately performs the reset operation. tion stops and the CPU clock stops and other peripherals are stop After reset, the MC80F0424/0432/0448 is placed in Main active too. But sub-frequency clock oscillation operate continuously if mode.
  • Page 104 MC80F0424/0432/0448 Preliminary Main freq. clock pin) Sub freq. clock pin) Operation clock Main-clock operation Sub-clock operation Changed to the Sub-clock SCMR ← XXXX X010 Turn off main clock SCMR.2 bit HIGH (a) Main active mode → Sub active mode 1 → Sub active mode 2 Main freq.

  • Page 105: Power Saving Operation

    Preliminary MC80F0424/0432/0448 21. POWER SAVING OPERATION The MC80F0424/0432/0448 has two power-down modes. In and SLEEP mode. Table 21-1 shows the status of each Power power-down mode, power consumption is reduced considerably. Saving Mode. SLEEP mode is entered by the SSCR register to For applications where power consumption is a critical factor, de- “0Fh”., and STOP mode is entered by STOP instruction after the...

  • Page 106: Stop Mode

    MC80F0424/0432/0448 Preliminary Oscillator pin) Clock External Interrupt SLEEP Instruction Executed Normal Operation SLEEP Operation Normal Operation Figure 21-2 SLEEP Mode Release Timing by External Interrupt Oscillator pin) Clock RESET Internal RESET SLEEP Instruction Stabilization Time Execution = 65.5mS @4MHz Normal Operation...
  • Page 107 Preliminary MC80F0424/0432/0448 The reset should not be activated before V is restored to its with the oscillator and the internal hardware is lowered; however, normal operating level, and must be held active long enough to the power dissipation associated with the pin interface (depend- allow the oscillator to restart and stabilize.
  • Page 108 MC80F0424/0432/0448 Preliminary 20msec). This guarantees that oscillator has started and stabi- By reset, exit from Stop mode is shown in Figure 21-6. lized. STOP INSTRUCTION STOP Mode Interrupt Request Corresponding Interrupt IENH or IENL ? Enable Bit (IENH, IENL) STOP Mode Release...

  • Page 109: Stop Mode At Internal Rc-Oscillated Watchdog Timer Mode

    Preliminary MC80F0424/0432/0448 STOP Mode Oscillator (XI pin) Internal Clock RESET Internal RESET STOP Instruction Execution Stabilization Time Time can not be control by software = 65.5mS @4MHz Figure 21-6 Timing of STOP Mode Release by Reset 21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip er.
  • Page 110 MC80F0424/0432/0448 Preliminary Oscillator pin) Internal RC Clock Internal Clock External Interrupt ( or WDT Interrupt ) Clear Basic Interval Timer STOP Instruction Execution Counter Normal Operation Stabilization Time STOP mode Normal Operation at RC-WDT Mode > 20mS Figure 21-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt...

  • Page 111: Minimizing Current Consumption

    Preliminary MC80F0424/0432/0448 21.4 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To off output drivers that are sourcing or sinking current, if it is prac- minimize current drawn during Stop mode, the user should turn- tical.
  • Page 112 MC80F0424/0432/0448 Preliminary no current flow after considering its relationship with external If it is not appropriate to set as an input mode, then set to output circuit. In input mode, the pin impedance viewing from external mode considering there is no current flow. The port setting to MCU is very high that the current doesn’t flow.

  • Page 113: Oscillator Circuit

    Preliminary MC80F0424/0432/0448 22. OSCILLATOR CIRCUIT The MC80F0424/0432/0448 has two oscillation circuits internal- Note: When using the sub clock oscillation, connect a re- ly. X and X are input and output for frequency, and SX sistor in series with R which is shown as below Figure 22-...

  • Page 114: Reset

    MC80F0424/0432/0448 Preliminary 23. RESET The MC80F0424/0432/0448 have four types of reset generation set, power fail processor reset, and address fail reset. Table 23-1 procedures; they are an external reset input, a watch-dog timer re- shows on-chip hardware initialization by reset action.

  • Page 115: Power Fail Processor

    Preliminary MC80F0424/0432/0448 24. POWER FAIL PROCESSOR The MC80F0424/0432/0448 has an on-chip power fail detection Note: If power fail voltage is selected to 2.4V or 2.7V on circuitry to immunize against power noise. A configuration reg- below 3V operation, MCU is freezed at all the times.
  • Page 116 MC80F0424/0432/0448 Preliminary RESET VECTOR PFDS =1 RAM Clear Initialize RAM Data PFDS = 0 Skip the Initialize All Ports initial routine Initialize Registers Function Execution Figure 24-2 Example S/W of Reset flow by Power fail 65.5mS Internal RESET When PFDM = 1 65.5mS...

  • Page 117: Flash Programming

    Preliminary MC80F0424/0432/0448 25. FLASH PROGRAMMING The Device Configuration Area can be programmed or left un- ble and writable during FLASH program / verify mode. The De- programmed to select device configuration such as security bit. vice Configuration Area register is located at the address 20FFH.

  • Page 118: Emulator Eva. Board Setting

    MC80F0424/0432/0448 Preliminary 26. Emulator EVA. Board Setting þ“ à ÃÕŒœ–— MAR. 2005 Ver 0.2...
  • Page 119 This connector is only used for a device over 32 PIN. Used for the MC80F0424/0432/0448. This connector is only used for a device under 32 PIN. Not used for the MC80F0424/0432/0448. Must be ON position. ON : MC80F0424/0432/0448 selection OFF : other MCU selection Eva.
  • Page 120 This switch select the Normal I/O port(on&off) or special function These switches select the R34 or X select(off&on). It is not used for the MC80F0424/0432/ 0448. These switches select the R35 or /Reset This is for External Clock(CAN Type. This is External oscillation socket(CAN Type. OSC) OSC).

  • Page 121: In-System Programming (Isp)

    D must be configured to enter the ISP mode. 1. Connect the serial(RS-232C) cable between a target 4. Run the MagnaChip ISP software. board and the COM port of your PC. 5. Press the Reset Button in the ISP S/W. If the status win- 2.
  • Page 122 MC80F0424/0432/0448 Preliminary Function Description Load HEX File Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format.

  • Page 123: Hardware Conditions To Enter The Isp Mode

    Preliminary MC80F0424/0432/0448 27.3 Hardware Conditions to Enter the ISP Mode The In-System Programming (ISP) is performed without remov- minimum of additional expense in components and circuit board ing the microcontroller from the target system. The In-System area. The boot loader can be executed by holding ALEB high,...

  • Page 124: Reference Isp Circuit Diagram And Magnachip Supplied Isp Board

    MC80F0424/0432/0448 Preliminary 27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board The ISP software and hardware circuit diagram are provided at partment. The following circuit diagram is for reference use.. www.magnachipmcu.com . To get a ISP B/D, contact to sales de- 2N2907 100Ω...
  • Page 125 Preliminary MC80F0424/0432/0448 APPENDIX MAR. 2005 Ver 0.2...

  • Page 127: Instruction Map

    MC80F0424/0432/0448 A. INSTRUCTION MAP 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC “ “ “ #imm...

  • Page 128: Instruction Set

    MC80F0424/0432/0448 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC ADC #imm Add with carry. A ← ( A ) + ( M ) + C ADC dp ADC dp + X NV--H-ZC ADC !abs...
  • Page 129 MC80F0424/0432/0448 BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC EOR #imm Exclusive OR A ← ( A ) ⊕ ( M ) EOR dp EOR dp + X EOR !abs N-----Z- EOR !abs + Y EOR [ dp + X ]...
  • Page 130 MC80F0424/0432/0448 2. REGISTER / MEMORY OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC LDA #imm Load accumulator A ← ( M ) LDA dp LDA dp + X LDA !abs LDA !abs + Y N-----Z- LDA [ dp + X ]...
  • Page 131 MC80F0424/0432/0448 3. 16-BIT OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION NVGBHIZC CODE 16-Bits add without carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : CMPW dp N-----ZC (YA) −...
  • Page 132 MC80F0424/0432/0448 5. BRANCH / JUMP OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel...
  • Page 133 MC80F0424/0432/0448 6. CONTROL OPERATION & etc. BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...

  • Page 134: Mask Order Sheet

    MC80F0424/0432/0448 C. MASK ORDER SHEET Refer to next page. viii MAR. 2005 Ver 0.2...
  • Page 135 YYWW KOREA If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer’s part number 4. Delivery Schedule Date Quantity MagnaChip Confirmation YYYY Customer sample YYYY Risk order 5. ROM Code Verification Please confirm out verification data.

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