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MagnaChip MC80F0104 User Manual

8-bit single-chip microcontrollers
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MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0104/0204
MC80C0104/0204
Preliminary User's Manual
(Ver. 0.2)

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  • Page 1 MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0104/0204 MC80C0104/0204 Preliminary User’s Manual (Ver. 0.2)
  • Page 2 MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way re- sponsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 3: Table Of Contents

    Preliminary MC80F0104/0204 1. OVERVIEW ..............................1 Description ..............................1 Features ................................1 Development Tools ............................2 Ordering Information ..........................3 2. BLOCK DIAGRAM ............................4 3. PIN ASSIGNMENT ............................5 4. PACKAGE DRAWING ............................. 6 5. PIN FUNCTION ..............................8 6.
  • Page 4 Getting Started / Installation ........................107 Basic ISP S/W Information .......................... 107 Hardware Conditions to Enter the ISP Mode ....................109 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board ............110 27. A. INSTRUCTION MAP ..........................i 28. B. INSTRUCTION SET ..........................ii 1.

  • Page 5: Overview

    1. OVERVIEW 1.1 Description The MC80F0104/0204 is advanced CMOS 8-bit microcontroller with 4K bytes of FLASH. This is a powerful microcontrol- ler which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 4K bytes of FLASH, 256 bytes of RAM, 8/16-bit timer/counter, watchdog timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry.

  • Page 6: Development Tools

    - Internal Oscillator (4MHz/2MHz) • Power Saving Modes - STOP mode 1.3 Development Tools The MC80F0104/0204 is supported by a full-featured macro as- sembler, an in-circuit emulator CHOICE-Dr. and OTP pro- grammers. There are two different type of programmers such as single type and gang type.

  • Page 7: Ordering Information

    Preliminary MC80F0104/0204 1.4 Ordering Information Device name ROM Size RAM size Package MC80C0204B 4K bytes 20PDIP MC80C0204D 4K bytes 20SOP Mask version 256 bytes MC80C0104B 4K bytes 16PDIP MC80C0104D 4K bytes 16SOP MC80F0204B 4K bytes FLASH 20PDIP MC80F0204D 4K bytes FLASH...

  • Page 8: Block Diagram

    MC80F0104/0204 Preliminary 2. BLOCK DIAGRAM Accumulator Stack Pointer Data Memory Program RESET System controller Memory System 8-bit Basic Data Table Clock Controller Interval Interrupt Controller Timer Timing generator Clock Generator Instruction Decoder 10-bit 8-bit High Buzzer Watch-dog Timer/ Speed SIO/UART...

  • Page 9: Pin Assignment

    Preliminary MC80F0104/0204 3. PIN ASSIGNMENT MC80F0204B/0204D 20 PDIP 20 SOP R04 / AN4 / EC0 / RXD R03 / AN3 / INT2 R05 / AN5 / T0O / TXD R02 / AN2 / SOUT R06 / AN6 / T2O / ACLK...

  • Page 10: Package Drawing

    MC80F0104/0204 Preliminary 4. PACKAGE DRAWING 20 PDIP unit: inch 1.043 TYP 0.300 1.010 0.270 0.245 0.021 0 ~ 15° 0.065 TYP 0.100 0.015 0.050 20 SOP 0.5118 0.4961 0 ~ 8° 0.020 0.042 0.013 TYP 0.050 0.016 Mar. 2005 Ver 0.2...
  • Page 11 Preliminary MC80F0104/0204 16 PDIP unit: inch TYP 0.300 0.765 0.260 0.745 0.240 0.022 0 ~ 15° 0.065 TYP 0.100 0.015 0.050 16 SOP 0.412 0.402 0.019 0 ~ 8° 0.040 0.014 TYP 0.050 0.016 Mar. 2005 Ver 0.2...

  • Page 12: Pin Function

    MC80F0104/0204 Preliminary 5. PIN FUNCTION : Supply voltage. R10~R14: R1 is a 5-bit, CMOS, bidirectional I/O port. R1 pins can be used as outputs or inputs according to “1” or : Circuit ground. “0” written the their Port Direction Register (R1IO).
  • Page 13 Preliminary MC80F0104/0204 Pin No. PIN NAME In/Out Function (20PDIP) Supply voltage Circuit ground Input only port RESET (R35) Reset signal input I ( I ) Normal I/O Port (R33) Oscillation Input I (I/O) (R34) Normal I/O Port Oscillation Output O (I/O)

  • Page 14: Port Structures

    MC80F0104/0204 Preliminary 6. PORT STRUCTURES R13~R14 R01 (AN1 / SI) Pull-up Pull-up Pull-up Reg. Pull-up Reg. Open Drain Reg. Open Drain Reg. Data Reg. Data Reg. Direction Reg. Direction Reg. Data Bus Data Bus AN[1] ADEN & ADS[3:0] (ADCM) Noise...
  • Page 15 Preliminary MC80F0104/0204 R04 (AN4 / EC0 / RXD) R02 (AN2 / SOUT) Pull-up Pull-up Pull-up Pull-up Reg. Reg. Open Drain Open Drain Reg. Reg. Data Reg. Data Reg. Direction SOUT Reg. SO_EN(SIOM) Data Bus Direction Reg. Data Bus AN[1] ADEN & ADS[3:0]...
  • Page 16 MC80F0104/0204 Preliminary R06 (AN6 / T2O / ACLK) R05 (AN5 / T0O / TXD) Pull-up Pull-up Pull-up Pull-up Reg. Reg. Open Drain Open Drain Reg. Reg. Data Reg. Data Reg. T0OE(PSR1.0) T2OE(PSR1.1) TXE(ASIMR.7) Direction Direction Reg. Reg. Data Bus Data Bus...
  • Page 17 Preliminary MC80F0104/0204 (Crystal or Ceramic Resonator) R33 (X ), R34 (X Pull-up Pull-up Reg. Open Drain Reg. STOP Data Reg. Direction Reg. / R33 MAIN CLOCK Data Bus IN4MCLK IN2MCLK IN4MCLKXO IN2MCLKXO CLOCK option (Configuration option bit) (External RC or R oscillation)

  • Page 18: Electrical Characteristics

    MC80F0104/0204 Preliminary 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ..........-0.3 to +6.5 V ................. 10 mA Storage Temperature ........-65 to +150 °C Maximum current (ΣI ) ........160 mA Voltage on any pin with respect to Ground (V Maximum current (ΣI...

  • Page 19: Dc Electrical Characteristics

    Preliminary MC80F0104/0204 7.4 DC Electrical Characteristics =-40~85°C, V =5.0V =0V) Specifications Parameter Symbol Condition Unit Min. Typ. Max. , RESET 0.8 V 0.8 V Input High Voltage Hysteresis Input Normal Input 0.7 V , RESET 0.2 V 0.2 V Input Low Voltage...

  • Page 20: Ac Characteristics

    MC80F0104/0204 Preliminary 7.5 AC Characteristics =-40~+85°C, V =5V±10%, V =0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Operating Frequency External Clock Pulse Width External Clock Transition Time RCP, Oscillation Stabilizing Time INT0, INT1, INT2, INT3 External Input Pulse Width...

  • Page 21: Typical Characteristics

    Preliminary MC80F0104/0204 7.6 Typical Characteristics These graphs and tables provided in this section are for de- The data presented in this section is a statistical summary sign guidance only and are not tested or guaranteed. of data collected on units from different lots over a period of time.

  • Page 22: Memory Organization

    MC80F0104/0204 Preliminary 8. MEMORY ORGANIZATION The MC80F0104/0204 has separate address spaces for Data memory can be read and written to up to 256 bytes in- Program memory and Data Memory. 4K bytes program cluding the stack area. memory can only be read, not written to.
  • Page 23 Preliminary MC80F0104/0204 V G B H RESET VALUE: 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE INTERRUPT ENABLE FLAG when G=1, page is selected to “page 1” BRK FLAG HALF CARRY FLAG RECEIVES...
  • Page 24 MC80F0104/0204 Preliminary At execution of At acceptance At execution At execution a CALL/TCALL/PCALL of interrupt of RET instruction of RET instruction Push 01FF 01FF 01FF 01FF down Push 01FE 01FE 01FE 01FE down 01FD 01FD 01FD 01FD 01FC 01FC 01FC...

  • Page 25: Program Memory

    Preliminary MC80F0104/0204 8.2 Program Memory A 16-bit program counter is capable of addressing up to Example: Usage of TCALL 64K bytes, but this device has 4K bytes program memory space only physically implemented. Accessing a location above FFFF will cause a wrap-around to 0000 ;1BYTE INSTRUCTION...
  • Page 26 MC80F0104/0204 Preliminary Address Program Memory PCALL Area Memory Address 0FFC0 0FF00 TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 PCALL Area (256 Bytes) TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3...
  • Page 27 Preliminary MC80F0104/0204 Example: The usage software example of Vector address for MC80F0204. ;Interrupt Vector Table 0FFE0H BIT_TIMER ; BIT ; WDT ; AD Converter Not_used TIMER3 ; Timer-3 TIMER2 ; Timer-2 TIMER1 ; Timer-1 TIMER0 ; Timer-0 ; Serial Interface ;...

  • Page 28: Data Memory

    User Memory When returning from the processing routine, executing the The MC80F0104/0204 has 256 × 8 bits for the user mem- subroutine return instruction [RET] restores the contents of ory (RAM). RAM pages are selected by RPR (See Figure the program counter from the stack;...
  • Page 29 Preliminary MC80F0104/0204 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00C0 R0 port data register 0 0 0 0 0 0 0 0 byte, bit 00C1 R0 port I/O direction register R0IO...
  • Page 30 MC80F0104/0204 Preliminary Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00E1 RAM page selection register - - - - - 0 0 0 byte, bit 00E2 SIO mode control register SIOM 0 0 0 0 0 0 0 1...
  • Page 31 Preliminary MC80F0104/0204 Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0C0H R0 Port Data Register 0C1H R0IO R0 Port Direction Register 0C2H R1 Port Data Register 0C3H R1IO R1 Port Direction Register...
  • Page 32 MC80F0104/0204 Preliminary Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0ECH IRQH INT0IF INT1IF INT2IF INT3IF RXIF TXIF SIOIF T0IF 0EDH IRQL T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF...

  • Page 33: Addressing Mode

    Preliminary MC80F0104/0204 8.4 Addressing Mode 8.4.3 Direct Page Addressing→ dp The HMS800 series MCU uses six addressing modes; • Register addressing In this mode, a address is specified within direct page. • Immediate addressing Example; G=0 ;A ←RAM[35H] • Direct page addressing C535 •...
  • Page 34 MC80F0104/0204 Preliminary ;A ←ROM[135H] 983501 !0135H ➋ data data 135H ➌ data → ➊ → ➋ data+1 → data 0F100H ➊ 0F101H address: 0135 0F102H X indexed direct page (8 bit offset) → dp+X 8.4.5 Indexed Addressing This address value is the second byte (Operand) of com- mand plus the data of X-register.
  • Page 35 Preliminary MC80F0104/0204 D500FA !0FA00H+Y 1625 [25H+X] 0F100H ➊ 0F101H ➋ 0E005H 0F102H 0FA00H+55H=0FA55H ➊ 25 + X(10) = 35H 0E005H data ➋ 0FA55H data data → ➌ 0FA00H ➌ A + data + C → 8.4.6 Indirect Addressing Y indexed indirect → [dp]+Y Direct page indirect →...
  • Page 36 MC80F0104/0204 Preliminary 1F25E0 [!0C025H] PROGRAM MEMORY 0E025H 0E026H ➋ jump to address 0E30AH ➊ 0E725H NEXT 0FA00H Mar. 2005 Ver 0.2...

  • Page 37: I/O Ports

    Preliminary MC80F0104/0204 9. I/O PORTS The MC80F0104/0204 has three ports (R0, R1 and R3). its initial status is input. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. All port can drive maximum 20mA of high current in output low WRITE “55...

  • Page 38: R1 And R1Io Register

    MC80F0104/0204 Preliminary Figure 9-2 R0 Port Register In addition, Port R0 is multiplexed with various alternate functions. The port selection register PSR0 (address 0F8 Port Pin Alternate Function and PSR1 (address 0F9 ) control the selection of alternate functions such as external interrupt 3 (INT3), external in-...
  • Page 39 Preliminary MC80F0104/0204 ADDRESS: 0F8 RESET VALUE: 0000 0000 ADDRESS: 0C2 R1 Data Register RESET VALUE: ---0 0000 PSR0 EC1E EC0E INT3E INT2E INT1E INT0E PWM3OE PWM1OE R14 R13 R12 R11 R10 Port / INT Selection Input / Output data 0: R11, R12, R03, R00...

  • Page 40: R3 And R3Io Register

    MC80F0104/0204 Preliminary 9.3 R3 and R3IO register R3 is a 5-bit CMOS bidirectional I/O port (address 0C6 Each I/O pin (except R35) can independently used as an in- put or an output through the R3IO register (address 0C7 ADDRESS: 0C6 R3 Data Register R35 is an input only port.

  • Page 41: Clock Generator

    Preliminary MC80F0104/0204 10. CLOCK GENERATOR As shown in Figure 10-1 , the clock generator produces the ry is through a divide-by-two flip-flop, but minimum and basic clock pulses which provide the system clock to be maximum high and low times specified on the data sheet supplied to the CPU and the peripheral hardware.
  • Page 42 In addition to external crystal/resonator and external RC/R oscillation, the MC80F0104/0204 provides the internal In addition, the MC80F0104/0204 has an ability for the ex- 4MHz or 2MHz oscillation. The internal 4MHz/2MHz os- ternal RC oscillated operation. It offers additional cost sav- cillation needs no external parts.

  • Page 43: Basic Interval Timer

    Preliminary MC80F0104/0204 11. BASIC INTERVAL TIMER The MC80F0104/0204 has one 8-bit Basic Interval Timer If the STOP instruction executed after writing "1" to bit that is free-run and can not stop. Block diagram is shown RCWDT of CKCTLR, it goes into the internal RC oscillat- in Figure 11-1 .
  • Page 44 MC80F0104/0204 Preliminary CKCTLR Interrupt (overflow) Period (ms) Source clock [2:0] = 8MHz ÷8 0.256 ÷16 0.512 ÷32 1.024 ÷64 2.048 ÷128 4.096 ÷256 8.192 16.384 ÷512 32.768 ÷1024 Table 11-1 Basic Interval Timer Interrupt Period ADDRESS: 0F2 CKCTLR BTCL ADRST...

  • Page 45: Watchdog Timer

    Preliminary MC80F0104/0204 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction The RC oscillated watchdog timer is activated by setting such as endless looping caused by noise or the like, and re- the bit RCWDT as shown below.
  • Page 46 MC80F0104/0204 Preliminary Watchdog Timer Control er output will become active at the rising overflow from the binary counters unless the binary counter is cleared. At Figure 12-2 shows the watchdog timer control register. this time, when WDTON=1, a reset is generated, which The watchdog timer is automatically disabled after reset.
  • Page 47 Preliminary MC80F0104/0204 Source clock BIT overflow Binary-counter Counter Counter Clear Clear WDTR Match Detect WDTIF interrupt WDTR ← “1000_0011 ” WDT reset reset Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is gen- The main clock oscillator also turns on when a watchdog erated, which drives the RESET pin low to reset the inter- timer reset is generated in sub clock mode.

  • Page 48: Timer/Event Counter

    MC80F0104/0204 Preliminary 13. TIMER/EVENT COUNTER TheMC80F0104/0204 has Four Timer/Counter registers. in response external or internal clock sources same with Each module can generate an interrupt to indicate that an timer or counter function. When external clock edge input, event has occurred (i.e. timer match).
  • Page 49 Preliminary MC80F0104/0204 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag T0CK2 TM0.4 000: 8-bit Timer, Clock source is f ÷...
  • Page 50 MC80F0104/0204 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP2 TM2.5 0: Timer/Counter mode 1: Capture mode selection flag T2CK2 TM2.4 000: 8-bit Timer, Clock source is f ÷...

  • Page 51: 8-Bit Timer / Counter Mode

    Preliminary MC80F0104/0204 13.1 8-bit Timer / Counter Mode The MC80F0104/0204 has four 8-bit Timer/Counters, cleared to "0" (Figure 13-3 ). These timers have each 8-bit Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 count register and data register. The count register is in- are shown in Figure 13-3 and Timer 2, Timer 3 are shown creased by every internal or external clock input.
  • Page 52 MC80F0104/0204 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] EDGE DETECTOR EC1 PIN T2ST ÷...
  • Page 53 Preliminary MC80F0104/0204 Example 1: ter. The count register is increased by every internal or ex- ternal clock input. The internal clock has a prescaler divide Timer0 = 2ms 8-bit timer mode at 4MHz ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by con- Timer1 = 0.5ms 8-bit timer mode at 4MHz...
  • Page 54 MC80F0104/0204 Preliminary Example: Make 1ms interrupt using by Timer0 at 4MHz TM0,#0FH ; divide by 32 TDR0,#124 ; 8us x (124+1)= 1ms SET1 ; Enable Timer 0 Interrupt ; Enable Master Interrupt When TM0 = 0000 1111 (8-bit Timer mode, Prescaler divide ratio = 32)
  • Page 55 Preliminary MC80F0104/0204 TDR1 enable disable clear & start stop TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt T1ST T1ST = 1 Start & Stop T1ST = 0 T1CN T1CN = 1 Control count T1CN = 0 Figure 13-8 Count Operation of Timer / Event counter...

  • Page 56: 16-Bit Timer / Counter Mode

    MC80F0104/0204 Preliminary 13.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit The clock source of the Timer 2 is selected either internal timer/counter register T0, T1 are incremented from 0000 or external clock by bit T2CK[2:0]. In 16-bit mode, the bits until it matches TDR0, TDR1 and then resets to 0000 T3CK[1:0] and 16BIT of TM3 should be set to "1"...

  • Page 57: 8-Bit Compare Output (16-Bit)

    Preliminary MC80F0104/0204 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] EDGE DETECTOR EC1 PIN T2ST ÷...
  • Page 58 MC80F0104/0204 Preliminary The Timer/Counter register is increased in response inter- Timer/Counter still does the above, but with the added fea- nal or external input. This counting function is same with ture that a edge transition at external input INTx pin causes...
  • Page 59 Preliminary MC80F0104/0204 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D2 16BIT CAP1 T1CK1 BTCL T1CK0 T1CN T1ST PWM1E INITIAL VALUE: 00 X means don’t care T0CK[2:0] Edge Detector EC0 PIN T0ST ÷...
  • Page 60 MC80F0104/0204 Preliminary ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] Edge Detector EC1 PIN T2ST ÷...
  • Page 61 Preliminary MC80F0104/0204 This value is loaded to CDR0 TIME Ext. INT0 Pin Interrupt Request ( INT0IF ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0IF ) 20nS Delay Clear & Start Capture ( Timer Stop ) Figure 13-13 Input Capture Operation of Timer 0 Capture mode Ext.

  • Page 62: 16-Bit Capture Mode

    MC80F0104/0204 Preliminary 13.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except The clock source of the Timer 2 is selected either internal that the Timer register is being run will 16 bits. The clock or external clock by bit T2CK[2:0]. In 16-bit mode, the bits...
  • Page 63 Preliminary MC80F0104/0204 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] Edge Detector EC1 PIN T2ST ÷...

  • Page 64: Pwm Mode

    MC80F0104/0204 Preliminary 13.6 PWM Mode TheMC80F0104/0204 has high speed PWM (Pulse Width reduced resolution. Modulation) functions which shared with Timer1 or Timer3. Frequency In PWM mode, R10 / PWM1O or R11 / PWM3O pin out- Resolution T1CK[1:0] T1CK[1:0] T1CK[1:0] put up to a 10-bit resolution PWM output. These pins...
  • Page 65 Preliminary MC80F0104/0204 ADDRESS: 0D2 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM1E INITIAL VALUE: 00 X:The value "0" or "1" corresponding your operation. ADDRESS: 0D5 T1PWHR BTCL T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 INITIAL VALUE: ---- 0000 Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
  • Page 66 MC80F0104/0204 Preliminary ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X:The value "0" or "1" corresponding your operation. ADDRESS: 0DB T3PWHR BTCL T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 INITIAL VALUE: ---- 0000 Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
  • Page 67 Preliminary MC80F0104/0204 Source clock PWM1E T1ST T1CN PWM1O [POL=1] PWM1O [POL=0] Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ] T1CK[1:0] = 00 ( XIN ) T1PPR (8-bit) Period T1PWHR3 T1PWHR2...

  • Page 68: Analog To Digital Converter

    10-bit digital The processing of conversion is start when the start bit value. The A/D module has ten (eight for MC80F0104) an- ADST is set to “1”. After one cycle, it is cleared by hard- alog inputs, which are multiplexed into one sample and ware.
  • Page 69 Preliminary MC80F0104/0204 (3) I/O operation the pin undergoing A/D conversion. The analog input pins AN0 ~ AN7,AN14 and AN15 also (4) AV pin input impedance have function as input/output port pins. When A/D conver- A series resistor string of approximately 5KΩ is connected...
  • Page 70 MC80F0104/0204 Preliminary ADDRESS: 0EF ADCM BTCL ADEN ADCK ADS3 ADS2 ADS1 ADS0 ADST ADSF INITIAL VALUE: 0000 0001 A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion.

  • Page 71: Serial Input/Output (Sio)

    Preliminary MC80F0104/0204 15. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit circuit as illustrated in Figure 15-1 . The SO pin is designed data serially. The Serial Input/Output (SIO) module is a se- to input and output. So the Serial I/O(SIO) can be operated rial interface useful for communicating with other periph- with minimum two pin.

  • Page 72: Transmission/Receiving Timing

    MC80F0104/0204 Preliminary Serial I/O Mode Register (SIOM) controls serial I/O func- Serial I/O Data Register (SIOR) is an 8-bit shift register. tion. According to SCK1 and SCK0, the internal clock or First LSB is send or is received. external clock can be selected.
  • Page 73 Preliminary MC80F0104/0204 SIOST SCK [R42] (POL=0) SO [P44] SI [R43] (IOSW=0) IOSWIN [P44] (IOSW=1) SIOSF (SIO Status) SIOIF (SIO Int. Req) Figure 15-3 Serial I/O Timing Diagram at POL=0 SIOST SCK [R42] (POL=1) SO [R44] SI [R43] (IOSW=0) IOSWIN [R44]...

  • Page 74: The Usage Of Serial I/O

    MC80F0104/0204 Preliminary 15.2 The usage of Serial I/O 1. Select transmission/receiving mode. SIOR,#0AAh ;set tx data 2. In case of sending mode, write data to be send to SIOR. SIOM,#0011_1100b ;set SIO mode 3. Set SIOST to “1” to start serial transmission.

  • Page 75: Universal Asynchronous Receiver/Transmitter (Uart)

    Preliminary MC80F0104/0204 16. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 16.1 UART Serial Interface Functions The Universal Asynchronous Receiver / Transmitter The UART driver consists of RXR, TXR, ASIMR, ASISR (UART) enables full-duplex operation wherein one byte of and BRGCR register. Universal asynchronous serial I/O data after the start bit is transmitted and received.

  • Page 76: Serial Interface Configuration

    MC80F0104/0204 Preliminary RECEIVE ACLK PIN 5-bit counter ÷2 ~ f ÷128 match ÷2 Tx_Clock (Divider) Decoder match ÷2 Rx_Clock (Divider) TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 (BRGCR) 5-bit counter Internal Data Bus SEND Figure 16-2 Baud Rate Generator Block Diagram 16.2 Serial Interface Configuration...
  • Page 77 Preliminary MC80F0104/0204 ADDRESS: 0E6 ASIMR BTCL ISRM INITIAL VALUE: 0000 -00- UART Receive interrupt request is issued when an error occurs bit 0: Receive Completion Interrupt Control When Error occurs 1: Receive completion interrupt request is not issued when an error occur...
  • Page 78 MC80F0104/0204 Preliminary Asynchronous serial interface status register (ASISR) When a receive error occurs during UART mode, this reg- sets ASISR to ----_-000B. Figure 16-4 shows the format ister indicates the type of error. ASISR can be read by an 8 of ASISR..
  • Page 79 Preliminary MC80F0104/0204 Baud rate generator control register (BRGCR) This register sets the serial clock for serial interface. Figure 16-5 shows the format of BRGCR. BRGCR is set by an 8 bit memory manipulation instruc- tion. The RESET input sets BRGCR to -001_0000B.

  • Page 80: Communication Operation

    MC80F0104/0204 Preliminary 16.3 Communication operation The transmit operation is enabled when bit 7 (TXE) of the Once reception of one data frame is completed, a receive asynchronous serial interface mode register (ASIMR) is completion interrupt request (INT_RX) occurs. Even if an set to 1.

  • Page 81: Relationship Between Main Clock And Baud Rate

    Preliminary MC80F0104/0204 16.4 Relationship between main clock and baud rate The transmit/receive clock that is used to generate the baud ing main system clock which is divided. The baud rate rate is obtained by dividing the main system clock. Trans-...

  • Page 82: Buzzer Function

    MC80F0104/0204 Preliminary 17. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, The bit 0 to 5 of BUZR determines output frequency for buzzer register BUZR, and clock source selector. It gener- buzzer driving. ates square-wave which has very wide range frequency Equation of frequency calculation is shown below.
  • Page 83 Preliminary MC80F0104/0204 The 6-bit counter is cleared and starts the counting by writ- When main-frequency is 4MHz, buzzer frequency is ing signal at BUZR register. It is incremental from 00 shown as below Table 17-1. til it matches 6-bit BUR value.

  • Page 84: Interrupts

    MC80F0104/0204 Preliminary 18. INTERRUPTS TheMC80F0104/0204 interrupt circuits consist of Inter- tored to only if the interrupt was transition-activated. rupt enable register (IENH, IENL), Interrupt request flags The Timer 0 ~ Timer 3 Interrupts are generated by T0IF, of IRQH, IRQL, Priority circuit, and Master enable flag T1IF, T2IF and T3IF which is set by a match in their re- (“I”...
  • Page 85 Preliminary MC80F0104/0204 The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register. Reset/Interrupt Symbol Priority The UART receive or transmit interrupts are generated by UARTRIF or UARTTIF are set by completion of UART...

  • Page 86: Interrupt Sequence

    MC80F0104/0204 Preliminary ADDRESS: 0EC IRQH T0IF INT0IF INT1IF INT2IF INT3IF SIOIF UARTRIF UARTTIF INITIAL VALUE: 0000 0000 Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag UART Txx interrupt request flag UART Rx interrupt request flag External interrupt 3 request flag...
  • Page 87 Preliminary MC80F0104/0204 System clock Instruction Fetch SP-2 V.L. V.H. New PC SP-1 Address Bus Not used Data Bus V.L. OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.

  • Page 88: Brk Interrupt

    MC80F0104/0204 Preliminary main task acceptance of interrupt interrupt service task saving registers restoring registers interrupt return 18.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section).
  • Page 89 Preliminary MC80F0104/0204 be serviced even if certain interrupt is in progress. Main Program service TIMER 1 service INT0 service enable INT0 disable other In this example, the INT0 interrupt can be serviced without any Occur Occur pending, even TIMER1 is in progress.

  • Page 90: External Interrupt

    MC80F0104/0204 Preliminary 18.4 External Interrupt The external interrupt on INT0, INT1, INT2 and INT3 pins The edge detection of external interrupt has three transition are edge triggered depending on the edge selection register activated mode: rising edge, falling edge, and both edge.
  • Page 91 Preliminary MC80F0104/0204 ADDRESS: 0EE IEDS IED3H IED3L IED2H IED2L IED1H BTCL IED1L IED0H IED0L INITIAL VALUE: 00 INT3 INT2 INT1 INT0 Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) ADDRESS: 0F8...

  • Page 92: Power Saving Operation

    MC80F0104/0204 Preliminary 19. POWER SAVING OPERATION TheMC80F0104/0204 has two power-down modes. In shows the status of each Power Saving Mode. SLEEP power-down mode, power consumption is reduced mode is entered by the SSCR register to “0Fh”., and STOP considerably. For applications where power consumption...

  • Page 93: Stop Mode

    Preliminary MC80F0104/0204 Oscillator pin) Internal Clock External Interrupt SLEEP Instruction Executed Normal Operation SLEEP Operation Normal Operation Figure 19-2 SLEEP Mode Release Timing by External Interrupt Oscillator pin) Clock RESET Internal RESET SLEEP Instruction Stabilization Time Execution = 65.5mS @4MHz...
  • Page 94 MC80F0104/0204 Preliminary The reset should not be activated before V is restored to pin interface (depending on the external circuitry and pro- its normal operating level, and must be held active long gram) is not directly determined by the hardware operation enough to allow the oscillator to restart and stabilize.
  • Page 95 Preliminary MC80F0104/0204 By reset, exit from Stop mode is shown in Figure 19-6 . STOP INSTRUCTION STOP Mode Interrupt Request Corresponding Interrupt IENH or IENL ? Enable Bit (IENH, IENL) STOP Mode Release Master Interrupt I-FLAG Enable Bit PSW[2] Interrupt Service Routine...

  • Page 96: Stop Mode At Internal Rc-Oscillated Watchdog Timer Mode

    MC80F0104/0204 Preliminary STOP Mode Oscillator (XI pin) Internal Clock RESET Internal RESET STOP Instruction Execution Stabilization Time Time can not be control by software = 65.5mS @4MHz Figure 19-6 Timing of STOP Mode Release by Reset 19.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode...
  • Page 97 Preliminary MC80F0104/0204 Oscillator pin) Internal RC Clock Internal Clock External Interrupt ( or WDT Interrupt ) Clear Basic Interval Timer STOP Instruction Execution Counter Normal Operation Stabilization Time STOP mode Normal Operation at RC-WDT Mode > 20mS Figure 19-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt...

  • Page 98: Minimizing Current Consumption

    MC80F0104/0204 Preliminary 19.4 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. should turn-off output drivers that are sourcing or sinking To minimize current drawn during Stop mode, the user current, if it is practical. INPUT PIN...
  • Page 99 Preliminary MC80F0104/0204 viewing from external MCU is very high that the current output mode considering there is no current flow. The port doesn’t flow. setting to High or Low is decided by considering its rela- tionship with external circuit. For example, if there is ex-...

  • Page 100: Reset

    MC80F0104/0204 Preliminary 20. RESET The MC80F0104/0204 supports various kinds of reset as • Watchdog Timer Timeout Reset below. • Power-Fail Detection (PFD) Reset • Power-On Reset (POR) • Address Fail Reset • RESET (external reset circuitry) RESET Noise Canceller (Power-On Reset)
  • Page 101 Preliminary MC80F0104/0204 10kΩ 7036P to the RESET pin 10uF Figure 20-1 Simple Power-on-Reset Circuit Oscillator pin) RESET ADDRESS FFFE FFFF Start DATA MAIN PROGRAM Reset Process Step Stabilization Time =65.5mS at 4MHz x 256 ÷1024 Figure 20-2 Timing Diagram after Reset...

  • Page 102: Power Fail Processor

    MC80F0104/0204 Preliminary 21. POWER FAIL PROCESSOR TheMC80F0104/0204 has an on-chip power fail detection on page 98. circuitry to immunize against power noise. A configura- In the in-circuit emulator, power fail function is not imple- tion register, PFDR, can enable or disable the power fail mented and user can not experiment with it.
  • Page 103 Preliminary MC80F0104/0204 65.5mS Internal RESET When PFDM = 1 65.5mS Internal t < 65.5mS RESET 65.5mS Internal RESET Figure 21-3 Power Fail Processor Situations (at 4MHz operation) Mar. 2005 Ver 0.2...

  • Page 104: Countermeasure Of Noise

    MC80F0104/0204 Preliminary 22. COUNTERMEASURE OF NOISE 22.1 Oscillation Noise Protector The Oscillation Noise Protector (ONP) is used to supply by high frequency noise. stable internal system clock by excluding the noise which - Change system clock to the internal oscillation clock could be entered into oscillator and recovery the oscillation when the high frequency noise is continuing.

  • Page 105: Oscillation Fail Processor

    Preliminary MC80F0104/0204 22.2 Oscillation Fail Processor The oscillation fail processor (OFP) can change the clock vice Configuration Area (MASK option for MC80C0104/ source from external to internal oscillator when the oscil- 0204) enables the function to operate the device by using lation fail occured.

  • Page 106: Device Configuration Area

    MC80F0104/0204 Preliminary Device Configuration Area The Device Configuration Area can be programmed or left accessible during normal execution but is readable and unprogrammed to select device configuration such as writable during FLASH program / verify mode. POR, ONP, CLK option and security bit. This area is not...

  • Page 107: Mask Option (Mc80C0104/0204)

    Preliminary MC80F0104/0204 24. MASK Option (MC80C0104/0204) The MC80C0104/0204 has several MASK option which package type, Oscillation selection, oscillation noise pro- configures the package type or use of some special features tector, oscillation fail protector, internal 4MHz, amount of of the device. The Mask option of the MASK order sheet noise to be cancelled.

  • Page 108: Emulator Eva. Board Setting

    MC80F0104/0204 Preliminary 25. Emulator EVA. Board Setting ➊ ➎ ➏ ➐ ➌ ➍ ➋ Mar. 2005 Ver 0.2...
  • Page 109 This connector is only used for a device under 32 PIN. For the MC80F0208/0216/0224. Must be OFF position. ON : For the MC80F0208/0216/0224. OFF : For the MC80F0104/0204. Eva. select switch These switches select the AV source. ON & OFF : Use Eva. V OFF &...
  • Page 110 MC80F0104/0204 Preliminary DIP S/W, VR Description ON/OFF Setting (switch 1 & 2) ➏ These switches select the R33 or X This switch select the Normal I/O port (off) (switch 3 & 4) or special function select (on). These switches select the R34 or X ON &...

  • Page 111: In-System Programming (Isp)

    D must be configured to enter the ISP mode. 1. Connect the serial(RS-232C) cable between a target 4. Run the MagnaChip ISP software. board and the COM port of your PC. 5. Press the Reset Button in the ISP S/W. If the status win- 2.
  • Page 112 MC80F0104/0204 Preliminary Function Description Load HEX File Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format.

  • Page 113: Hardware Conditions To Enter The Isp Mode

    Preliminary MC80F0104/0204 26.3 Hardware Conditions to Enter the ISP Mode The In-System Programming (ISP) is performed without bedded application possible with a minimum of additional removing the microcontroller from the system. The In- expense in components and circuit board area. The boot...

  • Page 114: Reference Isp Circuit Diagram And Magnachip Supplied Isp Board

    MC80F0104/0204 Preliminary 26.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board The ISP software and hardware circuit diagram are provided at partment. The following circuit diagram is for reference use.. www.magnachipmcu.com . To get a ISP B/D, contact to sales de- 2Ν2907...
  • Page 115 APPENDIX...

  • Page 117: Instruction Map

    MC80F0104/0204 Preliminary A. INSTRUCTION MAP 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC #imm dp+X !abs .bit...

  • Page 118: Instruction Set

    MC80F0104/0204 Preliminary B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC ADC #imm Add with carry. A ← ( A ) + ( M ) + C ADC dp ADC dp + X NV--H-ZC ADC !abs...
  • Page 119 MC80F0104/0204 Preliminary BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC EOR #imm Exclusive OR EOR dp A ← ( A ) ⊕ ( M ) EOR dp + X EOR !abs N-----Z- EOR !abs + Y EOR [ dp + X ]...

  • Page 120: Register / Memory Operation

    MC80F0104/0204 Preliminary 2. REGISTER / MEMORY OPERATION FLAG BYTE CYCLE MNEMONIC OPERATION NVGBHIZC CODE LDA #imm Load accumulator LDA dp A ← ( M ) LDA dp + X LDA !abs LDA !abs + Y N-----Z- LDA [ dp + X ]...

  • Page 121: Bit Operation

    MC80F0104/0204 Preliminary 3. 16-BIT OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION NVGBHIZC CODE 16-Bits add without carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents :...

  • Page 122: Branch / Jump Operation

    MC80F0104/0204 Preliminary 5. BRANCH / JUMP OPERATION BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel...

  • Page 123: Control Operation & Etc

    MC80F0104/0204 Preliminary 6. CONTROL OPERATION & etc. FLAG BYTE CYCLE MNEMONIC OPERATION NVGBHIZC CODE Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...
  • Page 124 MC80F0104/0204 Preliminary viii Mar. 2005 Ver 0.2...

  • Page 125: Mask Order Sheet

    “00H” EFFFH F000H .OTP file data FFFFH (Please check mark into 4. Delivery Schedule Quantity MagnaChip Confirmation Date YYYY Customer Sample YYYY Risk Order 5. ROM Code Verification This box is written after “5.Verification”. YYYY...
  • Page 126 “00H” EFFFH F000H .OTP file data FFFFH (Please check mark into 4. Delivery Schedule Quantity MagnaChip Confirmation Date YYYY Customer Sample YYYY Risk Order 5. ROM Code Verification This box is written after “5.Verification”. YYYY...

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