Page 1 TA600137-EN0/0 RoHS2 2011/65/EU Pulse Control LSI PCL6045BL User’s Manual...
Page 2 TA600137-EN0/0 INDEX 1. Introduc�on ....................................1 How to use this manual ................................ 1 1.1.1 Symbol descrip�on ................................ 1 1.1.2 Terminology ................................... 3 1.1.3 Nota�on ..................................4 Handling the product ................................5 1.2.1 Storing ................................... 5 1.2.2 Unpacking ..................................5 1.2.3 Safety ..................................... 5 Product Warranty .................................
Page 3 TA600137-EN0/0 Status and General-purpose I/O port ..........................41 5.2.1 Main status (MSTS) ..............................41 5.2.2 Sub-status (SSTS) & General Purpose I/O port (IOP) ....................45 5.2.3 Extension status (RSTS) ..............................46 5.2.4 Interpola�on status (RIPS) ............................46 Commands ..................................47 5.3.1 Opera�on commands ..............................
Page 4 TA600137-EN0/0 6.4.2 Target posi�on override 2 (PCS) ..........................176 6.4.3 End-point-draw opera�on ............................178 Output pulse control ................................ 179 6.5.1 Output pulse mode ..............................179 6.5.2 Opera�on complete �ming ............................181 6.5.3 Output pulse width control ............................183 Idling control ..................................184 Mechanical external input control ...........................
Page 5 TA600137-EN0/0 6.17.3 Con�nuous interpola�on using circular interpola�on dummy opera�on ............... 256 Interrupt request (INT) ..............................257 6.18.1 Error interrupt ................................. 258 6.18.2 Event interrupt ................................ 259 6.18.3 Opera�on stop interrupt ............................260 General-purpose one shot .............................. 261 7. Electrical Characteris�cs ................................. 262 Absolute maximum ra�ngs ...............................
Page 6 TA600137-EN0/0 1. Introduc�on Thank you for choosing our pulse control LSI, the "PCL6045BL." This manual describes the speciﬁca�ons, func�ons, connec�ons, and usages of PCL6045BL. Be sure to read this manual thoroughly and keep it handy in order to use the product appropriately. How to use this manual Reproduc�on of this manual in whole or in part without permission is prohibited by the Copyright Act.
Page 7 TA600137-EN0/0 C a u t i o n "Cau�on" without warning symbol indicates that the operator is not likely to be injured, but it can cause damage or result in a malfunc�on to this product, your equipment, or your instruments. In addi�on to the hazardous level classiﬁca�ons described above, the following nota�ons are also used.
Page 8 TA600137-EN0/0 1.1.2 Terminology Terminology used in this manual is described below. Refer to our web pages for terms that are not described in this sec�on. • 1st pre-register (= Pre-register) Pre-register is a register to set the con�nuous opera�on data during opera�on. It exists for every func�on such as for posi�oning control, speed control, and the like.
Page 9 TA600137-EN0/0 • FH speed Higher frequency (star speed, target speed) Specify the max speed of a motor [pps]. • FA speed Frequency for adjustment (backlash, slip, sensor detec�on) Specify the max star�ng speed of a motor [pps]. 1.1.3 Nota�on For the suﬃxes of pin names, register names, and bit names, "x" indicates the X-axis, "y" indicates the Y-axis, "z" indicates the Z-axis, and "u"...
Page 10 TA600137-EN0/0 Handling the product 1.2.1 Storing Store the product in an environment where condensa�on does not occur at a temperature from −65 °C to +150°C. 1.2.2 Unpacking Check if the quan�ty of the product you ordered, and moisture-proof desiccants are included in the package when unpacked. 1.2.3 Safety This sec�on describes the basic safety precau�ons for safer opera�ons.
Page 11 TA600137-EN0/0 1.2.3.2 Precau�ons for transporta�on and storing LSIs C a u t i o n • Always handle LSIs and the packages including LSIs with care. Do not throw or drop them. It may damage the LSIs or tear the aluminum-laminated packaging material and impair the air�ghtness.
Page 12 TA600137-EN0/0 1.2.3.3 Precau�ons for handling environment C a u t i o n • Humidity should be 30 to 70 % as a guide. Take into considera�on the moisture absorp�on a�er opening the moisture-proof packaging product. • Make sure to ground all equipment, tools, and jigs that are present at the work site. Place a conduc�ve mat on the ﬂoor in the work area to prevent sta�c electricity on the •...
Page 13 TA600137-EN0/0 1.2.3.4 Precau�ons for installa�on C a u t i o n • Plas�c packages are easy to absorb moisture, and even if le� indoors, the moisture absorp�on will progress over �me. If the LSI is put into a solder reﬂow oven while absorbing moisture, the resin may crack or the adhesion between the resin and the frame may deteriorate.
Page 14 The warranty period is one year from the date of delivery to an assigned place. 1.3.2 Warranty scope If any defect is found in a product during the warranty period under the normal use following this document, NPM will repair or replace the product without charge.
Page 15 TA600137-EN0/0 2. Outline Features PCL6045BL is a 4-axis pulse control LSI for stepping motors and servo motors. In the CMOS conﬁgura�on, the connec�on with a CPU can be selected from four types of parallel bus interfaces. In communica�on with a CPU, you can perform command inputs, data inputs/outputs, and interrupt request signal outputs, etc.
Page 16 TA600137-EN0/0 start when the external signal is input. - Triangle drive avoidance (FH correc�on func�on) In the posi�oning mode, this func�on automa�cally lowers the target speed (FH) to avoid a triangle driving when the feeding amount is too small. - Pre-register The 1st and 2nd data for con�nuous opera�on (feed amount, ini�al speed, moving speed, accelera�on rate, decelera�on rate, speed magniﬁca�on rate, slow-down point, opera�on mode, center posi�on of circular interpola�on, S-curve sec�on in accelera�on, S-curve sec�on in decelera�on, number of circular interpola�on steps) can be writen during opera�on.
Page 17 TA600137-EN0/0 - Simultaneous stop You can stop any mul�ple axes simultaneously by wri�ng a command, inpu�ng a CSTP signal, or caused by abnormal stops of any axis. Any axis or any mul�ple axes can be selected from mul�ple PCL6045BLs. If the CSTP signal is already ON at the start, the opera�on does not start. - Vibra�on suppression Set the frequency of vibra�on suppression so that one pulse each in reverse and forward direc�on are added just before stopping.
Page 18 TA600137-EN0/0 When this signal is already ON at start, no further movement made in + direc�on. (can move in − direc�on). (2) −EL: Func�ons the same as +EL signal when moving in − direc�on. (3) SD: Decelerates or decelerate-stops by so�ware se�ngs In the decelera�on se�ng, the axis will decelerate to FL speed if this signal is turned ON during high-speed opera�on.
Page 19 TA600137-EN0/0 - Output pulse speciﬁca�ons Output pulses can be selected among common-pulse mode (OUT/DIR), 2-pulse mode (PLS/MNS) or 90-degree phase diﬀerence mode (PHA/PHB). The output logic can also be selected. In 90-degree phase diﬀerence mode, frequency of output signals reduces to 1/4 of opera�on speed. Therefore, if the mode is selected, frequency characteris�cs of interface circuit can be lowered.
Page 20 TA600137-EN0/0 Conﬁgura�on Controlling PCL6045BL requires a crystal oscillator outpu�ng recommended frequency of 19.6608 MHz and a CPU or FPGA, etc. with a Parallel-bus interface with the 16-bit or 8-bit data bus. CS, RD, WR, RST INT, IFB, WRQ CEMG CSTA, CSTP IF0, IF1 Clock Circular interpolation circuit...
Page 21 TA600137-EN0/0 3. Speciﬁca�ons The following table shows the speciﬁca�ons of PCL6045BL such as the func�ons. Item Descrip�on Number of axes [axis] Posi�oning control range [pulses] −134,217,728 to +134,217,727 (28 bits) Number of registers used for se�ng speeds 3 (FL, FH, and FA) [type/axis] Speed se�ng step number [steps] 1 to 65,535 (16 bits)
Page 22 TA600137-EN0/0 4. Hardware descrip�on The following explains the connec�on between PCL6045BL and a CPU by showing the external dimensions and pin list. External dimensions A1 pin is located at the lower le� of PCL6045BL model name marking. (Equivalent to P-LQFP176-2424-0.50) PCL6045BL XXXXXXXXX JAPAN...
Page 23 TA600137-EN0/0 Dimension in Millimeters Symbol Minimum Nominal Maximum 23.90 24.00 24.10 23.90 24.00 24.10 25.60 26.00 26.40 25.60 26.00 26.40 0.50 0.17 0.22 0.27 0.08 1.70 0.00 0.10 0.20 1.30 1.40 1.50 0.08 0.30 0.50 0.75 0.80 1.00 1.20 0.09 0.15 0.20 θ...
Page 24 TA600137-EN0/0 Pin assignment diagram Pin 1 is located at the lower le� of PCL6045BL model name marking. ORGu ALMu LTCy CLRy INPy PCSy -DRy +DRy BSYy +DRu ERCy -DRu DIRy PCSu OUTy OUTu DIRu ERCu BSYu INPu CLRu ALMy LTCu ORGy PCL6045BL -ELy...
Page 25 TA600137-EN0/0 Pin deﬁni�ons [I/O] column shows the direc�on of signals I: Input, O: Output, B: Bidirec�onal [Logic] column shows the logic of signals. P: Posi�ve logic, N: Nega�ve logic, #: Can be changed by so�ware, %: Can be changed by hardware. [Resistance] column shows whether a pull-up resistor is built-in or not.
Page 26 TA600137-EN0/0 Signal Pin No. Logic Resistance Unused Descrip�on name Input pin for chip selec�on signal (CS) Enable RD and WR pins by CS = L level. Input pin for read signal (RD) Enable RD pin by CS = L level. Input pin for the write signal (WR) Enable WR pin by CS = L level.
Page 27 TA600137-EN0/0 Signal Pin No. Logic Resistance Unused Descrip�on name +ELx, +Direc�on End limit signal (+EL) input pins 34， +ELy, 66， See "6.7.1 End limit (+EL, −EL)". +ELz, 97， +ELu −ELx, 35， −Direc�on End limit signal (−EL) input pins −ELy, 67， See "6.7.1 End limit (+EL, −EL)"...
Page 28 TA600137-EN0/0 Signal Pin No. Logic Resistance Unused Descrip�on name EZx, Encoder Z phase signal (EZ) input pins 42， EZy, 73， See "6.7.3 Origin (ORG), Encoder Z phase (EZ)" EZz, 106， for details. PAx, 43， Manual pulser A-phase signal (PA) input pins PAy, 74，...
Page 29 TA600137-EN0/0 Signal Pin No. Logic Resistance Unused Descrip�on name LTCx, Counter latch signal (LTC) input pins 51， LTCy, 87， See "6.12.3 Counter latch". LTCz, 115， LTCu ERCx, 59， Devia�on counter clear (ERC)signal (ERC) ERCy, 80， output pins. Open ERCz, 124， Connect to a servo motor driver.
Page 30 TA600137-EN0/0 Signal Pin No. Logic Resistance Unused Descrip�on name P5x, I/O pin for general-purpose I/O port 5 (P5). 63， P5y, 94， This pin is also used for outpu�ng comparator P5z, 126， 3 condi�on-met signal (CP3). See “5.4.3.3 RENV2: Environment se�ng 2”. I/O pins for general-purpose I/O port 6 (P6).
Page 31 TA600137-EN0/0 CPU interface The connec�on to a CPU can be selected from four types: 68000, H8, 8086, and Z80 types. Select the connec�on with IF1 and IF0 pins as follow. The following table shows the correspondence between PCL6045BL pins and CPU pins. PCL6045BL pin name Type (bit width, CUP Interface #) 68000 (16, 0)
Page 32 TA600137-EN0/0 4.4.2 H8 interface Interface of 16-bit width of RD signal, HWR signal, and WAIT signal. 8 bits cannot be accessed. The lower-address corresponds to the upper-word of I/O buﬀer. Interface for H8 system CPU. H8 CPU PCL6045BL 水晶発振器 Crystal oscillator Decode デコード...
Page 33 TA600137-EN0/0 4.4.3 8086 interface Interface of 16-bit width of RD signal, WR signal, and READY signal. 8-bit cannot be accessed. The lower address corresponds to the lower word of I/O buﬀer. Interface for 8086-series CPU. 8086 CPU PCL6045BL M/IO Decode Crystal oscillator 水晶発振器...
Page 34 TA600137-EN0/0 4.4.4 Z80 interface Interface of 8-bit range of RD signal, WR signal, and WAIT signal. 16-bit cannot be accessed. The low-order address corresponds to the low-order byte of I/O buﬀer. Interface for Z80 system CPU. Z80 CPU PCL6045BL Crystal oscillator IORQ Decode 水晶発振器...
Page 35 TA600137-EN0/0 5. So�ware descrip�on This chapter describes the communica�on from a CPU and shows the commands and registers for PCL6045BL. CPU communica�on The communica�on method from a CPU to PCL6045BL is via parallel communica�on. 5.1.1 Access method Command wri�ng and status reading directly access the target address. Register reads and writes are accessed through I/O buﬀer by means of register control commands.
Page 36 TA600137-EN0/0 5.1.2.3 8086 Communica�on address map Axis A4, A3 A2, A1 Bits Address name Descrip�on MSTSW Main status COMW Axis Selec�on, Commands SSTSW Sub-status, General-purpose I/O port OTPW General-purpose output port BUFW0 I/O buﬀer Lower-data BUFW1 I/O buﬀer Upper-data (Same as X axis) (Same as X axis) (Same as X axis) 5.1.2.4 Z80 communica�on address map...
Page 37 TA600137-EN0/0 5.1.3 Command Write Axis selec�on (SELn) and commanding (COM) are writen to COMW (COMB1, COMB0) address. COMW COMB1 COMB0 SELu SELz SELy SELx COMW.COMB1: This is the wri�ng area for axis selec�on. Writes a command to the axis among SELx to SELu where 1 has been writen. If more than one bit is set to 1, the same command can be writen to more than one selected axis.
Page 38 TA600137-EN0/0 If the following access is performed without using WRQ signal, the waveform will be as shown by the doted line in the ﬁgure below, and wri�ng may fail. A4 ~ A1 COMW COMW D15 ~ D0 SELn, COM SELn, COM 自動的にCPUが...
Page 39 TA600137-EN0/0 R e m a r k s From now on, the programming language used in software sample is based on C#. The specifications of the program used are as follows. var: Identifier of Variant type. Address : In H8 system, 4-bit from A4 pin to A1 pin. WriteIn16bit(Address,Dt16bit): Prepare a method to write 16 bit to Address.
Page 40 TA600137-EN0/0 5.1.4 Register Write Register Write data (BUF) writes to BUFW1 and BUFW0 addresses. BUFW1 BUFW0 BUFB3 BUFB2 BUFB1 BUFB0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUFW1 (BUFB3, BUFB2): Writes the upper data.
Page 41 TA600137-EN0/0 Sample so�ware (H8 system): // The process to write data to PRMV register of X axis and Y axis simultaneously Var Address = 0x0; // Addresses: I/O buﬀer of X axis Var BufData = 0x01234567; // I/O buﬀer is 0123 4567h (19,088,743) WriteIn32bit (Address, BufData);...
Page 42 TA600137-EN0/0 5.1.5 Register Read Register read data (BUF) is made from BUFW1 address and BUFW0 address. BUFW1 BUFW0 BUFB3 BUFB2 BUFB1 BUFB0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUFW1 (BUFB3, BUFB2): Read the upper- data.
Page 43 TA600137-EN0/0 Sample so�ware (H8 system): // Reading register data from PRMV register of X axis and Y axis at the same �me var Address = 0x3: // Addresses: COMW of X axis var Command = 0x03C0; // Axis selec�on: Y axis and X axis (03h) // Command: RPRMV (C0h) WriteIn16bit (Address, Command);...
Page 44 TA600137-EN0/0 5.1.6 Main status read Main status (MSTS) is read from MSTSW address. MSTSW MSTSB1 MSTSB0 MSTS MSTSW (MSTSB1, MSTSB0): Read the main status. In Z80 communica�on, the main status is read from MSTSB1, MSTSB0 addresses. In other communica�ons, the main status is read from MSTSW address. The main status is updated by inpu�ng more than one cycle of CLK while RD (LS) = H level or CS = H level.
Page 45 TA600137-EN0/0 5.1.7 General-purpose output port write The status of the general-purpose output port (OTP) is writen to OTPW address. OTPW OTPB OTP7 OTP6 OTP5 OTP4 OTP3 OTP2 OTP1 OTP0 OTPW (OTPB): Writes the status of the general-purpose output port. OTP7 to OTP0 corresponds to P7n to P0n pin. If wri�ng 1 to the general-purpose output port, H-level is output from the general-purpose I/O pin.
Page 46 TA600137-EN0/0 Status and General-purpose I/O port There are four statuses as follows: Main status (MSTS)  Sub-status (SSTS)  Extension status (RSTS)  Interpola�on status (RIPS)  The status of the General-purpose I/O port (IOP) is described with the Sub-status. 5.2.1 Main status (MSTS) The following items can be read: Opera�on statuses, with/without interrupts, the establishment status of comparators, and decision status of pre-registers.
Page 47 TA600137-EN0/0 Name Descrip�on An event interrupt has occurred. 0 : No event interrupt has occurred. SINT 1 : An event interrupt has occurred. You can output L-level from INT pin. When all the bits set to 1 in RIST register become 0, MSTS.SINT bit returns to 0. It shows the sequence number (RMD.MSN) during opera�on or when stopped.
Page 48 TA600137-EN0/0 Name Descrip�on Determined state of 2nd pre-register for con�nua�on compare data. SPDF 0 : 2nd pre-register for con�nuous compare data is in undetermined. 1 : 2nd pre-register for con�nuous compare data is in determined state. The following ﬁgure shows the status bit change �ming for common pulse mode. The dashed line of MSTS.SEND bit in the bit change �ming chart is the ini�al status immediately a�er rese�ng.
Page 49 TA600137-EN0/0 3. Con�nuous movement by switch control (RMD.MOD = 02h) MSTS.SRUN bit ON is delayed for BSY signal ON delay �me (T ) from DR signal ON at the longest. CMDBSY START STOP COMMAND COMMAND MSTS READ MSTS.SEND MSTS.SENI MSTS.SRUN MSTS.SSCM *2 OUT signal output is delayed for the start delay �me (T ) from DR signal ON at the longest.
Page 50 TA600137-EN0/0 5.2.2 Sub-status (SSTS) & General Purpose I/O port (IOP) You can read the signal status of input pins, the speed during opera�on, the signal status of general-purpose I/O pins. SSTSW SSTSB IOPB SSD SORG SMEL SPEL SALM SFC IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 Name Descrip�on IOP0...
Page 51 TA600137-EN0/0 Name Descrip�on Input status of ORG signal. The input state of this signal is through the input noise ﬁlter and with the input logic applied. 0 : OFF SORG 1 : ON The input logic can be changed with RENV1.ORGL bit. The latch status of SD signal.
Page 52 TA600137-EN0/0 Commands There are two types of commands: “Opera�on command” and “Control command”. 5.3.1 Opera�on commands This command starts and stops the opera�on mode. 5.3.1.1 Start commands This command starts an opera�on mode while stopped. When writen during opera�on, the pre-register of con�nuous opera�on data is determined, and become the start command for con�nuous opera�ons.
Page 53 TA600137-EN0/0 5.3.1.4 Speed change commands When writen during opera�on, the target speed and speed patern are changed. If writen while stopped, it will be ignored. Symbol Descrip�on Change to FL speed immediately. FCHGL Speed patern becomes FL constant speed patern and changes to FL speed immediately. Change to FH speed immediately.
Page 54 TA600137-EN0/0 5.3.2 Control commands These commands control general-purpose output bits, registers, and counters. 5.3.2.1 NOP command This command does not aﬀect opera�ons or controls. Symbol Descrip�on This command does not aﬀect the opera�on. Wri�ng command will be processed. 5.3.2.2 General-purpose output bit control commands These commands control the general-purpose output port (OTP) bit by bit.
Page 55 TA600137-EN0/0 5.3.2.3 Reset control command A�er a hardware reset, you can use the so�ware reset if you want to reset again. Symbol Descrip�on Reset PCL6045BL by so�ware. SRST A�er wri�ng this command, wait at least 12 cycles of CLK signal before restar�ng CPU access. For rese�ng.
Page 56 TA600137-EN0/0 5.3.2.7 PCS control command This command controls the input of PCS signal. Symbol Descrip�on Used with target posi�on override 2. STAON Starts posi�oning control, instead of inpu�ng PCS signal to PCSn pin. For PCS signals, see "6.4.2 Target posi�on override 2 (PCS)". 5.3.2.8 Counter latch control command This command controls the counter latching.
Page 57 TA600137-EN0/0 5.3.2.10 Register control commands This command reads and writes registers and pre-registers. Register 2nd pre-register Read command Write command Read command Write command Descrip�on Name Name COMB0 Symbol COMB0 Symbol COMB0 Symbol COMB0 Symbol Feed amount RRMV WRMV PRMV RPRMV WPRMV (target posi�on)
Page 58 TA600137-EN0/0 Counter 1 RLTC1 RRLTC1 (command posi�on) latch Counter 2 RLTC2 RRLTC2 (general-purpose 1) latch Counter 3 (devia�on) RLTC3 RRLTC3 latch Counter 4 RLTC4 RRLTC4 (general-purpose 2) latch 34 Extension status RSTS RRSTS 35 Error interrupt factor REST RREST WREST 36 Event interrupt factor RIST RRIST...
Page 59 TA600137-EN0/0 Registers There are eight major types and 42 registers. For the pre-register, see "6.2 Pre-register". Descrip�on Name Range Pre-register Type -134,217,728 to 1 Feed amount (target posi�on) PRMV Posi�on control +134,217,727 2 FL speed step number 1 to 65,535 PRFL Speed control 3 FH speed step number...
Page 60 TA600137-EN0/0 Descrip�on Name Range Pre-register Type 134,217,728 to 26 Comparison data for comparator 3 RCMP3 Comparator +134,217,727 134,217,728 to 27 Comparison data for comparator 4 RCMP4 Comparator +134,217,727 134,217,728 to 28 Comparison data for comparator 5 RCMP5 PRCP5 Comparator +134,217,727 29 Event interrupt request RIRQ (4 byte)
Page 61 TA600137-EN0/0 5.4.1 Speed control register These registers are for speed controls. 5.4.1.1 RFL(PRFL): FL speed step number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFL(PRFL) Control commands: RRFL(D1h), RPRFL(C1h), WRFL(91h), WPRFL(81h)
Page 62 TA600137-EN0/0 5.4.1.3 RUR(PRUR): Accelera�on rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUR(PRUR) Control commands: RRUR(D3h), RPURU(C3h), WRUR(93h), WPRUR(83h) Register to set the accelera�on rate.
Page 63 TA600137-EN0/0 5.4.1.4 RDR(PRDR): Decelera�on rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR(PRDR) Control commands: RRDR(D4h)，RPRDR(C4h)，WRDR(94h)，WPRDR(84h) Register to set the decelera�on rate.
Page 64 TA600137-EN0/0 5.4.1.5 RMG(PRMG): Speed magniﬁca�on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMG(PRMG) Control commands: RRMG(D5h)，RPRMG(C5h)，WRMG(95h)，WPRMG(85h) Register that sets the rela�onship between the speed step number and the actual speed.
Page 65 TA600137-EN0/0 5.4.1.6 RUS(PRUS): S-curve accelera�on sec�on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUS(PRUS) Control commands: RRUS(D9h)，RPRUS(C9h)，WRUS(99h)，WPRUS(89h) Register to set the S-curve sec�on in S-curve accelera�on.
Page 66 TA600137-EN0/0 5.4.1.7 RDS(PRDS): S-curve decelera�on sec�on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDS(PRDS) Control commands: RRDS(DAh)，RPRDS(CAh)，WRDS(9Ah)，WPRDS(8Ah) Register to set the S-curve sec�on in S-curve decelera�on.
Page 67 TA600137-EN0/0 5.4.1.8 RFA: FA speed step number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Control commands: RRFA(DBh)，WRFA(9Bh) Register to set FA speed (backlash correc�on speed and slip correc�on speed) by speed step number.
Page 68 TA600137-EN0/0 5.4.2 Posi�on control register This register is for posi�on control. 5.4.2.1 RMV(PRMV): Feed amount (target posi�on) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # # # # RMV(PRMV) Control commands: RRMV(D0h)，RPRMV(C0h)，WRMV(90h)，WPRMV(80h)
Page 69 TA600137-EN0/0 5.4.2.3 RCI(PRCI): Number of circular interpola�on steps 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCI(PRCI) Control commands: RRCI(FCh)，RPRCI(CCh)，WRCI(BCh)，WPRCI(8Ch) Register to set the number of circular interpola�on steps of the control axis.
Page 70 TA600137-EN0/0 ( �� − �� ) × ( �� + 1 ) 1. Linear decelera�on (RMD.MSMD = 0) �� [ �� ] = ( �� + 1 ) × 32,768 When FH correc�on func�on OFF (RMD.MADJ = 1) is set, the op�mum value for a triangular drive are as follows. (Do not change the value to be set in RFH register) ��...
Page 71 TA600137-EN0/0 5.4.2.7 RPLS: Remaining pulse number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 RPLS Control commands :RRPLS(F4h) Register to obtain the remaining number of pulses up to target posi�on.
Page 72 TA600137-EN0/0 5.4.3 Environment se�ng register This register is for environment se�ngs. 5.4.3.1 RMD(PRMD): Opera�on mode MIPF MPCS MSDP MCCE MINP MSDE MENI METM MSMD MPIE MADJ MSPO MSPE Control commands : RRMD(D0h)，RPRMD(C0h)，WRMD(90h)，WPRMD(80h) Register to set the opera�on mode. PRMD register is the pre-register of RMD register. Name Description Set the opera�on mode.
Page 73 TA600137-EN0/0 Name Description 100 0111 (47h): Timer opera�on mode in posi�oning control. 101 0001 (51h): Opera�on mode of incremental movement in pulser control. 101 0010 (52h): Opera�on mode in which the absolute posi�on is speciﬁed with counter 1 in pulser control. 101 0011 (53h): Opera�on mode in which the absolute posi�on is speciﬁed with counter 2 in pulser control.
Page 74 TA600137-EN0/0 Name Description Sets the input func�on of SDn pins. 0: General-purpose input pin. MSDE 1: Decelerate or decelerate-stop when SD signal turns ON. SD signal status is obtained from RSTS.SDIN. Sets the input func�on of INPn pin. 0: General-purpose input pin MINP 1: Opera�on mode is completed when INP signal is ON The input status of INP signal is obtained in RSTS.SINP bit.
Page 75 TA600137-EN0/0 Name Description Sets the 2-bit sequence number. The sequence number is obtained in MSTS.SSC bit 17,16 The sequence number does not aﬀect the opera�on It can be used to control opera�on blocks when crea�ng the control so�ware. For the control of opera�on blocks, see "6.2.1 Con�nuous opera�on ". Sets the start �ming a�er wri�ng to start command.
Page 76 TA600137-EN0/0 Name Description Sets the FH correc�on func�on. 0: Automa�c correc�on (automa�cally avoid a triangular drive). 1: Manual correc�on (Not automa�cally avoid a triangular drive). When combining the following se�ngs, make sure to set the automa�c correc�on (RMD.MADJ = 0). •...
Page 77 TA600137-EN0/0 5.4.3.2 RENV1: Environment se�ng 1 ERCL EROR EROE ALML ORGL SDL SDLT SDM ELM ALMM PDTC PCSM INTM DTMF DRF FLTR PCSL LTCL INPL CLRM CLRL STPM STAM Control commands : RENV1(DCh)，WRENV1(9Ch) A register to set the speciﬁca�ons of I/O pins. Name Descrip�on Sets the output pulse mode.
Page 78 TA600137-EN0/0 Name Descrip�on Sets the input processing of EL signal ON in the opera�ng direc�on. 0: Immediate stop 1: Decelerate-stop If decelerate-stop is set, decelera�on starts by EL signal ON in the opera�ng direc�on. Even if EL signal becomes OFF during this decelera�on, decelera�on will con�nue to be stopped. Be careful of collision because the motor passes through the EL posi�on before stopping.
Page 79 TA600137-EN0/0 Name Descrip�on Sets the output func�on of ERCn pin at the immediate stop due to an abnormal stop factor. ERC signal can be output at the �me of immediate stop by +EL, −EL, ALM, CEMG signal and CEMG command (05h).
Page 80 TA600137-EN0/0 Name Descrip�on Sets the input logic of LTC signal. 0: Nega�ve logic LTCL 1: Posi�ve logic Latches the counter count value when LTC signal changes from OFF to ON when RENV5.LTM = 00b is set. Sets the input logic of PCSn pin. PCSL 0: Nega�ve logic 1: Posi�ve logic...
Page 81 TA600137-EN0/0 Name Descrip�on Sets the output pulse width control func�on. 0: When the output speed of a command pulse is 2.4 kpps or less, the output pulse width is ﬁxed at 0.2 PDTC 1: The output pulse width ﬂuctuates at a duty ra�o of 50% regardless of the output speed of a command pulse.
Page 82 TA600137-EN0/0 5.4.3.3 RENV2: Environment se�ng 2 POFF EOFF SMAX PMSK IEND PDIR EDIR PINF EINF Control commands : RRENV2(DDh)，WRENV2(9Dh) Registers to set the speciﬁca�ons of general-purpose I/O pins: EA, EB signals as well as PA, PB signals. Name Descrip�on Sets the I/O func�on of P0n pin. 00b: General-purpose input pin 01b: General-purpose output pin 10b: Outputs FUP signal in accelera�on.
Page 83 TA600137-EN0/0 Name Descrip�on Sets the I/O func�on of P6n pin. 00b: General-purpose input pin 13,12 01b: General-purpose output pin 10b: Outputs CP4 signal in nega�ve logic while comparator 4 condi�on is met. 11b: Outputs CP4 signal in posi�ve logic while comparator 4 condi�on is met. Sets the I/O func�on of P7n pin.
Page 84 TA600137-EN0/0 Name Descrip�on Sets the input logic of EZ signal. 0: Nega�ve logic 1: Posi�ve logic Counts down of RSPD.EZC bit when EZ signal changes from OFF to ON. Sets the input speciﬁca�ons for PA and PB signals. 00b: 90-degree phase diﬀerence mode 1x 01b: 90-degree phase diﬀerence mode 2x 25,24 10b: 90-degree phase diﬀerence mode 4x...
Page 85 TA600137-EN0/0 5.4.3.4 RENV3: Environment se�ng 3 BSYC CU4H CU3H CU2H CU4B CU3B CU2B CU1B CU4R CU3R CU2R CU1R CU4C CU3C CU2C CU1C Control commands : RRENV3(DEh)，WRENV3(9Eh) Register to set the speciﬁca�ons of an origin return opera�on and the func�on of a counter. Name Descrip�on Select the origin return method:...
Page 86 TA600137-EN0/0 Name Descrip�on Sets the count target of counter 4. 00b: Command pulse signal 13,12 01b: EA and EB signals 10b: PA and PB signals �� 11b: signal Sets the count limit for counter 4. 0: No limit BSYC 1: Count only when BSY = L level When RENV3.CI4 = 11b, the opera�ng �me can be measured with counter 4.
Page 87 TA600137-EN0/0 Name Descrip�on Sets whether or not counter 2 counts the command pulses even during backlash compensa�on and slip compensa�on. Enabled when counter 2 is set to count command pulses (RENV3.CI2 = 01b). CU2B 0: Not count 1: Count Sets whether or not counter 3 counts the command pulses even during backlash correc�on and slip correc�on.
Page 88 TA600137-EN0/0 5.4.3.5 RENV4: Environment se�ng 4 C2RM C1RM IDXM Control commands : RRENV4(DFh)，WRENV4(9Fh) Register to set the func�ons of Comparator 1 to Comparator 4. Name Descrip�on Sets the comparison target of Comparator 1. 00b: RCUN1 01b: RCUN2 10b: RCUN3 11b: RCUN4 If RENV4.C1C = 10b, compare with the absolute value of RCUN3 register (0 to 32,767).
Page 89 TA600137-EN0/0 Name Descrip�on Sets the comparison condi�ons for Comparator 2. 001b: RCMP2 = Comparison target (regardless of coun�ng direc�on). 010b: RCMP2 = Comparison target (only during count-up). 011b: RCMP2 = Comparison target 12: 10 (only during count-down). 100b: RCMP2 > Comparison target. 101b: RCMP2 <...
Page 90 TA600137-EN0/0 Name Descrip�on Sets the processing when the condi�on of Comparator 3 is met. 00b: Do nothing. It can be used to output INT signals and CP3 signals, and to perform an internal synchroniza�on start. 22,21 01b: Stops immediately. 10b: Decelerate-stop. 11b: Overrides at a �me.
Page 91 TA600137-EN0/0 5.4.3.6 RENV5: Environment se�ng 5 LTOF LTFD PDSM CU4L CU3L CU2L CU1L ISMR MSMR Control commands : RRENV5(E0h)，WRENV5(A0h) Register to set the func�on of Comparator 5. Name Descrip�on Sets the comparison target of Comparator 5. 000b: RCUN1 001b: RCUN2 010b: RCUN3 011b: RCUN4 2: 0...
Page 92 TA600137-EN0/0 Name Descrip�on Sets the �ming to latch RCUN1 register to RLTC1 register. This se�ng also latches RCUN2 and 4 registers into RLTC2 and 4 registers. The target to be latched to RLTC3 register is selected by RENV5.LTFD bit. 13,12 00b: From LTC signal OFF to ON 01b: From ORG signal OFF to ON 10b: When the condi�on of comparator 4 is met.
Page 93 TA600137-EN0/0 Name Descrip�on Sets the func�on to clear counter 2 to 0 immediately a�er latching counter 2. CU2L 0: Not clear counter 2 to 0. 1: Clears counter 2 to 0. Sets the func�on to clear counter 3 to 0 immediately a�er latching counter 3. CU3L 0: Not clear counter 3 to 0.
Page 94 TA600137-EN0/0 5.4.3.7 RENV6: Environment se�ng 6 PSTS Control commands : RRENV6(E1h)，WRENV6(A1h) Register to set the correc�on data of feed amount. Name Descrip�on Sets the backlash correc�on amount or slip correc�on amount. 11:0 The se�ng range is 0 to 4,095. Sets the func�on to correct the feed amount. 13,12 00b: Not correct the feed amount 01b: Backlash correc�on...
Page 95 TA600137-EN0/0 5.4.3.8 RENV7: Environment se�ng 7 Control commands : RRENV7(E2h)，WRENV7(A2h) Register to set the control �me of vibra�on suppression func�on. Name Descrip�on Sets the cycle of a reverse pulse. 15: 0 The reverse pulse cycle is the dura�on of CLK 32 cycles mul�plied by the set value. The se�ng range is 0 to 65,535.
Page 96 TA600137-EN0/0 5.4.4 Counter register They are registers for counters. See "6.12 Counter" for counters. 5.4.4.1 RCUN1: Counter 1 (Command posi�on) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # # # # RCUN1 Control commands : RRCUN1(E3h)，WRCUN1(A3h)
Page 97 TA600137-EN0/0 5.4.4.3 RCUN3: Counter 3 (Devia�on) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # # # # # # # # # # # # # # # # RCUN3 Control commands : RRCUN3(E5h)，WRCUN3(A5h) Register to obtain the count value of counter 3 (devia�on).
Page 98 TA600137-EN0/0 5.4.5 Comparator register This is the register for comparators. For the comparator, see "6.13 Comparator". The # in bits 31 to 28 of each register is the same as bit 27 because they are sign extensions. If register se�ng is posi�ve and +134,217,727, you can read 07FFFFFFh. If register se�ng is nega�ve and-134,217,728, you can read F8000000h.
Page 99 TA600137-EN0/0 5.4.5.5 RCMP5(PRCP5): Comparator 5 comparison value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # # # # RCMP5(PRCP5) Control commands : RRCMP5(EBh)，...
Page 100 TA600137-EN0/0 5.4.6 Counter latch register This is the register for counter latch. Input of LTC and ORG signals or wri�ng of LTCH (29h) command can latch the count value of the corresponding counter. RLTC3 register can also latch the current speed step number. See "6.12.3 Counter latch"...
Page 101 TA600137-EN0/0 5.4.6.3 RLTC3: Counter 3 (Devia�on) latch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # # # # # # # # # # # # # # # # RLTC3 Control command: RRLTC3(EFh) Counter 3 (Devia�on), or the register to obtain the latch data of the current speed step number.
Page 102 TA600137-EN0/0 5.4.7 Interrupt register This is a register for interrupt control. For interrupts, see "6.18 Interrupt request (INT)". 5.4.7.1 RIRQ: Event interrupt request IROL IRLT IRCL IRC5 IRC4 IRC3 IRC2 IRC1 IRDE IRDS IRUE IRUS IRND IRNM IRN IREN IRSA IRDR IRSD Control commands : RRIRQ(ECh)，WRIRQ(ACh) Register to set the event interrupt request.
Page 103 TA600137-EN0/0 Name Descrip�on 1: An interrupt occurs when LTC signal is turned ON and the count value is latched. IRLT If the latching �ming is not a LTC signal. (RENV5.LTM ≠ 00b), no interrupt is generated. 1: An interrupt occurs when the ORG signal is turned ON and the count value is latched. IROL If the latching �ming is not ORG signal (RENV5.LTM ≠...
Page 104 TA600137-EN0/0 5.4.7.2 REST: Error interrupt factor ESAO ESPO ESIP ESDT ESSD ESEM ESSP ESAL ESML ESPL ESC5 ESC4 ESC3 ESC2 ESC1 ESPE ESEE Control commands : RREST(F2h)，WREST(B2h) Register to retrieve the error interrupt factor. For details on the error interrupt, see “6.18.1 Error interrupt." Name Descrip�on 1: An abnormal stop occurred when the comparison condi�on of Comparator 1 is met.
Page 105 TA600137-EN0/0 (4) The center posi�on is not set in the opera�on mode of circular interpola�on control. (Both axis are set to RIP register 0) (5) U-axis does not operate in the U-axis interpola�on control opera�on mode (RMD.MOD = 66h, 67h). The error occurs if U-axis stops ﬁrst in the opera�on mode of U-axis interpola�on control.
Page 106 TA600137-EN0/0 5.4.7.3 RIST: Event interrupt factor ISOL ISLT ISCL ISC5 ISC4 ISC3 ISC2 ISC1 ISDE ISDS ISUE ISUS ISND ISNM ISEN ISSA ISMD ISPD ISSD Control commands : RRIST(F3h)，WRIST(B3h) Register to obtain the event interrupt factor. For details on the Event interrupt, see "6.18.2 Event interrupt". Name Descrip�on ISEN 1: The opera�on mode stopped normally.
Page 107 TA600137-EN0/0 Name Descrip�on 1: +DR signal is changed. ISPD When PEn = H level, no interrupt is generated. 1: −DR signal is changed. ISMD When PEn = H level, no interrupt is generated. 1: CSTA pin is enabled (RENV1.PCSM = 0) and CSTA signal turns ON. ISSA Or CSTA pin is disabled (RENV1.PCSM = 1) and STA signal turns ON.
Page 108 TA600137-EN0/0 5.4.8 Status display register This register is for indica�ng the status. 5.4.8.1 RSTS: Extension status SDIN SLTC SCLR SDRM SDRP SERC SPCS SEMG SSTP SSTA SDIR SINP Control commands : RRSTS(F1h) Register to obtain the opera�on mode and the status of various signals. Name Descrip�on Indicates the opera�ng status.
Page 109 TA600137-EN0/0 Name Descrip�on Indicates the input status of CEMG signal. 0: OFF SEMG 1: ON The input logic of CEMG signal is nega�ve. Indicates the status of a signal input to PCSn pin. 0: OFF SPCS 1: ON The logic of a signal input to PCSn pin is selected by RENV1.PCSL bit. Indicates the output status of ERC signal.
Page 110 TA600137-EN0/0 Name Descrip�on Indicates the input status of SD signal. 0: OFF PSDI 1: ON The input logics of SD signals are selected by RENV1.SDL bit. Indicates the input status of INP signal. 0: OFF SINP 1: ON The input logic of an INP signal is selected by RENV1.INPL bit. MSDI 0 is always obtained.
Page 111 TA600137-EN0/0 5.4.8.2 RIPS: Interpola�on status IPFu IPFz IPFy IPFx IPSu IPSz IPSy IPSx IPEu IPEz IPEy IPEx IPLu IPLz IPLy IPLx IPCC IPCW Control commands: RRIPS(FFh) This register is to obtain the status of various interpola�on controls. Interpola�on status is shared by all axis in common. The same content can be read regardless of axis-selec�on.
Page 112 TA600137-EN0/0 Opera�on mode There are 45 opera�on modes to select with the combina�ons of control methods and movement methods. Selects the opera�on mode by RMD.MOD bit. Name and descrip�on Target <Opera�on mode selec�on> RMD.MOD(6:0) 000 0000 (00h): Opera�on mode of con�nuous movement in +direc�on in command control 000 1000 (08h): Opera�on mode of con�nuous movement in −direc�on in command control 000 0001 (01h): Opera�on mode of con�nuous movement in pulser control 000 0010 (02h): Opera�on mode of con�nuous movement in switch control...
Page 113 TA600137-EN0/0 5.5.1 Command control This control method is to stop with the stop command. 5.5.1.1 Con�nuous movement in plus direc�on (00h) Starts to output command pulses in +direc�on when started. Stops to output command pulses when wri�ng a stop command. When the command pulse stops, the opera�on mode is completed.
Page 114 TA600137-EN0/0 5.5.2.3 Specify the absolute posi�on by counter 2 (43h) Same as RMD.MOD = 42h, except that RCUN2 register is used instead of RCUN1 register. 5.5.2.4 Zero-point return by counter 1 (44h) With RMD.MOD = 42h, the opera�on is the same as when RMV = 0 is set. Other than RMV = 0, the RPLS register is also updated with RMV = 0.
Page 115 TA600137-EN0/0 5.5.3 Pulser control Each opera�on mode can be controlled in synchroniza�on with the inputs of PA and PB signals. It can be used when the input pin of PA, PB signal is enabled (PEn = L) and also the input func�on of PA, PB signal is enabled (RENV2.POFF = 0).
Page 116 TA600137-EN0/0 Three 90-degree phase diﬀerence modes are via the mul�plying circuit (1 to 32) and dividing circuit (n / 2048). Maximum 128 mul�plica�ons (90-degree phase diﬀerence mode 4x, 32 mul�plica�ons, no division). The mul�plica�on is set by RENV6.PMG bit, and the division is set with RENV6.PD bit. Input interface Multiplication Division circuit of...
Page 117 TA600137-EN0/0 When RENV6.PMG = 2 (3x) is set. DOWN1 DOWN2 When RENV6.PD = 512 (512/2048 division) is set. DOWN2 DOWN3 In synchroniza�on with UP3 and DOWN3 signals, the internal pulse of FH speed is output with some being omited. Therefore, the input �ming of PA / PB signals and the output �ming of command pulses will have a tolerance of the internal pulse cycle at the longest.
Page 118 TA600137-EN0/0 PIMG in the formula is as follows, depending on the se�ng of RENV2.PIM bit. RENV2.PIM PIMG 00b (90-degree phase diﬀerence mode 1x) 01b (90-degree phase diﬀerence mode 2x) 10b (90-degree phase diﬀerence mode 4x) 11b (2 pulse mode) The calcula�on examples including RENV6.PMG and RENV6.PD bit are as follows. RENV2.PIM RENV6.PMG RENV6.PD Calcula�on result...
Page 119 TA600137-EN0/0 If the input frequencies of PA signal and PB signal are not constant, the shortest cycle will become FP. FP cycle When stopping immediately with STOP (49h) command, the total output pulse does not necessarily the integral mul�ple of a mul�plica�on value.
Page 120 TA600137-EN0/0 Name and descrip�on Target <Numerator of PA signal and PB signal Input> RENV6.PD(26:16) 0: Do not divide. 1 to 2047: Divide by the se�ng value/2048. <Mul�plica�on of PA and PB Input> RENV6.PMG(31:27) 0 to 31: Mul�plies the se�ng value by adding 1. <Opera�on status>...
Page 121 TA600137-EN0/0 When PA or PB signal is input while wai�ng to be input for PA and PB signals (RSTS.CND = 1000b), command pulse starts outpu�ng. The coun�ng direc�on is determined as plus direc�on if RMV > 0 and as minus direc�on if RMV < 0. PA and PB signals and RENV2.PDIR do not aﬀect the coun�ng direc�on.
Page 122 TA600137-EN0/0 5.5.3.8 Incremental movement by linear interpola�on 1 (69h) Linear interpola�on 1 control is performed in synchroniza�on with PA and PB signal inputs. If a PA or PB signal is input while wai�ng for PA or PB signal input (RSTS.CND = 1000b), the command pulse will start to be output.
Page 123 TA600137-EN0/0 5.5.4 Switch control Each opera�on mode is controlled by the input of +DR and −DR signals as the trigger. This control can be used when PEn = L level. PEn pin allows you to switch between mul�ple axes with a set of drive switches. The connec�on method is the same as in a pulser control.
Page 124 TA600137-EN0/0 When coun�ng in posi�ve direc�on, the opera�on stops by + EL signal ON. When coun�ng in nega�ve direc�on, the opera�on stops by − EL signal ON. When RENV5.PDSM = 0, opera�on mode con�nues. The error interrupt is not generated when EL signal is stopped by ON in the opera�ng direc�on.
Page 125 TA600137-EN0/0 Inputs of +DR or −DR signal is enabled only while wai�ng for the input of +DR signal or −DR signal (RSTS.CND = 0001b). +DR signal opera�on example: STAFH STOP (1) Because they are edge triggers, not operate even if the opera�on mode is started with +DR signal ON. (2) Because of an incremental movement, the command pulse is stopped at RPLS = 0 even if the +DR signal is kept ON.
Page 126 TA600137-EN0/0 5.5.5 Origin return control This control method is to stop at the origin. Also see “6.8.2 Devia�on counter clear (ERC)” to control a servo motor. Input status of ORG signal can be checked with SSTS.SORG bit. Input logic of ORG signal can be set with RENV1.ORGL bit. ORG signal noises ﬁlter can be set with RENV1.FLTR bit.
Page 127 TA600137-EN0/0 Names and Descrip�ons Target <EA, EB, EZ signal Noise-in ﬁlter> RENV2.EINF(18) 0: Pulse signal width of 0.05 μs or greater are reliably reacted. 1: Pulse signal width of 0.10 μs or less are completely ignored. Pulse signal width of 0.15 μs or greater are reliably reacted. <Number of EZ signals (Default down-count value)>...
Page 128 TA600137-EN0/0 5.5.5.1 Origin return in + direc�on (10h) When started, this LSI starts to output command pulses in the +direc�on. When the condi�on for the origin return is met, command pulses are stopped. When the command pulses are stopped, the opera�on mode is completed. Use RENV3.ORM bit to set the origin return method.
Page 129 TA600137-EN0/0 Origin return 0 (0000b) Sets the posi�on where ORG signal turns ON from OFF as the origin. In FL and FH constant speed paterns, the opera�on stops at the origin posi�on. In high speed 1 and 2 speed paterns, the opera�on stops a�er passing the origin posi�on. Example: STAFL (50h) command Operates in the +direc�on with FL constant speed patern.
Page 130 TA600137-EN0/0 Origin return 1 (0001b) Sets the posi�on where ORG signal turns ON from OFF as the origin. Stops at the origin posi�on. Example: STAUD (53h) command Operates in the +direc�on with high speed 2 speed patern. Decelerate-stops when ORG signal is changed from OFF to ON. Operates in the −direc�on with FA constant speed.
Page 131 TA600137-EN0/0 Origin return 2 (0010b) Sets the posi�on where EZ signal is turned ON for the speciﬁed number of �mes as the origin a�er ORG signal turns ON from OFF. Stops at the origin posi�on. Example: STAUD (53h) command (RENV3.EZD = 0001b) Operates in the +direc�on with high speed 2 speed patern.
Page 132 TA600137-EN0/0 Origin return 3 (0011b) Sets the posi�on where the speciﬁed number of EZ signal is turned ON as the origin a�er ORG signal turns ON from OFF. Passes through the origin posi�on and stops in high speed 1 and 2 speed paterns. Example: STAUD (53h) command (RENV3.EZD = 0001b) Operates in the +direc�on with high speed 2 speed patern.
Page 133 TA600137-EN0/0 Origin return 4 (0100b) A�er stopping when ORG signal is changed from OFF to ON, reverses, and sets the posi�on where the speciﬁed number of EZ signal is turned ON as the origin. Stops at the origin posi�on. Example: STAUD (53h) command (RENV3.EZD = 0001b) Operates in the +direc�on with high speed 2 speed patern.
Page 134 TA600137-EN0/0 Origin return 5 (0101b) A�er stopping when ORG signal is changed from OFF to ON, reverses, and sets the posi�on where the speciﬁed number of EZ signal is turned ON as the origin. Passes through the origin posi�on and stops in high speed 1 and 2 speed paterns. Example: STAUD (53h) command (RENV3.EZD = 0001b) Operates in the +direc�on with high speed 2 speed patern.
Page 135 TA600137-EN0/0 Origin return 6 (0110b) Sets the posi�on where EL signal is changed from OFF to ON as the origin. Stops at the origin posi�on. Example: STAUD (53h) command (RENV1.ELM = 1, doted line) Operates in the +direc�on with high speed 2 speed patern. Decelerate-stops when + EL signal is changed from OFF to ON.
Page 136 TA600137-EN0/0 Origin return 7 (0111b) A�er stopping when +EL signal is changed from OFF to ON, reverses and operates at FA speed. Then, sets the posi�on where the speciﬁed number of EZ signal is changed ON as the origin. Stops at the origin posi�on. Example: STAUD (53h) command (RENV3.EZD = 0001b, RENV1.ELM=1, doted line) Operates in the +direc�on with high speed 2 speed patern.
Page 137 TA600137-EN0/0 Origin return 8 (1000b) A�er stopping when +EL signal is changed from OFF to ON, reverses and then sets the posi�on where the speciﬁed number of EZ signals turn ON as the origin. Passes through the origin posi�on and stops in high speed 1 and 2 speed paterns. Example: STAUD (53h) command (RENV3.EZD = 0001b, RENV1.ELM = 1, doted line) Operates in the +direc�on with high speed 2 speed patern.
Page 138 TA600137-EN0/0 Origin return 9 (1001b) Sets the posi�on where ORG signal is changed from OFF to ON as the origin. A�er the origin return 0 opera�on, returns to zero point (operate un�l RCUN2 = 0). Stops at the origin posi�on. Set the encoder as the count target of counter 2.
Page 139 TA600137-EN0/0 Origin return 10 (1010b) A�er stopping when ORG signal is changed from OFF to ON, sets the posi�on where the speciﬁed number of EZ signal is turns ON as the origin. A�er an origin return 3 opera�on, returns to zero point (operates un�l RCUN2 = 0). Stops at the origin posi�on.
Page 140 TA600137-EN0/0 Origin return 11 (1011b) A�er stopping when ORG signal is changed from OFF to ON, reverses, and sets the posi�on where the speciﬁed number of EZ signal turns ON as the origin. A�er an origin return 5 opera�on, returns to zero point (operates un�l RCUN2 = 0). Stops at the origin posi�on.
Page 141 TA600137-EN0/0 Origin return 12 (1100b) A�er stopping when +EL signal is changed from OFF to ON, reverses, and sets the posi�on where the speciﬁed number of EZ signal turns ON as the origin. A�er the origin return 8 opera�on, returns to zero point (operates un�l RCUN2 = 0). Stops at the origin posi�on.
Page 142 TA600137-EN0/0 5.5.5.2 Origin return in the –direc�on (18h) Operates in the same way as "5.5.5.1 Origin return in + direc�on (10h)" except that the opera�on direc�on and EL signal are reversed. 5.5.5.3 Escape from the origin posi�on in the +direc�on (12h) When started, operates in the +direc�on un�l escaping from ORG signal ON.
Page 143 TA600137-EN0/0 2. When ORG signal is ON, performs "incremental movement" in the −direc�on. "Incremental movement" in the −direc�on repeats un�l ORG signal turns OFF. A�er "Incremental movement", when ORG signal turns OFF, performs "return to origin in the +direc�on". When ORG signal turns ON, the opera�on mode is completed. The ﬁgure below shows the case of Origin return 0 (RENV3.ORM = 0) and STAFL (50h).
Page 144 TA600137-EN0/0 5.5.5.6 Origin search in the –direc�on (1Dh) Operates in the same way as "5.5.5.5 Origin search in the +direc�on (15h)" except that the opera�on direc�on and EL signal are reversed. - 139 -...
Page 145 TA600137-EN0/0 5.5.6 Sensor control This control is to stop by +EL signal, −EL signal, +SL posi�on, −SL posi�on, or EZ signal. The input status of + EL signal can be checked with SSTS.SPEL bits. The input status of - EL signal can be checked with SSTS.SMEL bits. Input logic of + EL signal and-EL signal can be set at ELL pin.
Page 146 TA600137-EN0/0 Name and descrip�on Target <EA, EB and EZ input noise ﬁlters> RENV2.EINF (18) 0: Signals with a pulse width of 0.05 μs or greater are reliably reacted 1: Signals with a pulse width 0.10 μs or less are completely ignored. Signals with a pulse width of 0.15 μs or greater are reliably reacted.
Page 147 TA600137-EN0/0 5.5.6.5 Move in the +direc�on for a speciﬁed number of EZ counts (24h) When started, operates in the +direc�on un�l EZ signal turns ON for the speciﬁed number of �mes. Use FL constant speed or FH constant speed for the speed patern. When EZ signal turns ON for the speciﬁed number of �mes, the command pulse is stopped.
Page 148 TA600137-EN0/0 5.5.7 Linear interpola�on 1 control This control is to use a PCL6045BL LSI to perform a linear interpola�on opera�on by any two to four axes. The remaining axes can perform other opera�ons than the linear interpola�on 1 control. The speed is set on the interpola�on control axis. The interpola�on control axes are assigned in the order of X, Y, Z-axis among the interpola�on axes.
Page 149 TA600137-EN0/0 5.5.7.1 Con�nuous movement (60h) When started, outputs the command pulses in the +direc�on if RMV > 0 and in the −direc�on if RMV <0. If the same opera�on mode (RMD.MOD = 60h) has been set only to one axis, REST.ESDT = 1 will be set, and an opera�on will stop without outpu�ng a command pulse.
Page 150 TA600137-EN0/0 5.5.7.2 Incremental movement (61h) When started, outputs the command pulses in the +direc�on if RMV > 0 and in the −direc�on if RMV <0. If the same opera�on mode (RMD.MOD = 61h) has been set only to one axis, REST.ESDT = 1 will be set, and an opera�on will stop without outpu�ng a command pulse.
Page 151 TA600137-EN0/0 5.5.8 Linear interpola�on 2 control This control is to use one or more PCL6045BL and performs linear interpola�on on any one or more axes. With mul�ple PCL6045BLs, you can start linear interpola�ons on any ﬁve or more axes for synchronous opera�on with equal opera�ng �me.
Page 152 TA600137-EN0/0 5.5.8.1 Con�nuous movement (62h) When started, the command pulse starts to be output in the +direc�on if RMV > 0 and in the −direc�on if RMV < 0. The main axis is the axis whose absolute value of RMV register is the largest in Interpola�on opera�on axis. Following axis is Interpola�on opera�on axis other than the main axis.
Page 153 TA600137-EN0/0 5.5.8.2 Incremental movement (63h) When started, the command pulse starts to be output in the +direc�on if RMV > 0 and in the −direc�on if RMV < 0. If either interpola�on opera�on axis is with RIP = 0, REST.ESDT = 1 will be set, and an opera�on will stop without outpu�ng a command pulse.
Page 154 TA600137-EN0/0 5.5.9 Circular interpola�on control This control is to use a single PCL6045BL to perform a circular interpola�on by any two axes. The remaining two axes can perform other opera�ons other than a circular interpola�on control. The speed is set to the interpola�on control axes. The interpola�on control axes are assigned in the order of X, Y, Z-axis in the interpola�on axes.
Page 155 TA600137-EN0/0 5.5.9.1 Circular interpola�on in CW (64h) When started, it starts outpu�ng command pulses so that two axes draw a circle in CW direc�on. If REST.ESDT = 1 is set, the opera�on mode is canceled without outpu�ng the command pulse. For the REST.ESDT bit, see "5.4.7.2 REST: Error interrupt factor ".
Page 156 TA600137-EN0/0 Circular interpola�on completes the interpola�on opera�on where one axis reaches the end-point in the end-point quadrant. Therefore, even if the circular interpola�on opera�on is completed, the speciﬁed end-point coordinates may not be reached. If you want to automa�cally move to the end-point coordinates outside the circular a�er the circular interpola�on opera�on is completed, set the end-point draw opera�on.
Page 157 TA600137-EN0/0 5.5.10 U-axis synchronous control This control uses one PCL6045BL to synchronize with U-axis and perform circular interpola�on by the remaining two axes. Helical interpola�on is available for applica�ons such as threading and drilling. With remaining axes, you can perform opera�ons other than a circular interpola�on. The speed is set on the interpola�on control axis.
Page 158 TA600137-EN0/0 Circular interpola�on accuracy: Circular interpola�on draws an arc from the present coordinate to the end-point coordinate. The ﬁgure on the right shows an example of drawing a perfect circle with a radius of 11. When in circular interpola�on, posi�on value accuracy for the speciﬁed curve is ±...
Page 159 TA600137-EN0/0 5.5.10.1 Circular interpola�on with U-axis synchroniza�on in CW (66h) When started, command pulses are output so that two axes draw a circle in CW direc�on in synchroniza�on with U-axis. If REST.ESDT = 1 is set, the opera�on mode is canceled without outpu�ng the command pulse. For REST.ESDT bit, see "5.4.7.2 REST: Error interrupt factor".
Page 160 TA600137-EN0/0 6. Func�on descrip�on This chapter describes the features of PCL6045BL. Reset There are two types of reset in PCL6045BL: hardware reset and so�ware reset. A�er rese�ng, PCL6045BL will be in the default status shown in the table below. Item Default Register Pre-register...
Page 161 TA600137-EN0/0 6.1.1 Hardware reset In PCL6045BL, you need to input RST signal to RST pin before CPU communica�on is started a�er the power is turned ON. For RST signal, input an L level signal of 8 cycles or more of CLK signal and an H level signal of 8 cycles or more of CLK signal. Power High High...
Page 162 TA600137-EN0/0 Pre-register In an opera�on mode, the start command is writen a�er the opera�on se�ngs such as speed control and posi�on control are writen to the register. If the next opera�on se�ng is writen to a register a�er the opera�on mode is completed, the opera�on stops during this wri�ng �me.
Page 163 TA600137-EN0/0 6.2.1 Con�nuous opera�on The data writen to 2nd pre-register during stop, can shi� to the current register and also becomes the current data. During opera�on, it shi�s to 1st pre-register and becomes the data for 1st con�nuous opera�on. If 1st pre-register is determined during opera�on, it will not shi�...
Page 164 TA600137-EN0/0 2nd pre- 1st pre- Current RSTS. MSTS. Method register register register SPRF Data 1 completes the opera�on mode. Data 2 is copied to the current register. Data 3 is copied to the 1st pre-register. Data 3 Data 3 Data 2 Start the opera�on with data 2 and start command 2.
Page 165 TA600137-EN0/0 Name and descrip�on Target <Main status (SPRF)> MSTS.SPRF(14) 0: 2nd pre-register for con�nuous opera�on is undetermined. 1: 2nd pre-register for con�nuous opera�on is determined. <Main status (SSC)> MSTS.SSC(7,6) Sequence number (RMD.MSN) during opera�on or when stopped. When you create a user program, you can manage the blocks in opera�on. The sequence number does not aﬀect opera�on.
Page 166 TA600137-EN0/0 6.2.2 Con�nuous comparison When RSTS.PFC = 0, the data writen to 2nd pre-register (PRCP5) is shi�ed to the current register (RCMP5). At this �me, RCMP5 register is determined, and the write data becomes the current data. When RSTS.PFC = 1, data is shi�ed to 1st pre-register for 1st con�nuous comparison. When RSTS.PFC = 2, it does not shi�.
Page 167 TA600137-EN0/0 An interrupt request can be set to enable wri�ng (RIRQ.IRND = 1) to 2nd pre-register for con�nuous comparison (PRCP5). This se�ng can generate an interrupt factor that can be writen to PRCP5 register (RIST.ISND = 1). This interrupt factor occurs when PRCP5 register changes to undetermined (MSTS.SPDF = 1 to 0). Con�nuous comparison data can be shi�ed by PCPSHF(2Ch) command.
Page 168 TA600137-EN0/0 Speed control This sec�on describes the speed control func�ons such as speed paterns selected by opera�on commands and speed se�ng examples. 6.3.1 Speed paterns Describes the speed paterns selected by opera�on commands. Speed patern Con�nuous movement opera�on mode Incremental movement opera�on mode (1) Executes STAFL (50h) command (1) Executes STAFL (50h) command FL constant speed...
Page 169 TA600137-EN0/0 6.3.2 Speed se�ng example The following applies to �� = 19.6608 MHz、 FL speed ＝10 pps、 FH speed ＝100 kpps、 Accleration time ＝300 ms、 The procedure of speed se�ng is shown below. See "5.4.1 Speed control register" for each calcula�on formula. ��...
Page 170 TA600137-EN0/0 6.3.3 Manual correc�on calcula�on of the target speed When accelera�ng or decelera�ng in an opera�on mode that allows you to set a target posi�on, the speed patern may become triangular drive. The target is RMD.MOD = 41h, 42h, 43h, 44h, 45h, 51h, 52h, 53h, 54h, 55h, 56h, 61h, 64h, 65h, 66h, 67h, 69h, 6Ch, 6Dh and 6Fh.
Page 171 TA600137-EN0/0 6.3.3.1 Linear accelera�on/decelera�on The FH speed in linear accelera�on / decelera�on (RMD.MSMD = 0) is calculated by the following formula. ( �� ) × ( �� + �� + 2 ) − �� ≦ ( �� + 1 ) × 32768 ( ��...
Page 172 TA600137-EN0/0 RUS < RDS ( �� + �� ) × � ( �� − �� ) × ( �� + �� + 2 ) + 2 × �� × ( �� + 1 ) + 2 × �� × ( �� + 1 ) � ��...
Page 173 TA600137-EN0/0 RUS > RDS ( �� + �� ) × � ( �� − �� ) × ( �� + �� + 2 ) + 2 × �� × ( �� + 1 ) + 2 × �� × ( �� + 1 ) � ��...
Page 174 TA600137-EN0/0 6.3.4 Target speed override The target speed can be overridden (speed change) by re-wri�ng RFH, RUR, RDR, RUS, and RDS registers during opera�on. While opera�ng in the FL and FH constant-speed paterns, the speed changes to the new speed without accelera�ng or decelera�ng.
Page 175 TA600137-EN0/0 6.3.5 Circular interpola�on step number When performing accelera�on/decelera�on opera�ons in the circular interpola�on, you need to set the circular interpola�on step number (RCI). When the speed patern is in high-speed 1 or high-speed 2, the interpola�on control axis starts decelera�ng at RCIC <...
Page 176 TA600137-EN0/0 To ﬁnd the number of circular interpola�on steps at any start and end- points as shown on the right, follow the procedures below: (1) Specify which area the start point S belongs to out of the areas 0 to 7 from the center point and ﬁnd the intersec�on of the Radius a 半径a perpendiculars drawn from the start point to the inscribed...
Page 177 TA600137-EN0/0 6.3.6 Constant synthesized speed control Constant synthesized speed control is a func�on to keep the synthesized speed of the axes that perform linear interpola�on 1 control or circular interpola�on control constant. Opera�on mode MRD.MIPF = 1 Descrip�on Linear interpola�on 1 control (60h, 61h) Enabled ○...
Page 178 TA600137-EN0/0 Posi�on control This sec�on describes posi�on control func�ons such as re-wri�ng RMV registers and wai�ng for PCS signal input. 6.4.1 Target posi�on override 1 (RMV) Target posi�on override 1 is available in RMD.MOD = 41h, 42h, 43h and 47h opera�on modes. In other modes of opera�on, do not re-write RMV register during opera�on.
Page 179 TA600137-EN0/0 If the opera�on mode is an incremental posi�on of posi�oning control (RMD.MOD = 41h), the new target posi�on will be the incremental posi�on from the start. For example, if the target posi�on is overridden RMV = 200 when RPLS = 50 during running at RMV = 100, it will be recalculated to RPLS = 150, neither overwriten (RPLS = 200) nor added (RPLS = 250).
Page 180 TA600137-EN0/0 The target posi�on override is enabled only during opera�on (FL constant speed, FH constant speed, accelera�on, decelera�on, backlash correc�on). If you override just before stopping, the override may not be accepted. If the target posi�on override is ignored, it will be set to (MSTS.SEOR = 1). This happens when wri�ng to RMV register in the stopped status.
Page 181 TA600137-EN0/0 6.4.2 Target posi�on override 2 (PCS) Target posi�on override 2 (RMD.MPCS = 1) can be used in the opera�on modes of RMD.MOD = 41h. Do not use the target posi�on override 2 in other modes of opera�on. The minimum pulse width of PCS signal requires 2 cycles (0.1 μs) of the CLK signal. The PCS signal is sampled in synchroniza�on with the CLK signal a�er the opera�on mode starts.
Page 182 TA600137-EN0/0 <Input func�on of CSTA pin and PCSn pin> RENV1.PCSM(30) 0: CSTA pin input is enabled. The PCSn pin reﬂects the se�ng of the RMD.MPCS bit. 1: CSTA pin input is disabled. The PCSn pin also inputs the STA signal for star�ng only the own axis. RENV1.PCSM = 0 RENV1.PCSM = 0 RENV1.PCSM = 1...
Page 183 TA600137-EN0/0 6.4.3 End-point-draw opera�on If you set the end-point outside the arc in circular interpola�on opera�on, you can move to the end-point in a straight line when the circular interpola�on ends. This opera�on is called “End-point-draw opera�on.” The end-point is not on the arc, except for the arc angle, which is an integral mul�ple of 90-degree. Therefore, when the end point-draw opera�on is disabled (RMD.MPIE = 0), the speciﬁed end-point is not reached.
Page 184 TA600137-EN0/0 Output pulse control You can select the output pulse mode, output pulse width control, and the opera�on mode comple�on �ming. 6.5.1 Output pulse mode The output pulse mode can be selected with RENV1.PMD bit according to the input format of a motor driver. There are 4 types of common pulse modes, Two types of 2-pulse modes, and two types of 90-degree phase diﬀerence modes.
Page 185 TA600137-EN0/0 Set the direc�on change �mer �me. RENV1.DTMF(28) 0: If RENV1.PMD = 000b to 011b, wait 0.2 ms for pulse output a�er changing direc�ons. 1: If RENV1.PMD = 000b to 011b, wait 0.5 μs for pulse output a�er changing direc�ons. - 180 -...
Page 186 TA600137-EN0/0 6.5.2 Opera�on complete �ming By se�ng the ﬁnal pulse ON width completed (RMD.METM = 1), the opera�on mode can be completed without wai�ng for the comple�on of the ﬁnal pulse cycle. Since the motor driver operates on the edge of the output pulse, the OFF width of the ﬁnal pulse is not required. For example, if the FL speed stops at 1 pps, the ﬁnal pulse OFF width of 500 ms is not required if the duty ra�o is set to 50 %.
Page 187 TA600137-EN0/0 <Opera�ng signal> MSTS.SRUN(1) 0: Stopping: BSYn pin outputs H-level. 1: Opera�ng: BSYn pin outputs L-level. - 182 -...
Page 188 TA600137-EN0/0 6.5.3 Output pulse width control �� 8192 �� × 4096 (0.2 ms). If it is more than this, the output pulse width will ﬂuctuate with a duty ra�o of 50%. When the output speed of a command pulse is (2.4 kpps) or less, the output pulse width is ﬁxed narrowly to ��...
Page 189 TA600137-EN0/0 Idling control At the start of accelera�on of a stepping motor, the ﬁrst few pulses can be output at FL speed and then accelera�on can start. The pulse outpu�ng is called idling pulses, and the occurrence of step-out can be reduced. Set the number of idling pulses to RENV5.IDL bit.
Page 190 TA600137-EN0/0 Mechanical external input control In addi�on to the termina�on switch (+ELn, −ELn), origin switch (ORGn), and decelera�on switch (SDn) that are assembled in an actuator like a slider in the ﬁgure below, the Z-phase (EZn) output of a rotary encoder can be used as an external input trigger to perform a various controls.
Page 191 TA600137-EN0/0 Name and descrip�on Target <Input logic of EL signal in the opera�on direc�on> ELLn pin L: Posi�ve logic H: Nega�ve logic <Input processing of EL signal in the opera�on direc�on> RENV1.ELM(3) 0: Immediate stop 1: Decelerate-stop <Input noise ﬁlter for +EL, −EL, +SD, −SD, ORG, ALM, INP, CEMG signals > RENV1.FLTR(26) 0: Signal with the pulse width of 0.05 μs or more reacts reliably 1: Signals with the width of 3 μs or less is ignored completely...
Page 192 TA600137-EN0/0 6.7.2 Slow-down (SD) The input func�on (RMD.MSDE) of SD pins can be selected. If SD signal is ON and decelera�on or decelera�on stop (RMD.MSDE = 1) is set, SD signal will be enabled during opera�on. You can select (1) decelera�on, (2) latch & decelera�on, (3) decelera�on stop, and (4) latch & decelera�on stop, with RENV1.SDM bit and RENV1.SDLT bit.
Page 193 TA600137-EN0/0 (3) Decelera�on stop <RENV1.SDM = 1, RENV1.SDLT = 0> • In FL constant and FH constant speed paterns, if SD signal turns ON, the opera�on stops immediately. • In high-speed 1 and 2 speed paterns, if SD signal turns ON, the opera�on decelerates to FL speed and stops. In this case, if SD signal turns OFF during decelera�on, it accelerates to FH speed.
Page 194 TA600137-EN0/0 The Input noise ﬁlter (RENV1.FLTR) of SD signals can be selected. Abnormal stop due to SD signals can be read by the error interrupt factor (REST.ESSD). The input status of SD signals can be read by the extended status (RSTS.SDIN). The latch status of SD signals can be read by the extended status (RSTS.SSD).
Page 195 TA600137-EN0/0 6.7.3 Origin (ORG), Encoder Z phase (EZ) ORG signal and EZ signal are used in the origin return control mode. EZ signal is also used in some opera�on modes in sensor controls (RMD.MOD = 24h, 2Ch). The input logic (RENV1.ORGL) of ORG signal can be selected. The input noise ﬁlter (RENV1.FLTR) of ORG pin can also be selected.
Page 196 TA600137-EN0/0 Name and descrip�on Target <Opera�on mode using ORG signal and EZ signal> RMD.MOD(6:0) 10h: Opera�on mode for origin return in the + direc�on in origin return control 18h: Opera�on mode for origin return in the − direc�on in origin return control 12h: Opera�on mode to escape from the origin posi�on in the + direc�on by origin return control 1Ah: Opera�on mode to escape from the origin posi�on in the −direc�on by origin return control 15h: Opera�on mode for origin search in the + direc�on by origin return control...
Page 197 TA600137-EN0/0 Servo motor driver interface You can connect dedicated signals to a servo motor driver. The dedicated signals are: posi�oning complete output (INP), devia�on counter clear input (ERC) and alarm output (ALM). You can use the signals to perform various controls. 6.8.1 Posi�oning complete (INP) Servo motor drivers can output INP (In-posi�on) signals.
Page 198 TA600137-EN0/0 6.8.2 Devia�on counter clear (ERC) An ERC (Error/Deﬂec�on counter clear) signal can be input to a servo motor driver. Servo motor drivers do not stop servo controls un�l the devia�on counter reaches 0. Therefore, even if command pulses stop, servo motors do not stop immediately.
Page 199 TA600137-EN0/0 The output logic (RENV1.ERCL) of the ERC signal can be selected. The output status of the ERC signal can be read by the extended status (RSTS.SERC). Name and descrip�on Target <ERCn pin output func�on at the �me of immediate stop due to an abnormal stop factor> RENV1.EROE(10) 0: Does not output the ERC signal at the �me of immediate stop due to an abnormal stop factor.
Page 200 TA600137-EN0/0 6.8.3 Alarm (ALM) A servo motor driver can output an ALM signal. Servo motor drivers may experience abnormali�es such as overload or overcurrent. To no�fy that the abnormality has occurred, the servo motor driver can output an ALM signal. If ALM signal is input to ALMn pin while it is in opera�on (RSTS.CND ≠...
Page 201 TA600137-EN0/0 External start / Simultaneous start You can start with an external signal using CSTA and PCSn pins. Also, you can use CSTA pin to start mul�ple axes at the same �me. 6.9.1 Simultaneous start (CSTA) You can start externally by inpu�ng a one-shot pulse CSTA signal or level signal to CSTA pin. By connec�ng the CSTA pins of mul�ple PCL6045BLs, the axes of mul�ple PCL6045BLs can be started at the same �me.
Page 202 TA600137-EN0/0 1. Write the CMSTA (06h) command Output CSTA signals with the pulse width of 8 CLK signal cycles (0.4 μs) from the CSTA pin. All PCL6045BLs whose CSTA terminals are connected to each other will start if CSTA signal is input and CSTA signal is enabled.
Page 203 TA600137-EN0/0 <Opera�ng status> RSTS.CND(3:0) 0010b: Wai�ng for CSTA signal input. <CSTA signal input status> RSTS.SSTA(5) 0: OFF 1: ON <CSTA signal output> CMSTA(06h) CSTA signal is output from CSTA pin. Opera�on mode can be started on all axes that are wai�ng for CSTA signal input status (RSTS.CND = 0010b).
Page 204 TA600137-EN0/0 6.9.2 Own axis start (STA) External start can be performed by inpu�ng STA signal (one-shot pulse) to PCSn pin. By using any PCSn pin, you can start any axis on its own. As a prepara�on, set CSTA and STA signal input wait (RMD.MSY = 01b) and STA signal input (RENV1.PCSM = 1). If you write a start command with this se�ng, you can enter the CSTA and STA signal input wai�ng state (RSTS.CND = 0010b).
Page 205 TA600137-EN0/0 Name and descrip�on Target <Input func�on of CSTA pin and PCSn pin > RENV1.PCSM(30) 0: Input of CSTA pin is enabled. Se�ng in RMD.MPCS bit is reﬂected in PCSn pin. 1: Input of CSTA pin is disabled. STA signal to start only own axis is input in PCSn pin. <Interrupt request (IRSA)>...
Page 206 TA600137-EN0/0 6.9.3 Axis selec�on start (SELn) By using axis selec�on (SELn), PCL6045BL can write the same command to mul�ple axes at the same �me. At this �me, if one PCL6045BL is used, mul�ple axes can be started at the same �me by wri�ng a start command. So�ware example (H8): var Address = // Address: COMW of X-axis...
Page 207 TA600137-EN0/0 External stop / Simultaneous stop You can use CSTP pin to stop immediately or decelerate-stop with external signals. You can also stop simultaneously using CSTP pin. 6.10.1 Simultaneous stop (CSTP) You can externally stop by inpu�ng the CSTP signal (one-shot pulse signal) to the CSTP pin. By using the CSTP pins of mul�ple PCL6045BLs, each axis of mul�ple PCL6045BLs can be stopped simultaneously.
Page 208 TA600137-EN0/0 Input a one-shot pulse with the pulse width of 4 cycles (0.2 μs) or more of the CLK signal from the outside to CSTP pin. All PCL6045BLs connected by the CSTP pins input a one-shot pulse to stop the eﬀec�ve axis. PCL6045BL PCL6045BL PCL6045BL...
Page 209 TA600137-EN0/0 6.10.2 Axis selec�on stop (SELn) PCL6045BL can write the same command to mul�ple axes using axis selec�on (SELn). At this �me, if there is only one PCL6045BL, mul�ple axes can be stopped simultaneously by wri�ng a stop command. So�ware example (H8): var Address = // Address: COMW of X-axis 0x3：...
Page 210 TA600137-EN0/0 Emergency stop CEMG pin can be used to perform an emergency stop on all axes with an external signal. An emergency stop can be performed by inpu�ng CEMG signal (one-shot pulse signal) to CEMG pin. By connec�ng mul�ple CEMG pins of mul�ple PCL6045BLs, all axes can be stopped in an emergency. You cannot start while CEMG = L level.
Page 211 TA600137-EN0/0 C a u t i o n In an emergency stop opera�on, the ﬁnal pulse width cannot be secured, and a spike-like pulse may occur. When a spike-like pulse occurs, the command posi�on and the mechanical posi�on may deviate. (The motor driver cannot accept the pulse, only the command posi�on counter counts) Therefore, a�er an emergency stop, return to the origin and match the command posi�on with the mechanical posi�on.
Page 212 TA600137-EN0/0 Counter The counters includes the counter for the number of remaining pulses (RPLS) and counters 1 through 4. For “Remaining pulse number", see "5.4.2.7 RPLS: Remaining pulse number” and "5.5.2 Posi�oning control.” We explain on Counters 1 to 4 in this sec�on. 6.12.1 Counter types and input speciﬁca�ons You can use the four counters to perform the following func�ons: •...
Page 213 TA600137-EN0/0 6.12.1.1 Encoder (EA, EB) signal count For the encoder (EA, EB) signal, the input noise ﬁlter (RENV2.EINF) can be selected. The input speciﬁca�ons can be selected with RENV2.EIM bit, and the coun�ng direc�on can be selected with RENV2.EDIR bit. 90-degree phase diﬀerence mode (1x) (RENV2.EIM = 00b) Counter Count-up:...
Page 214 TA600137-EN0/0 If RENV2.EDIR = 1 is set, the coun�ng direc�on will be reversed. Se�ng RENV2.EOFF = 1 disables the inputs of EA and EB signals. EA and EB signal input errors can be read by the error interrupt factor (REST.ESEE). It occurs when EA and EB signal inputs change simultaneously in 90-degree phase diﬀerence mode.
Page 215 TA600137-EN0/0 6.12.1.2 Manual pulser signal (PA, PB) count The input noise ﬁlter (RENV2.PINF) for manual pulser signals (PAn, PBn) can be selected. The input speciﬁca�ons can be selected with RENV2.PIM bit, and the count direc�on can be selected with RENV2.PDIR bit. For RENV2.PIM bit, see "5.5.3 Pulser control".
Page 216 TA600137-EN0/0 6.12.2 Counter clear Counters 1 to 4 can be cleared by the following 5 methods. • CLR signal ON (RENV3.CU1C, CU2C, CU3C and CU4C) • Arriving the origin posi�on in origin return control (RENV3.CU1R, CU2R, CU3R and CU4R) • Immediately a�er latching the counter (RENV3.CU1L, CU2L, CU3L and CU4L) •...
Page 217 TA600137-EN0/0 Name and descrip�on Target <Clear counter 3 when the origin is reached in origin return control > RENV3.CU3R(22) 0: Not clear 1: Clear <Clear counter 4 when the origin is reached in origin return control > RENV3.CU4R(23) 0: Not clear 1: Clear <Clear counter 1 to 0 immediately a�er latching counter 1>...
Page 218 TA600137-EN0/0 6.12.3 Counter latch All counter values can be latched at once at one of the following ﬁve �mings: • When LTC signal is changed from OFF to ON. • When ORG signal is change from OFF to ON. • When Comparator 4 condi�on is met. •...
Page 219 TA600137-EN0/0 Name and descrip�on Target <Event interrupt request (IRLT)> RIRQ.IRLT(14) 1: When RENV5.LTM = 00b is set, an interrupt occurs when LTC signal turns ON. <Event interrupt request (IROL)> RIRQ.IROL(15) 1: When RENV5.LTM = 01b is set, an interrupt occurs when ORG signal turns ON. <Event interrupt factor (ISLT)>...
Page 220 TA600137-EN0/0 6.12.4 Counter count stop and input stop Counter 1 is stopped in three ways as follows: It will not count if RMD.MOD = 47h is set. ・ It will not count if RMD.MCCE = 1 is set. ・ It does not count during backlash correc�on and slip correc�on opera�ons if RENV3.CU1B = 0 is set. ・...
Page 221 TA600137-EN0/0 Name and descrip�on Target <Counter 2 coun�ng func�on> RENV3.CU2H(29) 0: Counts. 1: Does not count. Pulses can be output while counter 2 stops coun�ng. <Counter 3 coun�ng func�on> RENV3.CU3H(30) 0: Counts. 1: Does not count. Pulses can be output while counter 3 stops coun�ng. <Counter 4 count>...
Page 222 TA600137-EN0/0 Comparator PCL6045BL has a built-in 28-bit comparator with 5 circuits/axis. 6.13.1 Comparator types and func�ons Using RENV4 register and RENV5 register, you can select the comparison target, comparison condi�on, and processing method with a comparator when the comparison condi�ons are met. 6.13.1.1 Comparator comparison target Comparator 1 Comparator...
Page 223 TA600137-EN0/0 Name and descrip�on Target <Comparison target of Comparator 3> RENV4.C3C(17,16) 00b: RCUN1 01b: RCUN2 10b: RCUN3 11b: RCUN4 If RENV4.C3C = 10b, compare with the absolute value in RCUN3 register (0 to 32,767). <Comparison target of Comparator 4> RENV4.C4C(25,24) 00b: RCUN1 01b: RCUN2 10b: RCUN3...
Page 224 TA600137-EN0/0 * 2 The condi�on is met only when coun�ng up. * 3 The condi�on is met only when coun�ng down. For "+SL, -SL signal output (so�ware limit)", see "6.13.2 So�ware limit". For "IDX signal output", see "6.13.4 Index output". For "Counter 1 Ring Count"...
Page 225 TA600137-EN0/0 Name and descrip�on Target <Comparator 3 comparison condi�ons> RENV4.C3S(20:18) 001b: RCMP3 = Comparison target. (Regardless of coun�ng direc�on) 010b: RCMP3 = Comparison target. (Only when coun�ng up) 011b: RCMP3 = Comparison target. (Only when coun�ng down) 100b: RCMP3 > Comparison target. 101b: RCMP3 <...
Page 226 TA600137-EN0/0 Name and descrip�on Target <Comparator 5 comparison condi�ons> RENV5.C5S(5: 3) 001b: RCMP5 = Comparison target. (Regardless of coun�ng direc�on) 010b: RCMP5 = Comparison target. (Only when coun�ng up) 011b: RCMP5 = Comparison target. (Only when coun�ng down) 100b: RCMP5 > Comparison target. 101b: RCMP5 <...
Page 227 TA600137-EN0/0 Name and descrip�on Target <Processing when the condi�on of Comparator 3 is met> RENV4.C3D(22,21) 00b: No ac�on. It can be used to output INT signals and CP3 signals, and to start internal synchroniza�on. 01b: Immediate stop. 10b: Decelera�on stop. 11b: Bulk override.
Page 228 TA600137-EN0/0 Name and descrip�on Target <Event interrupt factor (ISC3)> RIST.ISC3(10) 1: The comparison condi�on of Comparator 3 is met. (MSTS.SCP3 changed from 0 to 1) <Event interrupt factor (ISC4)> RIST.ISC4(11) 1: The comparison condi�on of Comparator 4 is met. (MSTS.SCP4 changed from 0 to 1) <Event interrupt factor (ISC5)>...
Page 229 TA600137-EN0/0 Name and descrip�on Target <P7n pin I/O func�on> RENV2.P7M(15,14) 10b: Outputs the CP5 signal as a nega�ve logic level signal while the comparator 5 condi�on is met. 11b: Outputs the CP5 signal as a posi�ve logic level signal while the comparator 5 condi�on is met. <Output �ming of internal synchroniza�on signal>...
Page 230 TA600137-EN0/0 6.13.2 So�ware limit You can use so�ware limits with Comparator 1 (RCMP1) and Comparator 2 (RCMP2). If the condi�on of +SL (Comparator 1) is met while opera�ng in the +direc�on, the opera�on will stop abnormally. If the condi�on of −SL (Comparator 2) is met while opera�ng in the−direc�on, the opera�on will stop abnormally. Set a counter other than counter 3 for the comparison target of comparator 1.
Page 231 TA600137-EN0/0 Name and descrip�on Target <Comparator 2 comparison condi�ons> RENV4.C2S(12:10) 110b: −Side so�ware limit (RCMP2 > comparison target) <Processing when the condi�on of Comparator 2 is met> RENV4.C2D(14,13) 01b: Immediate stop. 10b: Decelera�on stop. If RENV4.C2S = 110b is set, the opera�on will stop immediately even if RENV4.C2D = 00b, 11b is set. <Error interrupt factor (CP1 / +SL)>...
Page 232 TA600137-EN0/0 6.13.3 Out-of-step detec�on of stepping motor By se�ng the counter 3 count value (RCUN3) as the comparison target, out-of-step with a stepping motor can be detected. Counter 3 counts the devia�on between command pulse signals and EA / EB signals. Set the maximum devia�on tolerance (absolute value) in the comparison value in a comparator that is compared with counter 3 to detect out-of-step.
Page 233 TA600137-EN0/0 Name and descrip�on Target <Comparator 2 comparison target> RENV4.C2C(9,8) 10b: RCUN3 (RCUN3) If RENV4.C2C = 10b, compare with the absolute value of RCUN3 register (0 to 32,767). <Comparator 3 comparison target> RENV4.C3C(17,16) 10b: RCUN3 (RCUN3) If RENV4.C3C = 10b, compare with the absolute value of RCUN3 register (0 to 32,767). <Comparator 4 comparison target>...
Page 234 TA600137-EN0/0 Name and descrip�on Target <Processing when the condi�on of Comparator 4 is met> RENV4.C4D(31,30) 00b: No ac�on. It can be used to output INT signals and CP4 signals, and internal synchroniza�on start. 01b: Immediate stop. 10b: Decelera�on stop. 11b: Bulk override. <Processing when the condi�on of Comparator 5 is met>...
Page 235 TA600137-EN0/0 Name and descrip�on Target <Main status (SCP2)> MSTS.SCP2(9) 0: The comparison condi�on of comparator 2 is not met. 1: The comparison condi�on of comparator 2 is met. <Main status (SCP3)> MSTS.SCP3(10) 0: The comparison condi�on of comparator 3 is not met. 1: The comparison condi�on of comparator 3 is met.
Page 236 TA600137-EN0/0 6.13.4 Index output Comparator 4 (RCMP4) can be used to periodically output the index (IDX) signal from CP4n pin. Set the comparison target of comparator 4 (RENV4.C4C) to 11b of counter 4 (RCUN4). Then, select the comparison condi�on for comparator 4 (RENV4.C4S) from IDX signal output (IDX) 1000b, 1001b, and 1010b. The count range of RCUN4 register will be from 0 to the RCMP4 register.
Page 237 TA600137-EN0/0 Pulse output se�ng example: CP4n pin outputs IDX signal at nega�ve logic. Counter 4 counts the command pulses from 0 to 4. When changing to RCUN4 = 0, IDX signal with 2-cycle width of the CLK signal is output. Se�ng value: RENV2 = 00002000h, RENV3 = 00000000h, RENV4 = 23800000h, RCMP4 = 4.
Page 238 TA600137-EN0/0 6.13.5 Ring count The ring count func�on can be used with the ring counters used in a rotary encoder. The ring counter is an up/down counter that operates in a ring opera�on from 0 to the set maximum value. When coun�ng up from the maximum value, the ring counter jumps to 0.
Page 239 TA600137-EN0/0 Name and descrip�on Target <Comparator 2 comparison condi�on> RENV4.C2S(12: 10) 000: The comparison condi�on is always not met. <When the condi�on of comparator 2 is met> RENV4.C2D(14,13) 00b: No ac�on. It can be used to output INT signals and CP2 signals, and for internal synchroniza�on start <Counter 2 ring count>...
Page 240 TA600137-EN0/0 6.13.6 Bulk override The data in the pre-register for con�nuous opera�on, which is determined by PRSET (4Fh) command is called the overriding data. The overriding data should be writen from the 2nd pre-register at least when the current register is determined. The writen undetermined data will be determined as overriding data when wri�ng PRSET (4Fh) command.
Page 241 TA600137-EN0/0 6.13.6.1 Bulk override example 1 This is an example of using the overriding data in determined status with PRESHF (2Bh) command, and then star�ng the next con�nuous opera�on. Determine the data 1 for ini�al opera�on, the data 1' for speed change, and the data 2 for con�nuous opera�on, then start.
Page 242 TA600137-EN0/0 6.13.6.2 Bulk override example 2 This is an example in which the next con�nuous opera�on starts without using determined overriding data. Determines the Data 1 for the ini�al opera�on, the Data 1' for overriding, and the Data 2 for the con�nuous opera�on, and start.
Page 243 TA600137-EN0/0 6.13.6.3 Bulk override example 3 This is an example in which the opera�on mode will be completed without using determined overriding data. Determines the Data 1 for the ini�al opera�on, the Data 1' for the override 1, and the Data 1" for the override 2, and start. If the opera�on mode of the current register is completed before the comparator condi�on is met, the pre-register is also shi�ed.
Page 244 TA600137-EN0/0 6.13.6.4 Pre-register for con�nuous comparison use example This is an example in which you use the determined overriding data with the comparator, and then start the next con�nuous opera�on. Determine the Data 1 for the ini�al opera�on, the Data 1' for the override 1, and the Data 1" for the override 2, and start the opera�on.
Page 245 TA600137-EN0/0 RSTS. RSTS. Procedures 2nd pre-register 1st pre-register Current register Opera�on will stop at RCUN1 = 1000 Data 1" Data 1" Data 1" (RPLS = 0). (Undetermined) (Undetermined) (Undetermined) Comparison B Comparison B Comparison B (Undetermined) (Undetermined) (Undetermined) - 240 -...
Page 246 TA600137-EN0/0 Backlash correc�on For actuators that use gears or chains, there is a func�on to compensate backlashes in reversal mo�ons. If RENV6.ADJ = 01b is set, the number of pulses set in RENV6.BR bit is output at FA speed, and then the opera�on starts. Backlash correc�on is performed at each start when the direc�on of movement changes.
Page 247 TA600137-EN0/0 Slip correc�on For actuators that use pulleys or belts, there is a func�on to correct slip at the start. If RENV6.ADJ = 10b is set, the number of pulses set in RENV6.BR bits is output at FA speed and then the opera�on starts. Slip correc�on is performed at every �me start, regardless of changes in the direc�on of movement.
Page 248 TA600137-EN0/0 Vibra�on suppression You can use this func�on in all posi�oning opera�on modes other than the Timer. Immediately a�er the opera�on mode is completed, PCL6045BL outputs one pulse reverse rota�on and one pulse forward rota�on to suppress vibra�on. The vibra�on suppression pulse can be output at the �ming to suppress the vibra�on generated by the ﬁnal pulse, which can reduce the setling �me.
Page 249 TA600137-EN0/0 Synchronous start At the start �ming a�er wri�ng the start command, you can start an opera�on in synchroniza�on with the stop of speciﬁed axis. You can also start with the output of an internal sync signal. 6.17.1 Start when the speciﬁed axis stops The start �ming can be set by (RMD.MSY = 11b) when the speciﬁed axis (RMD.MAX) stops.
Page 250 TA600137-EN0/0 Name and descrip�on Target <Start �ming a�er wri�ng the start command> RMD.MSY(19,18) 11b: Starts when the speciﬁed axis (RMD.MAX) stops. <Axis to conﬁrm stop when RMD.MSY = 11b> RMD.MAX(23:20) Example: 0001b: Starts when X-axis stops. 0010b: Starts when Y-axis stops. 0100b: Starts when Z-axis stops.
Page 251 TA600137-EN0/0 If linear interpola�on 2 stops before the circular interpola�on stops, linear interpola�on 1 (RMD.MOD = 61h) cannot start. Linear BSYxy Circular interpolation interpolation 1 Linear BSYzu interpolation 2 Opera�on example 1-2(RENV2.SMAX = 0)： Set the X-axis opera�ng �me > Y-axis opera�ng �me, and set 1 to 4 below. 1.
Page 252 TA600137-EN0/0 When linear interpola�on 2 stops a�er the circular interpola�on stops, linear interpola�on 1 (RMD.MOD = 61h) will start. This is the same as the func�on that does not start if the own axis stops at the end (RENV2.SMAX = 0). Circular Linear BSYxy...
Page 253 TA600137-EN0/0 6.17.1.2 Con�nuous interpola�on without changing the interpola�on opera�on axes In the con�nuous interpola�on that does not change the combina�on of interpola�on opera�on axes, it is not necessary to set the start by stopping the speciﬁed axis. Since all axes stop at the same �me, con�nuous interpola�on can be performed simply by se�ng the con�nuous opera�on in the pre-register.
Page 254 TA600137-EN0/0 (RENV2.SMAX = 0 and speed control register se�ngs are omited) STEP Wri�ng target X-axis value Y-axis value Z axis value Descrip�on X-axis and Y-axis have the target PRMV 10000 10000 coordinates:10000,10000 (90-degree). Z axis: 0 feed amount PRIP 10000 - Center coordinates: 10000, 0.
Page 255 TA600137-EN0/0 6.17.1.4 Con�nuous interpola�on 2 to change the interpola�on opera�on axes In the con�nuous interpola�on that changes the combina�on of interpola�on opera�on axes, it is necessary to set the dummy opera�on data and the start by stopping speciﬁed axis. The dummy opera�on is an incremental movement of the posi�oning control that sets RMV = 0.
Page 256 TA600137-EN0/0 STEP1’s all axes are completed to start the linear interpola�on 1 (10000, 5000) of STEP2 and the dummy opera�on of Z axis. STEP2 dummy opera�on will stop immediately. STEP3 is set while STEP1 or STEP2 is opera�ng to wait the comple�on of all axes of STEP2. STEP2’s all axes are completed to start the linear interpola�on 1 (10000, −5000) of STEP3 and the dummy opera�on of Y- axis.
Page 257 TA600137-EN0/0 6.17.2 Start with internal sync signal When RMD.MSY = 10b is set, RSTS.CND = 0011b will be set a�er wri�ng the start command. The opera�on starts when the axes that are set in RENV5.SYI bit outputs an internal synchroniza�on signal. The output �ming of an internal synchroniza�on signal can be selected from nine types of signals with RENV5.SYO bit.
Page 258 TA600137-EN0/0 OUTy RCUN1y 1000 1001 1002 1003 1004 1997 1998 1999 2000 CP1y OUTx RCUN1x 1000 In this example, se�ng PRMVy = 2000 and PRMVx = 1000 results in RCUN1x = 1 at RCUN1y = 1000. Therefore, when RCUN1Y = 1999, it will be RCUN1x = 1000, and X-axis stops 1 pulse short of the Y-axis. When se�ng RCUN1x = 1000 with RCUN1y = 2000, set “the comparison target size is larger (RENV4y.C1S = 11b)”.
Page 259 TA600137-EN0/0 Name and descrip�on Target ＜Output �ming of internal synchronous signal＞ RENV5.SYO(19:16) 0001b: When comparator 1 condi�on is met 0010b: When comparator 2 condi�on is met 0011b: When comparator 3 condi�on is met 0100b: When comparator 4 condi�on is met 0101b: When comparator 5 condi�on is met 1000b: When the accelera�on starts 1001b: When the accelera�on ends...
Page 260 TA600137-EN0/0 Name and descrip�on Target <Event interrupt factor (ISUE)> RIST.ISUE(5) 1: The accelera�on has ended. (SSTS.SFU bit changed from 1 to 0) <Event interrupt factor (ISDS)> RIST.ISDS(6) 1: Decelera�on has started. (SSTS.SFD bit changed from 0 to 1) <Event interrupt factor (ISDE)> RIST.ISDE(7) 1: The decelera�on has ended.
Page 261 TA600137-EN0/0 6.17.3 Con�nuous interpola�on using circular interpola�on dummy opera�on In case of con�nuous interpola�on that changes the combina�on of interpola�on opera�on axes, the opera�on mode of circular interpola�on dummy (RMD.MOD = 6Fh) can be used. The circular interpola�on dummy is an opera�on mode for con�nuous interpola�on with circular interpola�on control without se�ng the RENV2 register or RMD.MAX bit.
Page 262 TA600137-EN0/0 Interrupt request (INT) From INT pin, INT signals that perform interrupt requests can be output. INT signal con�nues to be output un�l all the causes in all the axes that are interrup�ng are cleared. There are 17 types of errors, 20 types of events, and 1 type of opera�on stop as the interrupt factors for each axis. You can iden�fy the interrupt genera�on axis and interrupt cause by the following procedures.
Page 263 TA600137-EN0/0 6.18.1 Error interrupt The error interrupt factor occurs when only one condi�on is met. When an error interrupt factor occurs, the corresponding bit in REST register becomes 1. When any bit of REST register is 1, the L level can be output from INT pin. In REST register, wri�ng 1 to the corresponding bit can clear the bit to 0.
Page 264 TA600137-EN0/0 6.18.2 Event interrupt The event interrupt factor occurs when the condi�on of RIRQ register is met. When an event interrupt factor occurs, the corresponding bit in RIST register becomes 1. When any bit of RIST register is 1, it becomes MSTS.SINT = 1, so L level can be output from INT pin. In RIST register, wri�ng 1 to the corresponding bit clears the bit to 0.
Page 265 TA600137-EN0/0 6.18.3 Opera�on stop interrupt The opera�on stop interrupt factor occurs when an opera�on is stopped by RENV2.IEND = 1 se�ng. When an interrupt factor occurs, MSTS.SENI bit becomes 1. When MSTS.SENI bit is 1, L level can be output from INT pin. MSTS.SENI bit will be cleared to 0 when you write SENIR (2Dh) command.
Page 266 TA600137-EN0/0 General-purpose one shot General-purpose one-shot signals can be output from the P0 and P1 pins using a general-purpose output bit control command. The output pulse width of the general-purpose one-shot signal is 23 to 25 ms. P0n pin can output a general-purpose one-shot signal by se�ng RENV2.P0M = 11b. When RENV2.P0L = 0 is set, a general-purpose one-shot signal with nega�ve logic is output with P0RST (10h) command.
Page 267 TA600137-EN0/0 7. Electrical Characteris�cs Absolute maximum ra�ngs Item Symbol Ra�ng Unit Remarks Power supply voltage −0.3 to +4.0 Input voltage −0.3 to +7.0 Output voltage −0.3 to +7.0 Output current ±30 Storage temperature −65 to +150 °C C a u t i o n Regarding the output voltage ra�ng, if a voltage higher than the power supply voltage is applied, a large current may ﬂow.
Page 268 TA600137-EN0/0 DC characteris�cs Item Symbol Condi�ons Min. Max. Unit CLK = 20 MHz, 4 axes 6.667 Mpps，No Current consump�on load Output leakage current ＝ 3.6 V，V ＝ 0 V −1 μA Output leakage current −1 μA ＝ 3.6 V，V ＝ 0 V High level input voltage = 3.6 V Low level input voltage...
Page 269 TA600137-EN0/0 AC characteris�cs 7.4.1 Reference clock Item Symbol Condi�ons Min. Max. Unit Frequency (Recommended frequency 19.6608 MHz) Cycle H level width L level width - 264 -...
Page 270 TA600137-EN0/0 7.4.2 CPU IF = 0 (68000) If IF1 = L level and IF0 = L level are set, the interface will be for 68000 series CPUs. ＜Write cycle＞ A4 ~ A1 LS(A0) R/W(WR) SLAKW SHAKW ACK(WRQ) AKDH D15 ~ D0 ＜Read cycle＞...
Page 271 TA600137-EN0/0 Item Symbol Condi�ons Min. Max. Unit Address setup �me LS↓ Address hold �me LS↑ CS setup �me LS↓ CS hold �me LS↑ R/W setup �me LS↓ R/W hold �me LS↑ = 40pF 1⋅T 5⋅T SLAKR ACK ON delay �me LS↓...
Page 272 TA600137-EN0/0 7.4.3 CPU IF = 1 (H8) If IF1 = L level and IF0 = H level are set, the interface will be for H8 CPUs. ＜Write cycle＞ A4 ~ A1 RWCS CSWT WAIT D15 ~ D0 ＜Read cycle＞ A4 ~ A1 RWCS CSWT WAIT...
Page 273 TA600137-EN0/0 Item Symbol Condi�ons Min. Max. Unit Address setup �me RD↓ Address setup �me WR↓ Address hold �me RD↑，WR↑ CS setup �me RD↓ CS setup �me WR↓ CS hold �me RD↑，WR↑ RWCS WRQ ON �me CS↓ ＝40pF CSWT WRQ L level �me 4⋅T WAIT Data output delay �me...
Page 274 TA600137-EN0/0 7.4.4 CPU IF = 2 (8086) If IF1 = H level and IF0 = L level are set, the interface will be for 8086 CPUs. ＜Write cycle＞ A4 ~ A1 RWCS CSWT WAIT D15 ~ D0 ＜Read cycle＞ A4 ~ A1 RWCS CSWT WAIT...
Page 275 TA600137-EN0/0 Item Symbol Condi�ons Min. Max. Unit Address setup �me RD↓ Address setup �me WR↓ Address hold �me RD↑，WR↑ CS setup �me RD↓ CS setup �me WR↓ CS hold �me RD↑，WR↑ RWCS WRQ ON �me CS↓ ＝40pF CSWT WRQ L level �me 4⋅T WAIT Data output delay �me...
Page 276 TA600137-EN0/0 7.4.5 CPU IF = 3 (Z80) If IF1 = H level and IF0 = H level are set, the interface will be for Z80 CPUs. ＜Write cycle＞ A4 ~ A0 RWCS CSWT WAIT D7 ~ D0 ＜Read cycle＞ A4 ~ A0 RWCS CSWT WAIT...
Page 277 TA600137-EN0/0 Item Symbol Condi�ons Min. Max. Unit Address setup �me RD↓ Address setup �me WR↓ Address hold �me RD↑，WR↑ CS setup �me RD↓ CS setup �me WR↓ CS hold �me RD↑，WR↑ RWCS WRQ ON �me CS↓ ＝40pF CSWT WRQ L level �me 4⋅T WAIT Data output delay �me...
Page 278 TA600137-EN0/0 Opera�on �ming Input signals completely ignore the below the Minimum �me and reacts reliably above the Standard �me. Output signals reliably output more than the Minimum �me and stops completely within the Standard �me. The delay �me is not completed if it is less than the Minimum �me, and it is completed if more than the Standard �me. Item Symbol Condi�on...
Page 279 TA600137-EN0/0 7.5.1 RST signal RSTD reset 7.5.2 SRST command Write Cycle SRST ライトサイクル完了 SRSTD reset 7.5.3 EA, EB signals 7.5.3.1 2-pulse mode (encoder) 7.5.3.2 90-degree phase diﬀerence mode (encoder) - 274 -...
Page 280 TA600137-EN0/0 7.5.4 PA, PB signals 7.5.4.1 2-pulse mode (manual pulser) 7.5.4.2 90-degree phase diﬀerence mode (manual pulser) 7.5.5 Start command Write Cycle STAxx ライトサイクル完了 CMDBSY CMDPLS First pulse 7.5.6 CSTA signal CSTA STABSY STAPLS First pulse - 275 -...
Page 281 TA600137-EN0/0 Revision history Revision Date Content Sep 16, 2009 - New document - P38: The following comments are added in “8-2-3.Wri�ng to the comparator pre-registers”: Apr 16, 2018 “However, when the comparison status between RCMP5 and the comparison target is “true”, you must be careful when wri�ng data to PRCP5.
Page 282 TA600137-EN0/0 Revision Date Content - P117: Revision in “Apply an input ﬁlter to EZ”. In correct [RENV2] (WRITE) Correct [RENV2] (WRITE) 134: 4 new charts are added in “[Speed change using the comparator]”. One whole page increases by this addi�on. Apr 16, 2018 -P30: The following phrase is added in “Direct access method”;...
Page 283 TA600137-EN0/0 Revision Date Content -P15: 3) 8086 I/F (Memory map, full address) Changed “Decode circuit” to “Interrupt control circuit”. -P15: 4) 8086 I/F (I/O map, reduced address) Added CPU brand (8086CPU) and PCL model (PCL6045BL) in the diagram. -P16: 5) H8 I/F (full address) Removed the arrow(→) beside the “Decode circuit”.
Page 284 TA600137-EN0/0 Revision Date Content P85: 9-5-1-11. Origin return opera�on 10 (RENV3.ORM = 1010) Revised “High speed opera�on <Sensor: EL, ORG, EZ (RENV3.EZD = 0001)>” chart. P85: 9-5-1-12. Origin return opera�on 11 (RENV3.ORM = 1011) Revised “High speed opera�on <Sensor: EL, ORG, EZ (RENV3.EZD = 0001)>” chart. P104: 10-3.
Page 285 TA600137-EN0/0 Revision Date Content from “11” to “10”. P157: Revised chapter name: CPU-I/F 3) (IF1 = L, IF0 =L) H8 CPU-I/F 3) (IF1 = L, IF0 = H) H8 P157: <Write cycle> Added under “TDWR”. P160: Revised the �tle to “5) Timing for the command start (IF1=H and IF0=H)” from “5) Timing for the command start (IF1=H and IF0=H)”.
Page 286 TA600137-EN0/0 Revision Date Content 6-5-4. Reading the main status Changed “set to” to “becomes” 6-5-5. Reading the sub status and input/output port Changed “set to” to “becomes” July 31, 2018 8-3-40. PRCI (RCI) register Changed “the U axis is not available for circular interpola�on control” to “the U-axis cannot be a master axis for circular interpola�on control”...
Page 287 TA600137-EN0/0 Revision Date Content July 31, 2018 11-5-2. Enable/disable SD signal input Corrected “RMD” to “PRMD”. 11-5-3. Apply an input ﬁlter to EZ Corrected “<Set FLTR (bit 18) in RENV1>” to“<FINF (bit 18) in RENV2>”. 11-6. Changed to “(CND0 to 3, opera�on status)” to “(CND3 to 0 in RSTS, opera�on status)”. 11-11-1.
Page 288 TA600137-EN0/0 Revision Date Content The ERC signal is a pulsed output. The pulse length can be set. Incorrect: (12 μs to 104 ms. A level output is also available. Correct: (11 µs to 100 ms. Level outputs are available) ∴ In this manual, see "2.1 Features". 4.
Page 289 TA600137-EN0/0 Revision Date Content "Descrip�on" column of "14 to 12|EPW2 to 0". Incorrect: 000: 12 μs 001: 102 μs 010: 409 μs 011:1.6 ms 100 :13 ms 101 :52 ms 110 :104 ms 111: Level output Correct : 000b: 11 to 13 μs 001b: 91 to 98 μs 010b: 360 to 390 μs 011b: 1.4 to 1.6 ms 100b: 11 to 13 ms...
Page 290 TA600137-EN0/0 Revision Date Content Correct : Sets the processing when wri�ng a stop command in pulser control. 0: Stops by ignoring the PA and PB signals that have been input. 1: Outputs the command pulse corresponding to the PA and PB signals that have been input, and then stops.
Page 291 TA600137-EN0/0 Revision Date Content Set RENV6.PSTP=1 to delay the opera�on un�l the total output pulse becomes an integral mul�ple of the mul�plica�on value. However, for interpola�ng control (68h,69h,6Ah,6Bh,6Ch,6Dh), it will be stopped ignoring RENV6.PSTP=1. ∴ In this manual, see "5.5.3 Pulser control". 9-4-1.
Page 292 TA600137-EN0/0 Revision Date Content ∴ In this manual, see " ". 5.5.8 Linear interpola�on 2 control 10-1. Speed paterns In the note of "High speed opera�on 1)| Posi�oning mode". When posi�oning with a high speed start command 1 (52h), the ramping-down point is ﬁxed to the manual se�ng, regardless of the se�ng for MSDP (bit 13) in the PRMD.
Page 293 TA600137-EN0/0 Revision Date Content 11-14-1. Start triggered by another axis stopping [Example 2] Incorrect: X and Y axis perform a linear interpola�on 1 PRMV 10000 5000 with an endpoint (1000, 5000) Correct : X and Y axis perform a linear interpola�on 1 PRMV 10000 5000...
Page 294 TA600137-EN0/0 Revision Date Content CLR input signal width Incorrect: CLR input-signal-width | | |2T | |ns Correct: CLR input signal width| | |1T | |ns ∴ In this manual, see "7.5 Opera�on �ming". ALM, INP, +EL, -EL, SD, ORG input signal width Incorrect: ALM, INP, +EL, -EL, SD, ORG input signal width | | |2T | |ns Correct: ALM, INP, +EL, -EL, SD, ORG input signal width| | |1T...
Page 295 TA600137-EN0/0 Revision Date Content 10 seconds. within 10 seconds of �me exceeding 255°C [A proﬁle] 255°C or more within 10 seconds 220°C or higher within 60 seconds ∴ In this manual, see "1.2.3.4 Precau�ons for installa�on". - 290 -...
Page 296 TA600137-EN0/0 www.pulsemotor.com/global Informa�on www.pulsemotor.com/global/contact Fi�h edi�on issued in December, 2023 Copyright 2009 Nippon Pulse Motor Co., Ltd.

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