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molex BittWare XUP-VV4 Hardware Reference Manual

Xilinx ultrascale+ 3/4-length pcie board
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XUP-VV4
Xilinx UltraScale+ 3/4-Length PCIe Board
Hardware Reference Guide

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Summary of Contents for molex BittWare XUP-VV4

  • Page 1 XUP-VV4 Xilinx UltraScale+ 3/4-Length PCIe Board Hardware Reference Guide...
  • Page 2 +1 (603) 226 0404 Intellectual Property Copyright © 2021, BittWare, a Molex company All rights reserved. All names, images and logos identifying BittWare or third parties and their products and ser- vices are subject to copyright, design rights and trademarks of BittWare and/or third parties. Nothing contained in these terms shall be construed as conferring by implication, estoppel or otherwise any license or right to use any trademark, patent, design right or copyright of BittWare, or any other third party.
  • Page 3 (2) this device must accept any interference received, including interference that may cause undesired operation CAN ICES-3(A)/NMB-3(A) If further information is needed regarding REACH or conflicting minerals, please contact the Molex Compliance Group. CHAPTER 1 │ XUP-VV4 Hardware Reference Guide...
  • Page 4 CONTENTS 1 Introduction 1.1 About this Hardware Reference Guide 1.1.1 Document History 1.1.2 Additional Resources 1.2 Handling, Shipping, and Warranty 1.2.1 Handling the XUP-VV4 1.2.2 Warranty 1.2.3 RMA - Returning Your Product to BittWare 1.3 Contact BittWare 2 Board Overview 2.1 Board Architecture 2.1.1 Block Diagram 2.1.2 XUP-VV4 Features 2.2 Components and Interfaces...
  • Page 5 3.2 FPGA Implementation Details 3.2.1 FPGA Bank Usage and Clocks 3.2.2 PCIe Connections 3.2.3 Transceiver Connections 3.2.4 I2C Interface 3.2.5 Step Load Requirements 4 PCIe Interface 4.1 PCIe Pinout 4.2 PCIe Signal Details 4.3 Tandem Support 5 External Interfaces 5.1 Validated Cables and Transceiver Settings 5.2 QSFP28 5.2.1 FPGA Transceivers 5.2.2 Connector Mapping to Endplate...
  • Page 6 6.1.2 DIMM Support 6.2 Flash Memory 7 Clock Circuitry 7.1 Clock Configurations 7.2 Timestamp and Synchronization 7.3 System Clocks 7.3.1 Clock Descriptions 7.3.2 Clock Circuitry 8 Configuration, Status, and Setup 8.1 FPGA Configuration 8.1.1 Power-Up Reset 8.1.2 Configuration via USB and JTAG 8.1.3 Boot Image Location 8.1.4 Boot Image Management 8.2 Status and Setup Elements...
  • Page 7 10.1 Chassis Requirements 10.1.1 PCIe Express 10.1.2 PCIe Bracket 10.2 Air Flow 10.3 Board Dimensions...
  • Page 8 1 Introduction BittWare’s XUP-VV4 is an UltraScale+ VU13P FPGA-based PCIe card, ideal for high-density datacenter applications. The Xilinx UltraScale+ VU13P FPGA gives designers incredible performance potential, with 3.8M logic elements — yet with a power density that makes thermal management difficult. The XUP-VV4 meets this challenge with BittWare’s Viper platform, supporting large FPGA loads, up to 512 GBytes DDR4, and 4x 100 Gbps Ethernet.
  • Page 9 1.1 About this Hardware Reference Guide This guide covers Rev. 0 of the XUP-VV4 board and describes the XUP-VV4’s components and interfaces. For instructions on installing and setting up USB or PCIe access to the XUP-VV4, refer to the XUP-VV4 Quick Start Guide.
  • Page 10 1.2 Handling, Shipping, and Warranty 1.2.1 Handling the XUP-VV4 The XUP-VV4 contains electro-static discharge (ESD) sensitive devices. Be sure to follow the standard handling procedures for ESD sensitive devices, taking proper precautions to ground yourself and the work area before removing the board from its static shielding bag.
  • Page 11 RMA resolution time varies depending on the issue and the amount of investigation, retest, and rework required. The lead time for replacement parts and the availability of our rework factory also impacts the RMA resolution time. We can estimate the RMA resolution time when we receive the RMA board at our factory. Contacting BittWare for instructions on how to contact BittWare Support to request an RMA.
  • Page 12 1.3 Contact BittWare BittWare is dedicated to providing customers with superior technical support: BittWare Developer Site: The BittWare Developer Site provides online access to our technical support resources. Go to developer.bittware.com to register for an account. Once you've set up an account, you will have access to BITTS (the BittWare Issue Tracking and Technical Support site), BittWare product doc- umentation, software downloads, release notes, and examples.
  • Page 13 2 Board Overview This chapter gives an overview of the XUP-VV4 board and discusses the board’s architecture and its components. It covers the following topics: Board architecture, including block diagram and feature list Components and interfaces Firmware Board configuration options © BittWare, 2021...
  • Page 14 2.1 Board Architecture The XUP-VV4 is based on the Xilinx UltraScale+ FPGA, which handles all of the board's I/O. The I/O interfaces on the board include the following: 16-lane mechanical and electrical PCIe 3.0 host interface 4 QSFP28 cages 2 UltraPort SlimSAS USB interface for BMC and Vivado JTAG Utility interface with 1 PPS, USB UART, and GbE Also connected directly to the FPGA are four DIMM sites, each supporting a DDR4 SDRAM or QDR-II+ DIMM mod-...
  • Page 15 Integrated PCIe hard IP Up to 11,904 DSP slices with 27x18 multipliers Four optional DIMM sites, each with support for: Up to 128 GBytes DDR4 x72 with ECC Up to 576 Mbits dual QDR-II+ x18 (2 independent 288 Mbit banks) Up to 2 Gbit (256 MB) Flash x16 Gen1, Gen2, Gen3 interface direct to FPGA I/O interfaces...
  • Page 16 Board Layout (Bottom View) Front Panel...
  • Page 17 Xilinx Ultrascale+ FPGA Connectors QSFP+ connectors TE Connectivity 1551920-2 QSFP28 Micro USB interface TE Connectivity 2013499-1 USB C interface Mill Max Manufacturing 898-43-024-00-310002 Utility SlimSAS Amphenol U10A074200T SlimSAS External power Molex 45586-0005 Power DIMM connectors Molex 78730-1002 Memory CHAPTER 2 │ XUP-VV4 Hardware Reference Guide...
  • Page 18 Component Manufacturer Part Number Section Reference Clocks 48 MHz crystal Kyocera CX3225SB48000D0FPJC1 Clock Circuitry Clock generators (programmable) Silicon Laboratories Si5341A-D-GM Clock Circuitry SiT9365AI-2B2- 322.265625 MHz Clock SiTime Clock Circuitry 33E322.265625 Memory Flash, 2Gbit Micron Technology MT25QU02GCBB8E12-0SIT Memory EEPROM MAC PROM Microchip Technology AT24CS04-MAHM-T Firmware 2.3 Firmware...
  • Page 19 BittWare supports a variety of leading server vendors. As part of Molex, we can handle global supply chain and logistics. We can cater to a range of application environments such as data center and at the edge. Lastly, through OEM programs, you have the option of purchasing selected TeraBox servers directly from server vendors such as Dell, HPE, and Lenovo.
  • Page 20 3 Xilinx Ultrascale+ FPGA The FPGA on the XUP-VV4 handles all of the board's I/O. This section covers the following: Component overview FPGA implementation details © BittWare, 2021...
  • Page 21 3.1 Component Overview The XUP-VV4 features a Xilinx Virtex UltraScale+ VU13P FPGA. 3.1.1 Supported Devices The XUP-VV4 supports the following UltraScale+ devices: Table 3 Supported Virtex UltraScale+ Devices Family Part Number Virtex XCVU9P Virtex XCVU13P (default option) 3.2 FPGA Implementation Details 3.2.1 FPGA Bank Usage and Clocks Bank Usage FPGA bank usage...
  • Page 22 FPGA bank usage CHAPTER 3 │ XUP-VV4 Hardware Reference Guide...
  • Page 23 FPGA annotated DIE view Clock Connections Clock Connections (VU13P FPGA) illustrates the board's clock connections. The QSFP reference clocks can be used to support 400G/100G/25G/10G Ethernet. The 16 front panel lanes can use up to 12 different frequencies.
  • Page 24 Clock Connections (VU13P FPGA) CHAPTER 3 │ XUP-VV4 Hardware Reference Guide...
  • Page 25 3.2.2 PCIe Connections The following table describes the connections from the PCIe Hard IP blocks in the FPGA to the board's PCIe inter- faces. Hard Bank(s) RefClk(s) Connection X0Y1 225-224 PCIe fingers 8-15 X0Y1 227-226 PCI fingers 0-7 3.2.3 Transceiver Connections The UltraScale+ FPGAs have 50 multi-gigabit transceivers supporting 32.75 Gb/s .
  • Page 26 Transceivers Clocks Group Name Connection Ref Clock Connection Notes / Default GTY_CH3_129 SlimSAS1 3 GTY_CH0_133 SlimSAS1 4 GTREFCLK0 Clk_A4B GTY-133 GTY_CH1_133 SlimSAS1 5 GTREFCLK1 SlimSAS1 Clk1 GTY_CH2_133 SlimSAS1 6 GTY_CH3_133 SlimSAS1 7 Table 5 PCIe and QSFP Transceiver Connections Transceivers Clocks Group Name...
  • Page 27 Transceivers Clocks Group Name Connection Ref Clock Connection Notes / Default GTY_CH0_229 QSFP3-1 GTREFCLK0 Si5341A_2 322.265625 MHz GTY_CH1_229 QSFP3-2 GTREFCLK1 Si5341B_8 322.265625 MHz GTY-229 GTY_CH2_229 QSFP3-3 GTY_CH3_229 QSFP3-4 GTY_CH0_230 USB C Tx1 GTREFCLK0 Si5341A_8 322.265625 MHz GTY_CH1_230 USB C Rx1 GTREFCLK1 Unused GTY-230...
  • Page 28 Note: If you plan to use this signal, please review the knowledge base article "Mastering I2C Devices on the FPGA" on the BittWare developer site to make sure you don't run into a bus conflict. 3.2.5 Step Load Requirements Warning! Be sure the XUP-VV4 does not go from high power to no power all at once as it may cause a voltage spike on the FPGA core supply that could damage the FPGA.
  • Page 29 4 PCIe Interface The XUP-VV4 features a PCI x16 mechanical interface, which supports a PCIe Gen1, Gen2, and Gen3 connection in a standard slot. The PCIe interface connects to the FPGA via 16 transceivers. © BittWare, 2021...
  • Page 30 4.1 PCIe Pinout Table 8 PCIe Connector Pinout Side B Side A Pin # PCIe Signal XUP-VV4 Usage PCIe Signal XUP-VV4 Usage +12V P12V_PCIE_BP PRSNT1_N PCIE_PRSNT_L +12V P12V_PCIE_BP +12V P12V_PCIE_BP +12V P12V_PCIE_BP +12V P12V_PCIE_BP SMCLK PCIE_SMBCLK JTAG_TCK SMDAT PCIE_SMBDAT JTAG_TDI JTAG_TDO +3_3V-1 P3V3_PCIE JTAG_TMS...
  • Page 31 Side B Side A Pin # PCIe Signal XUP-VV4 Usage PCIe Signal XUP-VV4 Usage PER2N PCIE_TX_N_2 PET3P PCIE_RX_P_3 PET3N PCIE_RX_N_3 PER3P PCIE_TX_P_3 RSVD3 PER3N PCIE_TX_N_3 PRSNT2_N_X4 PCIE_PRSNT_X4_L RSVD4 x8 lanes PET4P PCIE_RX_P_4 RSVD5 PET4N PCIE_RX_N_4 PER4P PCIE_TX_P_4 PER4N PCIE_TX_N_4 PET5P PCIE_RX_P_5 PET5N PCIE_RX_N_5 PER5P...
  • Page 32 Side B Side A Pin # PCIe Signal XUP-VV4 Usage PCIe Signal XUP-VV4 Usage PET9N PCIE_RX_N_9 PER9P PCIE_TX_P_9 PER9N PCIE_TX_N_9 PET10P PCIE_RX_P_10 PET10N PCIE_RX_N_10 PER10P PCIE_TX_P_10 PER10N PCIE_TX_N_10 PET11P PCIE_RX_P_11 PET11N PCIE_RX_N_11 PER11P PCIE_TX_P_11 PER11N PCIE_TX_N_11 PET12P PCIE_RX_P_12 PET12N PCIE_RX_N_12 PER12P PCIE_TX_P_12 PER12N PCIE_TX_N_12...
  • Page 33 Clock and Reset PCIe reset is connected to the FPGA through a voltage translator from the edge fingers. The PCIe RefClk is con- nected through a mux to the FPGA to support standalone or systems where a 100 MHz RefClk is not available, such as some expansion chassis.
  • Page 34 5 External Interfaces The XUP-VV4 supports the following interfaces for high-speed serial I/O as well as debug support: Table 9 XUP-VV4 I/O Interfaces Ref. Des. Connector Type Description J1, J2, J9, J13 288-pin DIMM: supports DDR4 or QDRII+ DIMMs 8-pin (2x4) Power: external power connector J4, J6, J8, J12 38-pin SMD...
  • Page 35 XCVR Mfg. Part Rate Description Tx Settings Mfg. Type Settings Pre-Cursor=2.50db 3m Active Optical QSFP 25Gbps Post-Cursor=0.00dB 5.520E-16 Molex 183710-0004 Cable Enabled Diff Swing=933mV Table 12 SlimSAS Cables XCVR Mfg. Part Rate Description Tx Settings Mfg. Type Settings 1.53m 8x to 8x SlimSAS Pre-Cursor=0.00db...
  • Page 36 Table 13 USB Cables XCVR Rx Set- Rate Description Tx Settings Mfg. Mfg. Part No. Type tings Pre-Cursor=0.00dB 1m USB-C to USB-C USB-C 10Gbps Post-Cursor=0.00dB DFE Enabled 6.162E-16 Belkin F2CU030BT1M-BLK Cable Diff Swing=846mV 5.2 QSFP28 The XUP-VV4 has four QSFP28 cages on the front panel (see Board Layout (Top View) Front Panel for loc-...
  • Page 37 5.2.3 QSFP GPIO Connections 5.2.4 QSFP+ Control Signals All QSFP+ control signals are connected to the FPGA via a translator. I2C signals also connect to the BMC; the FPGA needs to assert the FPGA_MASTER_I2C_L signal (drive it to 0) to prevent collisions. Connector Pin FPGA Signal...
  • Page 38 Connector Pin FPGA Signal Default Description Number C clock line, connected to the FPGA via an I expander. If not used, configure as unused input, I2C_SCL_[7:4] Unused Input Pin 12 so the BMC can have control. I2C_SDA_[7:4] cor- responds to QSFP[4:1]. If used as I C, it will be output.
  • Page 39 5.3.2 SlimSAS Connector and Cable Pinout Note: The diagram shows that the cable swaps Axx and Bxx.
  • Page 40 5.3.3 GPIO Connections Table 14 SlimSAS GPIO Signal Details PIO Signal Name FPGA Pin FPGA Bank External Voltage Level FPGA Dir SlimSAS Pin SAS1_GPRX_0 AN22 Bank 64 3.3V Input J5-B11 SAS1_GPRX_1 AN21 Bank 64 3.3V Input J5-B12 SAS1_GPTX_0 AL19 Bank 64 3.3V Output J5-A11...
  • Page 41 Settings Validated Cables and Transceiver Settings Validated Cables and Transceiver Settingsfor details. We recommend you always reach out to BittWare prior to designing your customized cabling. Please contact BittWare Technical Support for details; we will be happy to review your requirements and com- patibility with our product.
  • Page 42 5.5.2 Pinout CHAPTER 5 │ XUP-VV4 Hardware Reference Guide...
  • Page 43 6 Memory The XUP-VV4 features four DIMM sites that support standard DDR4 and proprietary QDR-II+ DIMMs. Additional on- board memory includes Flash with factory default and support for multiple FPGA images. © BittWare, 2021...
  • Page 44 6.1 DIMM The XUP-VV4 features four 288-pin DIMM connectors that support DIMMs in the following configurations: DDR4: x72 w/ECC Up to 128 GBytes per DIMM QDR-II+ x18 Up to 72 MBytes per DIMM Table 15 Supported DIMM Modules Type Size Test Speed RefClk (MHz) DDR4 RDIMM VLP 16GB 2400 DDR4 RDIMM...
  • Page 45 DIMM Power Architecture Table 16 DIMM Power Configuration Options Configuration DIMM connector installed, but no DIMM inserted 1.2V DDR4 installed 1.2V QDRII+ installed 1.8V 6.1.2 DIMM Support BittWare supports multiple DDR4 DIMMs in addition to a QDR-II+ DIMM as documented earlier in this section. Bitt- Ware does not support customers with non-standard or non-validated DIMMs installed.
  • Page 46 6.2 Flash Memory A 2 Gbit bank of flash memory is used to store FPGA configuration code. The flash contains a factory image and a user image. The configuration code can be loaded via the USB interface, using the BwConfig utility, which is included in BittWare's BittWorks II Toolkit, or it can be loaded via PCIe (requires BMC IP in the FPGA).
  • Page 47 7 Clock Circuitry The XUP-VV4 features the following on-board clocks: Two SI5341 high-performance programmable clock synthesizers 2x 48MHz crystal oscillators 322.265625 MHz oscillator Note: Refer to the Component Reference Table for a list of manufacturers and part numbers for the on-board clocks.
  • Page 48 7.1 Clock Configurations You can create your own clock configurations using a utility from Silicon Labs called "Clock Builder Desktop Soft- ware (Si534x)." BittWare also offers a quick start guide for using this utility, which is available on the BittWare developer site.
  • Page 49 7.3.2 Clock Circuitry XUP-VV4 Clock Circuitry (VU13P FPGA) CHAPTER 7 │ XUP-VV4 Hardware Reference Guide...
  • Page 50 8 Configuration, Status, and Setup This section covers the configuration, control, and support features on the board: FPGA configuration Status and setup elements (such as LEDs and switches) Board management controller © BittWare, 2021...
  • Page 51 8.1 FPGA Configuration The FPGA can be configured via the Flash memory or on-board USB and JTAG connectors. 8.1.1 Power-Up Reset The reset input pin (FPGA_RST_L, pin AW21) on the FPGA comes from the BMC. It is normally de-asserted and is pulsed from high to low and back by the BMC as detailed below.
  • Page 52 JTAG and USB Connections to the FPGA 8.1.3 Boot Image Location The boot image is stored in the board's Flash memory: Flash Partition 0 = Application Flash Partition 1 = Factory image 8.1.4 Boot Image Management The XUP-VV4 supports field updates of the FPGA images via PCIe or via USB. To perform a field update via USB, use the BwConfig utility, which is included with the BittWorks II Toolkit.
  • Page 53 8.2 Status and Setup Elements 8.2.1 LEDs The XUP-VV4 has eight LEDs (see Board Layout (Top View) for their locations). Four general-purpose LEDs are connected to the FPGA and are located on the top edge of the board. Four additional LEDs provide status of the FPGA and the microcontroller.
  • Page 54 accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I C bus components, field upgrades, and IPMI mes- saging.
  • Page 56 9 Power This section covers the board's power and standalone setup features: Power requirements External power connector Standalone setup © BittWare, 2021...
  • Page 57 9.1 Power Requirements Power requirements for the XUP-VV4 are application-specific. The card power draw might go from low, if the FPGA is unconfigured, to medium when the FPGA is programmed with one of the BittWare example designs for instance (downloads available on the BittWare Developer Site). FPGA designs with high resource utilization, high toggle rate, and high clock frequency will increase the card power draw, which might approach the card’s max power.
  • Page 58 Table 19 Sense pins decoding by the XUPVV4 Sense1 Sense0 Description A 2x4 auxiliary power connector is plugged into the card. The XUP-VV4 can draw up to 150W from the Ground Ground auxilliary power connector. Ground Open Reserved A 2x3 auxiliary power connector is plugged into the card. The XUP-VV4 can only draw up to 75W from the Open Ground auxiliary power connector.
  • Page 59 10 Mechanical 10.1 Chassis Requirements 10.1.1 PCIe Express The XUP-VV4 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes.The board requires a x16 PCIe slot for mechanical compatibility. 10.1.2 PCIe Bracket The board ships with a full-height dual-slot bracket for the front panel. BittWare P/N Description Delivery...
  • Page 60 10.3 Board Dimensions XUP-VV4 Top View with Dimensions...