Related Manuals for ADLINK Technology DAQ-2010
Summary of Contents for ADLINK Technology DAQ-2010
- Page 1 NuDAQ ® DAQ-2010/2005/2006 PXI-2010/2005/2006 4-CH, Simultaneous, High Performance Multi-function Data Acquisition Card User's Guide Recycle Paper...
- Page 2 ® ® ® ® NuDAQ , NuIPC , NuDAM , NuPRO are registered trademarks of ADLINK Technology Inc. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.
- Page 3 Getting service from ADLINK • Customer Satisfaction is the most important priority for ADLINK Tech Inc. If you need any help or service, please contact us. ADLINK Technology Inc. Web Site http://www.adlinktech.com Sales & Service Service@adlinktech.com NuDAQ + USBDAQ nudaq@adlinktech.com...
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Page 4: Table Of Contents
Table of Contents Tables..................iii Figures..................iv How to Use This Guide............vi Chapter 1 Introduction ............1 Features ................. 1 Applications ..............2 Specifications ..............3 Software Support ............9 1.4.1 Programming Library..............9 ® 1.4.2 D2K-LVIEW: LabVIEW Driver........... 10 1.4.3 PCIS-OCX: ActiveX Controls..........10 Chapter 2 Installation............ - Page 5 D/A Conversion............. 36 4.2.1 Software Update ..............37 4.2.2 Timed Waveform Generation..........37 Digital I/O..............44 General Purpose Timer/Counter Operation ..... 44 4.4.1 Timer/Counter functions basics........... 44 4.4.2 General Purpose Timer/Counter modes......45 Trigger Sources ............49 4.5.1 Software-Trigger..............49 4.5.2 External Analog Trigger............
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Page 6: Tables
Tables Table 1: -3dB small signal bandwidth........4 Table 2: System Noise............4 Table 3: CMRR: (DC to 60Hz) ..........5 Table 4: 68-pin VHDCI-type Connector Legend ...... 17 Table 5: Bipolar analog input range and the output digital code on DAQ/PXI-2010............ - Page 7 Figures Figure 1: PCB Layout of the DAQ-20XX ........13 Figure 2: PCB Layout of the PXI-20XX........13 Figure 3: 68-pin VHDCI-type pin assignment ......16 Figure 4: Single-Ended connections ........18 Figure 5: Ground-referenced source and differential input ..19 Figure 6: Floating source and differential input ......
- Page 8 Figure 35: Mode 7 Operation............ 48 Figure 36: Mode 8 Operation............ 48 Figure 37: Analog trigger block diagram ........49 Figure 38: Below-Low analog trigger condition ......50 Figure 39: Above-High analog trigger condition ......51 Figure 40: Inside-Region analog trigger condition ...... 51 Figure 41: High-Hysteresis analog trigger condition ....
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Page 9: How To Use This Guide
How to Use This Guide This manual is designed to help you use/understand the DAQ/PXI-20XX. The manual describes the versatile functions and the operation theory of the DAQ/PXI-20XX. It is divided into five chapters: Chapter 1, Introduction gives an overview of the product features, ap- plications, and specifications. -
Page 10: Chapter 1 Introduction
Introduction The DAQ/PXI-20XX is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap- plications in medical, process control, etc. Features DAQ/PXI-20XX Advanced Data Acquisition Card provides the fol- lowing advanced features:... -
Page 11: Applications
• Versatile trigger sources: software trigger, external digital trigger, analog trigger and trigger from System Synchronization Interface (SSI). • A/D Data transfer: software polling & bus-mastering DMA with Scatter/Gather functionality • Four A/D trigger modes: post-trigger, delay-trigger, pre-trigger and middle-trigger •... -
Page 12: Specifications
Specifications ♦ Analog Input (AI) • Number of channels: 4 differential • A/D converter: 2010: LTC1414 or equivalent 2005: A/D7665 or equivalent 2006: A/D7663 or equivalent • Max sampling rate: 2010: 2MS/s 2005: 500kS/s 2006: 250kS/s • Resolution: 2010: 14 bits, no missing code 2005/2006:16 bits, no missing code •... -
Page 13: Table 1: -3Db Small Signal Bandwidth
• -3dB small signal bandwidth: (Typical, 25° C) Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB) ±10V 1170 kHz 0~10V 1090 kHz ±5V 1050 kHz 0~5V 1020 kHz 2010 ±2.5V 800 kHz 0~2.5V 790 kHz ±1.25V 530 kHz 0~1.25V 530 kHz ±10V 1160 kHz... -
Page 14: Table 3: Cmrr: (Dc To 60Hz)
• CMRR: (DC to 60Hz, Typical) Device Input Range CMRR Input Range CMRR ±10V 90 dB 0~10V 89 dB ±5V 92 dB 0~5V 92 dB 2010 ±2.5V 95 dB 0~2.5V 94 dB ±1.25V 97 dB 0~1.25V 97 dB ±10V 86 dB 0~10V 85 dB ±5V... - Page 15 ♦ Analog Output (AO) • Number of channels: 2 channel voltage output • DA converter: LTC7545 or equivalent • Max update rate: 1MS/s • Resolution: 12 bits • FIFO buffer size: 1k samples per channel when both channels are enabled for timed DA output, and 2k samples when only one channel is used for timed DA output •...
- Page 16 ♦ General Purpose Digital I/O (G.P. DIO, 82C55A) • Number of channels: 24 programmable Input/Output • Compatibility: TTL/CMOS • Input voltage: Logic Low: VIL=0.8V max; IIL=0.2mA max. High: VIH=2.0V max; IIH=0.02mA max • Output voltage: Low: VOL=0.5V max; IOL=8mA max. High: VOH=2.7V min;...
- Page 17 ♦ External Analog Trigger Input (EXTATRIG) • Input Impedance: 40kO for DAQ/PXI-2010 2kO for DAQ/PXI-2005/2006 • Coupling: DC • Protection: Continuous ± 35V maximum ♦ Digital Trigger (D.Trig) • Compatibility: TTL/CMOS • Response: Rising or falling edge • Pulse Width: 10ns min ♦...
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Page 18: Software Support
♦ Storage Environment • Ambient temperature: -20 to 80°C • Relative humidity: 5% to 95% non-condensing ♦ Interface Connector: 68-pin AMP-787254-1 or equivalent Software Support ADLINK provides versatile software drivers and packages for users’ dif- ferent approach to building up a system. ADLINK not only provides pro- gramming libraries such as DLL for most Windows based systems, but also ®... -
Page 19: D2K-Lview: Labview Driver
® 1.4.2 D2K-LVIEW: LabVIEW Driver D2K-LVIEW contains the VIs, which are used to interface with NI’s Lab- ® VIEW software package. The D2K-LVIEW supports Windows 98/NT/2000. ® The LabVIEW drivers is shipped free with the card. You can install and use them without a license. -
Page 20: Chapter 2 Installation
Installation This chapter describes how to install the DAQ/PXI-20XX. The contents of the package and unpacking information that you should be aware of are outlined first. The DAQ/PXI-20XX performs an automatic configuration of the IRQ, and port a ddress. Users can use software utility, PCI_SCAN to read the system configuration. -
Page 21: Unpacking
Unpacking Your DAQ/PXI-20XX SERIES card contains electro-static sensitive com- ponents that can be easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. -
Page 22: Daq/Pxi-20Xx Layout
DAQ/PXI-20XX Layout 2005/2006/2010 Daughter Board Figure 1: PCB Layout of the DAQ-20XX 2005/2006/2010 Daughter Board Figure 2: PCB Layout of the PXI-20XX Installation • 13... -
Page 23: Pci Configuration
PCI Configuration Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. -
Page 24: Chapter 3 Signal Connections
Signal Connections This chapter describes the connectors of the DAQ/PXI-20XX, and the signal connection between the DAQ/PXI-20XX and external devices. Connectors Pin Assignment The DAQ/PXI-20XX is equipped with one 68-pin VHDCI-type connector (AMP-787254-1). It is used for digital input/output, analog input / output, and timer/counter signals, etc. -
Page 25: Figure 3: 68-Pin Vhdci-Type Pin Assignment
CH0+ 35 CH0- CH1+ 36 CH1- CH2+ 37 CH2- CH3+ 38 CH3- EXTATRIG 39 AIGND DA1OUT 40 AOGND DA0OUT 41 AOGND AOEXTREF 42 AOGND SDI3_1 / NC* 43 SDI3_0 / NC* SDI2_1 / NC* 10 44 SDI2_0 / NC* SDI1_1 / NC* 11 45 SDI1_0 / NC* SDI0_1 / NC* 12 46 SDI0_0 / NC*... -
Page 26: Table 4: 68-Pin Vhdci-Type Connector Legend
Legend: Pin # Signal Name Reference Direction Description Differential positive input CH<0..3>+ CH0<0..3>- Input for AI channel <0..3> EXTATRIG AIGND Input External AI analog trigger DA0OUT AOGND Output AO channel 0 DA1OUT AOGND Output AO channel 1 External reference for AO AOEXTREF AOGND Input... -
Page 27: Analog Input Signal Connection
Analog Input Signal Connection The DAQ/PXI-20XX provides 4 differential analog input channels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input signals. -
Page 28: 3.2.3 Differential Measurements
In single-ended configurations, more electrostatic and magnetic noise couples into the single connections than in differential configurations. Therefore, the single-ended connection is not recommended unless minimal wire connections are necessary. 3.2.3 Differential Measurements Differential Connection for Grounded-Reference Signal Sources The differential analog input provides two inputs that respond to the signal voltage difference between them. -
Page 29: Figure 6: Floating Source And Differential Input
Differential Connection for Floating Signal Sources Figure 6 shows how to connect a floating signal source to DAQ/PXI-20XX in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance. -
Page 30: Chapter 4 Operation Theory
Operation Theory The operation theory of the functions on the DAQ/PXI-20XX is described in this chapter. The functions include the A/D conversion, D/A conversion, Digital I/O and General Purpose Counter/Timer. The operation theory can help you understand how to configure and program the DAQ/PXI-20XX. The whole DAQ/PXI-2000 series cards, including DAQ/PXI-20XX, DAQ/PXI-22XX and DAQ/PXI-25XX, are designed based on the same logic-timing template of DAQ/PXI-22XX. -
Page 31: Daq/Pxi-2010 Ai Data Format
After the end of A/D conversion, the A/D data is buffered in a Data FIFO. The A/D data should be transferred into the PC's memory for further processing. 4.1.1 DAQ/PXI-2010 AI Data Format 4.1.1.1 Synchronous Digital Inputs (for DAQ/PXI-2010 only) When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI<1..0>_X per channel from J5 will be latched into the 16-bit register and data FIFO, as shown in Figure 7 and... -
Page 32: Table 5: Bipolar Analog Input Range And The Output Digital Code
Note: Since the analog signal is sampled when an A/D conversion starts (falling edge of A/D_conversion signal), while SDI<1..0> are sam- pled right after an A/D conversion completes (rising edge of nADBUSY signal). Precisely SDI<1..0> are sampled within 220 to 400ns lag to the analog signal, due to the variation of the conver- sion time of the A/D converters. -
Page 33: Daq/Pxi-2005/2006 Ai Data Format
4.1.2 DAQ/PXI-2005/2006 AI Data Format The data format of the acquired 16-bit A/D data is Binary coding. Table 7 and 8 illustrate the valid input ranges and the ideal transfer characteristics. The converted digital codes for DAQ\PXI-2005/2006 are 16-bit and direct binary, and here we present the codes as hexadecimal numbers. -
Page 34: Software Conversion With Polling Data Transfer Acquisition Mode (Software Polling)
4.1.3 Software conversion with polling data transfer acqui- sition mode (Software Polling) This is the eas iest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. -
Page 35: Programmable Scan Acquisition Mode
4.1.4 Programmable scan acquisition mode 4.1.4.1 Scan Timing and Procedure It's recommended that this mode be used if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least 2 counters, which need to be specified: SI_counter (24 bit): Specify the Scan Interval = SI_counter / TIMEBASE... -
Page 36: Figure 9: Scan Timing
3 Scans (PSC_Counter=3) ( channel sequences are specified in Channel Gain Queue) Scan_start ADCONV Acquisition_in_progress Post Scan Count Scan Interval T= SI_COUNTER/TimeBase Figure 9: Scan Timing There are 4 trigger modes to start the scan acquisition, please refer to section 4.1.4.2 for more details. The data transfer mode is discussed in section 4.1.4.3. -
Page 37: Figure 10: Pre-Trigger
There are 4 trigger modes (pre-trigger, post-trigger, middle-trigger, and delay-trigger) working with the 4 trigger sources to initiate different scan data acquisition timing when a trigger event occurs. They are described as follows. For information of trigger sources, please refer to section 4.5. Pre-Trigger Acquisition Use pre-trigger acquisition in applications where you want to collect data before a trigger event. -
Page 38: Figure 11: Pre-Trigger Scan Acquisition
(M_counter = M = 3, PSC_counter=0) Trigger occurs Trigger Scan_start Data acquisition ADCONV won’t stop until this conversion completes Acquisition_in_progress Acquired data Acquired & stored data (M samples) Operation start Figure 11: Pre-trigger scan acquisition (trigger occurs when a conversion is in progress) When the trigger signal occurs before the first M scans of data are con- verted, the amount of stored data could be fewer than the originally speci- fied amount M_counter, as illustrated in figure 12. -
Page 39: Figure 13: Pre-Trigger With M_Enable = 1
(M_counter = M = 3, PSC_counter=0) The first M scans Trigger signals which occur in the shadow region(the first M scans) will be ignored Trigger Scan_start ADCONV Acquisition_in_progress Acquired data Acquired & stored data (M scans) Operation start Figure 13: Pre-trigger with M_enable = 1 Note: The PSC_counter is set to 0 in pre-trigger acquisition mode. -
Page 40: Figure 14: Middle Trigger With M_Enable = 1
(M_Counter=M=3, PSC_Counter=N=1) The first M scans Trigger signals which occur in the shadow region(the first M scans) will be ignored Trigger Scan_start ADCONV Acquisition_in_progress Post Scan Count Acquired data M scans before N scans trigger after trigger Operation start Acquired & stored data (M+N scans) Figure 14: Middle trigger with M_enable = 1 If the trigger event occurs when a scan is in progress, the stored N scans of... -
Page 41: Figure 16: Post Trigger
Note: M_counter defined in Middle-Trigger is different from that of Pre-Trigger. In Middle-trigger, M_Counter ends counting before the trigger event while in Pre-Trigger, M_Counter ends counting right at or before trigger event. Please refer to figure 11 and figure 15. Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. -
Page 42: Figure 17: Delay Trigger
(PSC_Counter=3 Trigger Scan_start ADCONV Acquisition_in_progress Post Scan Count Delay until Acquired & stored data Delay_Counter (3 scans) reaches 0 Operation start Figure 17: Delay trigger Note: When the Delay_counter clock source is set to TIMEBASE, the maximum delay time = 2 /40M s = 1.638ms, and when the source is set to A/D sampling clock, the maximum delay time can be as higher as (2... -
Page 43: Figure 18: Post Trigger With Re-Trigger
(PSC_Count er=2, retrig_no=3) Trigger Scan_start ADCONV Acquisition_in_progress Post Scan Count Acquired & stored data (6 scans) Operation start Figure 18: Post trigger with re-trigger 4.1.4.3 Bus-mastering DMA Data Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. -
Page 44: Figure 19: Scatter/Gather Dma For Data Transfer
In a multi-user or multi-tasking OS, like Microsoft Windows, Linux, and so on, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PLX IOP-480 provides the function of scatter /gather or chaining mode DMA to link the non-continuous memory blocks into a linked list so that users can transfer very large amounts of data without being limited by the fragment of small size memory. -
Page 45: D/A Conversion
D/A Conversion There are 2 channels of 12-bit D/A output available in the DAQ/PXI-20XX. When using D/A converters, users should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. Users could also select the output polarity: unipolar or bipolar. The reference selection control lets users fully utilize the multiplying characteristics of the D/A converters. -
Page 46: Software Update
The D/A conversion is initiated by a trigger source. Users must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from PC’s main memory to a buffering Data FIFO. There are two modes of the D/A conversion: Software Update and Timed Waveform Generation are described, including timing, trigger source con- trol, trigger modes and data transfer methods. -
Page 47: Figure 20: Typical D/A Timing Of Waveform Generation
4 update counts, 3 iterations (UC _Counter=4, IC_Counter=3) Trigger DAWR WFG_in_progress Delay until Delay until Delay until DLY1_Counter DLY2_Counter DLY2_Counter reaches 0 reaches 0 reaches 0 DA update_interval t= UI_Counter/Timebase Output Waveform Operation start A single waveform Figure 20: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Note: 1.The maximum D/A update rate is 1MHz. -
Page 48: Figure 21: Post Trigger Waveform Generation
8 update counts, 1 iterations (UC _Counter=8, IC_Counter=1) Trigger DAWR WFG_in_progress Output Waveform Operation start Figure 21: Post trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Delay-Trigger Generation Use delay trigger when you want to delay the waveform generation after a trigger event. -
Page 49: Figure 23: Re-Triggered Waveform Generation
Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In figure 23, each trigger signal will initiate a waveform generation. However, the trigger event would be ignored while the waveform generation is ongoing. -
Page 50: Figure 24: Finite Iterative Waveform Generation With Post-Trigger
4 update counts, 3 iterations (UC _Counter=4, IC_Counter=3) Trigger DAWR WFG_in_progress Output Waveform A single waveform Operation start Figure 24: Finite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) 4 update counts, infinite iterations (UC _Counter=4, IC_Counter= 4) Trigger... - Page 51 Delay2 in Repetitive Waveform Generation To diversify the D/A waveform generation, we add a DLY2 Counter to separate 2 consecutive waveforms in repetitive waveform generation. The time between two waveforms is set by the value of DLY2 Counter. The Delay2 counter starts to count down after a waveform generation finishes, and the next waveform generation starts right after it counts down to zero, just as shown in figure 20.
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Page 52: Figure 26: Stop Mode I
4 update counts, infinite iterations (UC _Counter=4, IC_Counter=3) Trigger DAWR WFG_in_progress Output Waveform Operation start Software stop command Figure 26: Stop mode I (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) 4 update counts, infinite iterations (UC _Counter=4, IC_Counter=3) Trigger DAWR... -
Page 53: Digital I/O
Digital I/O The DAQ/PXI-20XX contains 24-lines of general-purpose digital I/O (GPIO), which is provided through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be indi- vidually programmed to be either inputs or outputs. -
Page 54: General Purpose Timer/Counter Modes
All the polarities of input/output signals can be programmed by software. In this chapter, for easy explanation, all GPTC_CLK, GPTC_GATE, and GPTC_OUT are assumed to be active high or rising-edge triggered in the figures. 4.4.2 General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. -
Page 55: Figure 30: Mode 2 Operation
Software start Gate Count value Figure 30: Mode 2 Operation 4.4.2.3 Mode 3: Single Pulse-width Measurement In this mode the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is in its active state. -
Page 56: Figure 32: Mode 4 Operation
Software start Gate Count value Figure 32: Mode 4 Operation 4.2.2.5 Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro- grammable pulse-width following an active GPTC_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC_CLK input. -
Page 57: Figure 34: Mode 6 Operation
S o f t w a r e s t a r t I g n o r e d G a t e C L K C o u n t v a l u e O U T Figure 34: Mode 6 Operation 4.2.2.7 Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to mode5 except that the counter generates con-... -
Page 58: Trigger Sources
Trigger Sources We provide flexible trigger selections in the DAQ/PXI-20XXseries products. In addition to the internal software trigger, DAQ/PXI-20XX also supports external analog, digital triggers and SSI triggers. Users can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger. -
Page 59: Table 11: Analog Trigger Src1 (Extatrig) Ideal Transfer Characteristic
Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V 0x81 0.08V 0x80 0x7F -0.08V 0x01 -9.92V Table 11: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic The trigger signal is generated when the analog trigger condition is satis- fied. There are five analog trigger conditions in the DAQ/PXI-20XX. The DAQ/PXI-20XX uses threshold... -
Page 60: Figure 39: Above-High Analog Trigger Condition
4.5.2.2 Above-High analog trigger condition Figure 39 shows the above-high analog trigger condition, the trigger signal is generated when the input analog signal is higher than the High_Threshold voltage, and the Low_Threshold setting is not used in this trigger condition. Figure 39: Above-High analog trigger condition 4.5.2.3 Inside-Region analog trigger condition Figure 40 shows the inside-region analog trigger condition, the trigger... -
Page 61: Figure 41: High-Hysteresis Analog Trigger Condition
4.5.2.4 High-Hysteresis analog trigger condition Figure 41 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration. Figure 41: High-Hysteresis analog trigger condition 4.5.2.5 Low-Hysteresis analog trigger condition Figure 42 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the... -
Page 62: External Digital Trigger
4.5.3 External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXTDTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process, and the EXTWFTRG is used for D/A process. -
Page 63: Daq Timing Signals
Internal timing signals SSI timing Signals SSI timing DAQ timing Signals signals Trigger_Out timing signals AFI timing signals Figure 44: DAQ signals routing Users can utilize the flexible timing signals through our software drivers, and simply and correctly connect the signals with the DAQ/PXI-20XX se- ries cards. -
Page 64: Auxiliary Function Inputs (Afi)
SCAN_START, the signal to start a scan, which would bring the fol- lowing ADCONV signals for AD conversion, and could come from the internal SI_counter, AFI[0] and SSI_AD_START. This signal is syn- chronous to the TIMEBASE. Note that the AFI[0] should be TTL-compatible and the minimum pulse width should be the pulse width of the TIMEBASE to guarantee correct functionalities. -
Page 65: Table 13: Auxiliary Function Input Signals And The Corresponding Functionalities
Category Timing signal Functionality Constraints 1. TTL-compatible Replace the internal 2. 1MHz to 40MHz EXTTIMEBASE TIMEBASE 3. Affects on both A/D and D/A operations 1. TTL-compatible External digital 2. Minimum pulse width Dedicated = 20ns EXTDTRIG trigger input for A/D input operation 3. -
Page 66: System Synchronization Interface
EXTTIMEBASE When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE, the 40MHz clock, users could utilize the EXTTIMEBASE with internal counters to achieve the specific timing intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIMEBASE. -
Page 67: Table 14: Summary Of Ssi Timing Signals And The Corresponding Functionalities As The Master Or Slave
SSI timing signal Functionality SSI master: send the TIMEBASE out SSI slave: accept the SSI_TIMEBASE to replace the internal SSI_TIMEBASE TIMEBASE signal. Note: Affects on both A/D and D/A operations SSI master: send the internal AD_TRIG out SSI_AD_TRIG SSI slave: accept the SSI_AD_TRIG as the digital trigger signal. - Page 68 The mechanism of the SSI/PXI We adopt master-slave configuration for SSI/PXI. In a system, for each timing signal, there shall be only one master, and other cards are SSI slaves or with the SSI function disabled. For each timing signal, the SSI master doesn’t have to be in a single card.
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Page 69: Ai_Trig_Out And Ao_Trig_Out
4.6.4 AI_Trig_Out and AO_Trig_Out AI_Trig_Out (or AO_Trig_Out) is the signal output following one of the four trigger sources (software trigger, analog trigger, digital trigger and SSI trigger) selected by the user. That is, AI_Trig_Out follows the A/D trigger source, and AO_Trig_Out follows the D/A trigger source. These two si g - nals can be used to control external peripheral circuits or boards, or can be used as synchronization control signals. -
Page 70: Chapter 5 Calibration
Calibration This chapter introduces the calibration process to minimize AD meas- urement errors and DA output errors. Loading Calibration Constants The DAQ/PXI-20XX is factory calibrated before shipment by writing the associated calibration constants of TrimDACs to the on-board EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability. -
Page 71: Auto-Calibration
Auto-calibration By using the auto-calibration feature of the DAQ/PXI-20XX, the calibration software can measure and correct almost all the calibration errors without any external signal connections, reference voltages, or measurement de- vices. The DAQ/PXI-20XX has an on-board calibration reference to ensure the accuracy of auto-calibration. -
Page 72: Warranty Policy
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the fo llowing carefully. Before using ADLINK’s products, please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form. - Page 73 To ensure the speed and quality of product repair, please download application form from company website www.adlinktech.com . Damaged products with RMA forms attached receive priority. For further questions, please contact our FAE staff. ADLINK: service@adlinktech.com Test & Measurement Product Segment: NuDAQ@adlinktech.com Automation Product Segment: Automation@adlinktech.com...
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