Epson SG-8506CA Applications Manual
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Epson SG-8506CA Applications Manual

Epson SG-8506CA Applications Manual

Programmable crystal oscillator
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ETM52E-04
l
Application Manua
Programmable Crystal Oscillator
SG-8506CA
Preliminary

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Summary of Contents for Epson SG-8506CA

  • Page 1 ETM52E-04 Application Manua Programmable Crystal Oscillator SG-8506CA Preliminary...
  • Page 2 The information about applied circuitry, software, usage, etc. written in this material is intended for reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any patent or copyright of a third party. This material does not authorize the licensing for any patent or intellectual copyrights.

  • Page 3: Table Of Contents

    Reconfiguring Frequency Setting ..................16 C interface ..........................17 Connection of I C Bus ......................17 C Bus Protocols Supported by the SG-8506CA ............... 18 START Condition and STOP Condition ................18 Byte Format and ACK/NACK ....................19 Read/Write to Register ......................19 7.

  • Page 4: Overview

    SG-8506CA Overview Programmable crystal oscillator: SG-8506CA is a low jitter programmable XO at any frequency. Its output frequency is programmable from 50 MHz to 800 MHz with almost 2 ppb resolution. SG-8506CA consists of XO, PLL and LVPECL output buffer.

  • Page 5: Part Number

    SG-8506CA 2. Part Number ⚫ Standard (Factory preset start-up frequency product) ⚫ Blank (one-time programmable start-up frequency product) Page - 2 ETM52E-04...

  • Page 6: Block Diagram

    SG-8506CA Block Diagram * If OE pin is configured as active low, OE pin is pulled down to GND with internal pull down resistor. Figure 3.1. SG-8506CA Block Diagram Page - 3 ETM52E-04...

  • Page 7: Pin Assignments

    Positive Power Supply Input/Output C Data Input/Output Input: LVCMOS interface levels, Output: Open drain Input C Clock Input Note: “Pull-up” or “Pull-down” refers to SG-8506CA internal input resistors. *Note 1: External pull-up resistor to V is necessary. Page - 4 ETM52E-04...

  • Page 8: Electrical Characteristics

    SG-8506CA 5. Electrical Characteristics Absolute Maximum Ratings Item Symbol Condition Min. Typ. Max. Units Supply voltage, V GND = 0 V -0.3 Pull-up voltage SDA, SCL -0.3 Input voltage 1 GND = 0 V, GND - 0.3 + 0.3 Input pins except to SDA and SCL...
  • Page 9 SG-8506CA Table 5.2. Logic I/O = 2.5 V - 5% ~ 3.3 V + 10%, GND = 0 V, Ta = -40 ~ +85 °C Item Symbol Conditions Min. Typ. Max. Units Pull-up voltage SDA, SCL x 0.7 3.630 High level input voltage 1 x 0.7...

  • Page 10: Ac Characteristics

    SG-8506CA AC Characteristics Table 5.3. Output Frequency Characteristics = 2.5 V - 5% ~ 3.3 V + 10%, GND = 0 V, Ta = -40 ~ +85 °C Item Symbol Conditions Min. Typ. Max. Units Output frequency OUT, OUTN Internal crystal frequency 114.144...
  • Page 11 SG-8506CA Frequency Change Time Page - 8 ETM52E-04...
  • Page 12 SG-8506CA Phase Noise Test Circuit Page - 9 ETM52E-04...
  • Page 13 SG-8506CA Table 5.4. Serial Interface = 2.5 V - 5% ~ 3.3 V + 10%, GND = 0 V, Ta = -40 ~ +85 °C Item Symbol Conditions Min. Typ. Max. Units SCL clock frequency Hold time (repeated) START condition, HD;STA...

  • Page 14: Lvpecl

    SG-8506CA LVPECL Table 5.5. LVPECL = 2.5 V - 5% ~ 3.3 V + 10%, GND = 0 V, Ta = -40 ~ +85 °C Item Symbol Conditions Min. Typ. Units Output load condition L_PECL Outputs terminated with 50 Ω to V –...
  • Page 15 SG-8506CA OE function (Active High) OE function (Active Low) Page - 12 ETM52E-04...

  • Page 16: Startup

    SG-8506CA Startup Table 5.6. Startup = 2.5 V - 5% ~ 3.3 V + 10%, GND = 0 V, Ta = -40 ~ +85 °C Item Symbol Conditions Min. Typ. Units ramp rate from 0 V to V 5 x 10...

  • Page 17: Functions

    Functions Overview The SG-8506CA has a XO, PLL and output buffer unit. The XO unit is composed of a fundamental mode crystal that generates stable reference clock for PLL. The output frequency is determined by the feedback divider and the output divider. The feedback divider can offer not only integer setting that achieves lower jitter, but also fractional setting that provides frequency in ppb resolution.
  • Page 18 SG-8506CA Table 6.1. f and ODIV [MHz] ODIV ODIV.ODIV register setting 50 ~ 57 53 ~ 67 64 ~ 80 80 ~ 100 91 ~ 114 106 ~ 133 128 ~ 160 159 ~ 200 182 ~ 229 213 ~ 267...

  • Page 19: Reconfiguring Frequency Setting

    SG-8506CA Reconfiguring Frequency Setting The SG-8506CA has a “user register” and a “PLL register”. The user register stores ODIV, NINT and NFRAC. It can be reprogrammed at any time when I C bus is available. The PLL register is connected directly to the PLL.

  • Page 20: I 2 C Interface

    C interface Connection of I C Bus The SG-8506CA can be used as a slave device of I C bus. The I C bus is composed of serial data line (SDA) and serial clock (SCL). The lines need to be both pulled up by external resistors. Electric level of the pull up resistor need to be above the Vcc so these are recommended to be pulled up to the Vcc.

  • Page 21: I 2 C Bus Protocols Supported By The Sg-8506Ca

    SG-8506CA C Bus Protocols Supported by the SG-8506CA I2C bus protocols that can be supported by the SG-8506CA are shown in the below Table 6.3. Table 6.3. I C bus protocols supported by the SG-8506CA Feature SG-8506CA ✓ START condition ✓...

  • Page 22: Byte Format And Ack/Nack

    Procedure of Read/Write to register is shown in the below Figure 6.5. The SG-8506CA can Read/Write single or multi byte data. The SG-8506CA slave address is able to be specified by the customer. It will be programmed to non-volatile memory at our factory.

  • Page 23: Registers

    SG-8506CA 7. Registers List of registers Register Address name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x46 (Ascii ‘F’, Read Only) 0x00 P_CODE0 0x06 (Read Only) 0x01 P_CODE1 0x01 (Read Only) 0x02 0x01 (Read Only) 0x03 ID_CODE0 ID (Read Only)

  • Page 24: Revision Code Register

    SG-8506CA Revision Code Register Register Address name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x02 Type Default Name Function Revision code 0x01 ID Code 0 Register Register Address name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ID_CODE0 0x03...

  • Page 25: Odiv Register

    SG-8506CA ODIV Register Register Address name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ODIV ODIV 0x10 Type Default Name Function Reserved Please write 0 at all the times. ODIV Division ratio of output divider 0x0: 4 0x4: 8 0x8: 16...

  • Page 26: Nfrac Register

    SG-8506CA NFRAC Register Register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 NFRAC[23:16] 0x12 NFRAC_H NFRAC[15:8] 0x13 NFRAC_M NFRAC[7:0] 0x14 NFRAC_L Type Default Name Function NFRAC[23:16] Fractional portion of the feedback divider (N FRAC NFRAC[15:8] E.g. Setting in case N...

  • Page 27: Pll Control Register

    SG-8506CA PLL Control Register Register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x15 PLL_CTRL0 NEW_FR SML_CH NVM_RE OE_REG STORE 0x50 PLL_CTRL1 Type Default PLL_CTRL0 and PLL_CTRL1 is an address shared register. Name Function OE_REG Output enable register function LVPECL output buffer is enable when OE pin or this register is set as 1/High as shown below table.

  • Page 28: Dimensions

    SG-8506CA 8. Dimensions Page - 25 ETM52E-04...

  • Page 29: Device Marking

    SG-8506CA 9. Device Marking ⚫ Standard (Factory preset start-up frequency product) ⚫ Blank Sample (SG-Writer II programmable start-up frequency product) The above marking layout shows only marking contents and their approximate position, not actual font, size and exact position. Page - 26...

  • Page 30: Soldering Pattern

    SG-8506CA 10. Soldering Pattern Example of patterning design indicated as follows. In an actual design, please consider mounting density, the reliability of soldering, etc. and check whether performance is optimal. Page - 27 ETM52E-04...

  • Page 31: Application Note

    Especially the quality of telecommunication equipment could be affected by this phenomenon. Although Epson’s crystal products are designed to minimize the effect of mechanical vibration, we recommend checking them in advance.
  • Page 32 So please use the products that always have connection with load resistance. 15. As with any high speed analog circuitry, the power supply pins for SG-8506CA are vulnerable to noise. In order to achieve optimum jitter performance, the 0.1 μF and 10 μF capacitor as shown below is required.
  • Page 33 This figure shows an example of this product’s application schematic. As with any high speed analog circuitry, the power supply pins for SG-8506CA are vulnerable to noise. In order to achieve optimum jitter performance, power isolation with filter device is required for power supply pins.
  • Page 34 SG-8506CA Page - 31 ETM52E-04...

  • Page 35: Application Manual

    Unit 715-723 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong Phone: (86) 755-2699-3828 (Shenzhen Branch) Fax: (86) 755-2699-3838 (Shenzhen Branch) www.epson.com.hk Epson Taiwan Technology & Trading Ltd. 15F, No.100, Songren Rd., Sinyi Dist.,Taipei City, 11073 Taiwan www.epson.com.tw/ElectronicComponent Epson Singapore Pte., Ltd.

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