System Board; Arbitration Bus Priority Assignments; System Memory Map; System Board Memory Connector - IBM Personal System/2 60 Technical Reference

Section 3. System Board
Description ..........0.0..0 000.0000 eee ee 3-3
| Micro Channel Implementation ....................... 3-3
| Exception Reporting ....... 0... 0.0.00 eee eee 3-3
Adapter Identification .......................0..., 3-3
Central Arbiter ....................0..0....0000. 3-3
Arbitration Bus Priority Assignments ............... 3-4
Central Arbiter Programming .................... 3-5
Memory ...... 0.0.00. ee eee ey 3-7
Read-Only Memory Subsystem ....................., 3-7
Random Access Memory Subsystem ................. 3-7
System Memory Maps ...............2.......... 3-8
System Board Memory Connector ................. 3-9
Real-Time Clock/Complementary Metal-Oxide Semiconductor
RAM ©. 0. Le ee eee 3-10
RT/CMOS Address Register and NMI Mask (Hex 0070) .. 3-11
RT/CMOS Data Register (Hex 0071) ............... 3-11
RT/GMOS RAM I/O Operations .................. 3-12
Real-Time Clock Bytes (Hex 000-00D) .............. 3-13
CMOS RAM Configuration ..................... 3-16
Miscellaneous System Functions ..................... 3-20
Nonmaskable Interrupt ....................200005 3-20
System Control Port B (Hex 0061) ...............0.. 3-20
System Control Port A (Hex 0092) ...........0..0... 3-21
Power-On Password .....................000005 3-23
Hardware Compatibility .................00..0..0..., 3-24
© Copyright IBM Corp. 1989, 1990 3-1