Melexis MLX73290-A Manual

300 to 960mhz multi-channel transceiver with 3dlf low power interface
Table of Contents

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Features and Benefits
3DLF interface for low power wake-up
Backup mode for battery less operations
RSSI information for LF and RF interfaces
LF/ RF intelligent self-polling modes for low power
operations
Multi-band frequency coverage from 300MHz up to
960MHz
Modulation schemes supported:
(G)FSK, (G)MSK, OOK
Transmitter power of -20 to 13dBm, 64 steps
Receiver sensitivity of -120dBm (FSK, 433MHz,
15kHz CHBW)
Application Examples
Low-power tracking systems
Secure access systems
Passive Keyless Entry / Start (PKES)
Ordering Code
Product
Temperature
MLX73290
R
Legend: R for -40°C to 105°C
Introduction
The MLX73290-A combines a highly integrated Radio Frequency transceiver for long range, high speed
communication and a 3 dimensional low frequency interface (3DLF) for low power wake-up. This unique
combination makes the MLX73290-A suitable for applications requiring a very low power wake-up function
together with long range, high speed RF feedback.
The transceiver part allows for multi-channel operation including frequency hopping in the European bands
(433MHz and 868MHz) as well as in North America or Asia bands (315MHz or 915MHz). The output power,
frequency channel, modulation type and frequency deviation are programmable. Thanks to the high
frequency resolution and phase noise performance of its fractional-N PLL, the MLX73290-A is fit for narrow-
band operation. There are two selectable modulation schemes: binary on-off keying (OOK) and binary
frequency shift keying (FSK) as well as their Gaussian filtered versions. The low-IF receiver part comprises
fully digital demodulation and self-polling features together with channel scanning and built-in packet
recognition.
The 3DLF interface features an automatic and programmable wake-up algorithm together with an integrated
data decoder to receive the payload. Monitoring independently the RSSI information from the 3-axis LF front-
ends allows precise monitoring of the received LF field. Thanks to its internal rectifier, power management
and
load
modulator,
390107329001
Rev 003
300 to 960MHz Multi-channel Transceiver
Package
LQ
LQ for 32L QFN5x5
the
MLX73290-A
is
Page 1 of 63
With 3DLF Low Power Interface
Supply voltage range of 2.1 to 3.6V
PLL synthesizer with 60Hz resolution
Channel filter bandwidth of 9 to 600kHz
Data rate of 0.3 to 250kbps (GFSK)
Frequency deviation up to 125kHz
32MHz crystal frequency
SPI interface with embedded FIFO, 256bytes for
RF and 8bytes for LF interfaces 4 programmable
GPIO ports
32L QFN5x5 package
Conform to EN 300 220, DASH7, FCC part 15,
Japan ARIB STD-T67, Korean and other standards
Option
ABA-000
capable
of
battery-less
MLX73290-A
Packaging Form
RE or TU
RE for reel (5000 pcs.)
LF
RFID
tag
operation.
Data Sheet
April/2016

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Summary of Contents for Melexis MLX73290-A

  • Page 1 Thanks to the high frequency resolution and phase noise performance of its fractional-N PLL, the MLX73290-A is fit for narrow- band operation. There are two selectable modulation schemes: binary on-off keying (OOK) and binary frequency shift keying (FSK) as well as their Gaussian filtered versions.
  • Page 2: Table Of Contents

    8.1 Simulated output power ................................58 8.2 Spectrum Plots ..................................... 59 8.3 Eye Diagram ....................................60 8.4 Phase Noise ....................................60 9 Manufacturability of Melexis Products with Different Soldering Processes ..............61 10 ESD Precautions ................................61 11 Package Information ..............................62 12 Disclaimer ..................................63...
  • Page 3: Glossary Of Terms

    3 Pin Definitions and Pin-out XTALP LF3P XTALN LF3N VSSA LF2P MLX73290-A LF2N LF1P LF1N GPIO0 VSSA GPIO1 Figure 1: Pin-out of MLX73290-A 390107329001 Page 3 of 63 Data Sheet Rev 003 April/2016...
  • Page 4 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Pin № Name Type Function Supply Supply of PA LF3P Analog LF Positive input 3 LF3N Analog LF Negative input 3 LF2P Analog LF Positive input 2 LF2N Analog...
  • Page 5: Electrical Specifications

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 4 Electrical Specifications 4.1 Normal operating conditions Parameter Symbol Test Conditions Units Supply voltage Operating temperature (R) R version °C Input low voltage (CMOS) Digital pins 0.3 * V...
  • Page 6 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Parameter Symbol Test Conditions Units 100kbps, FSK, NRZ, 0dBm TX,433MHz 100kbps, FSK, NRZ, 10dBm 100kbps, FSK, NRZ, 0dBm TX,868MHz 100kbps, FSK, NRZ, 10dBm 100kbps, FSK, NRZ, 0dBm TX,915MHz 100kbps, FSK, NRZ, 10dBm...
  • Page 7: Lf Characteristics

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Parameter Symbol Test Conditions Units @ 1MHz offset -110 dBc/Hz PH_1MHz Frequency resolution RX/TX switching time Δt μs RXTX RX or TX frequency change μs Crystal oscillator Crystal oscillator frequency...
  • Page 8 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Parameter Symbol Test Conditions Units = 32kHz Register Tstandby [3:0] “0000” (3*t “0001” (5*t “0010” (4*t “0011” (8*t “0100” (6*t “0101” (14*t Average current consumption “0110” (10*t µA in scan mode “0111”...
  • Page 9: Spi Characteristics

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 4.5 SPI Characteristics Operating Conditions T = -40 C to 105 C, V = 2.1V to 3.6V (unless otherwise specified) Parameter Symbol Test Conditions Units SPI Clock Frequency SCLK SCK high time SCK ↑...
  • Page 10: Functional Description

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 5 Functional Description 5.1 Frequencies and standards The MLX73290-A complies with the following frequency bands and radio standards. freq. band max. ERP channel BW max. data rate Comment [MHz]...
  • Page 11: Detailed Description

    A built-in power switch selects the power voltage from the battery or from the 3DLF interface (through an internal bridge rectifier). This is used in case of low battery, to supply the MLX73290-A and the host MCU with the power recovered from the interface LF-1.
  • Page 12 Valid header Receive payload found, receiving Manchester violation data or FIFO overrun Idle Disable all coils, (standby) update LFRX_COIL standby to select next coil Figure 4: MLX73290-A 3DLF State-machine flow-chart 390107329001 Page 12 of 63 Data Sheet Rev 003 April/2016...
  • Page 13: Reception Mode (Self-Polling Mode)

    AGC settling RCclk counting RCclk settling coil1_listen standby standby coil2_listen coil3_listen coilx_header 40 t 12 t RCclk RCclk settling counting coilx_enck frozen depending on coilxabovey Figure 5: MLX73290-A 3DLF self-polling mechanism 390107329001 Page 13 of 63 Data Sheet Rev 003 April/2016...
  • Page 14: Data Format

    ������ 5.4.6 RSSI Mode The MLX73290-A features a receive signal strength indicator (RSSI) block used to measure the level of the LF field. The RSSI measurement corresponds to the logarithmic functions of the RMS values measured on the LF-input selected with the bits...
  • Page 15: Transmission Mode (Tx)

    5.4.7 Transmission Mode (TX) In transmit mode, the MLX73290-A recovers the LF carrier frequency, to use it as a clock signal for the 3DLF State Machine, insuring that the device is always synchronized on the incoming LF field. The recovered LF...
  • Page 16: Rf Transceiver

    MLX73290-A device. 5.5.2 Transmit mode (TX) In RF transmit mode, the MLX73290-A outputs a CW signal on the differential RF outputs RFP and RFN. The output power can be configured from -20dBm up to 13dBm according to the bits...
  • Page 17: Receive Mode (Rx)

    At the end of the waiting periods, the timer restarts and sets the corresponding IRQ flag TMR_FLAG, the MLX73290-A is set in receiver mode looking for a valid synchronization word SYNC_WORD[31:0], during a certain time as defined in the State Machine chapter just above. The RX period might be preceded by periodic recalibration as configured by CALIB_MODE.
  • Page 18: Rssi Information

    RF TX and/or RF RX FIFOs. In receive mode, the MLX73290-A first waits for a matching synchronization word defined in registers SYNC_WORD[31:0], then move to the “RX receiving payload” state and start the reception of the payload.
  • Page 19 Furthermore there is the option to set a threshold RX_RSSI_TH on the RSSI, below which reception is inhibited. The MLX73290-A also features a termination timer programmable between 64µs and 32s (RXTERM_MANT[3:0] and RXTERM_EXP[3:0]). When the timer expires, termination may be postponed while RSSI is above the threshold, or while payload is being received, depending on the setting of the bit RXTERM_COND.
  • Page 20: Modulation Settings

    Table 8 : Modulation Settings 5.7 Packet Handler The MLX73290-A embeds a packet handler mechanism, able to manage the encoding/decoding of the transmit/received bytes contain in the RF FIFO. Different frame formats are supported and can be fully configured by the user, the following picture shows the different formats supported in transmit and receive...
  • Page 21: Preamble

    Figure 8: RF Packet Handler: Packet correction principle 5.7.1.4 Manchester Encoder/Decoder A built-in Manchester encoder/decoder is implemented in the MLX73290-A, enabled with the bit EN_MANCHESTER in unbanked register 0x27. By default, the Manchester polarity is set to “normal” but it can also be reversed with the bit BIT_INVERT.
  • Page 22: Address

    Note: The Data whitening operation is only performed on the data to be sent (payload + address + CRC16) and NOT on the SYNC_WORD and PREAMBLE. 5.8 Power Management Unit The power management unit of the MLX73290-A performes the following operations: • It measures the battery voltage (VDDA3) at power-on reset (POR) and decides whether the voltage is sufficient to power up the MLX73290-M and to supply the host MCU through pin VMAIN (if ≥...
  • Page 23: Programmable Timer / Clock Generator

    For more information about the programmable timer, please refer to the chapter 6.4 below. 5.10 System timer The MLX73290-A embeds a 23-bit free-running counter that can serve as a time reference. When enabled, it increments at 7.8 kHz derived from the calibrated RC clock. Counter overflows (every ~18 minutes) will set a flag, which may wake-up the microcontroller.
  • Page 24: General Purpose Adc

    SPI Clock The pin SDO is set to high impedance by the MLX73290-A when not transmitting SPI information; this allows a configuration using only one pin to successively send/receive information from/to the MLX73290-A. The two configurations using classical 4-pin and optimized 3-pin are illustrated below:...
  • Page 25 Opposite to most conventional SPI devices, the CS chip select input of the MLX73290-A is active high. When the CS is set low, the MLX73290-A is deselected as SPI-slave; SCK and SDI can take any level, and SDO is tri-state. When CS goes high, the MLX73290-A becomes selected, and expects from the host MCU a 7-bit register address preceded by one bit of direction (0 = write, 1 = read).
  • Page 26: Gpio Pins

    With 3DLF Low Power Interface 5.13 GPIO Pins Four general purpose I/O (GPIO) pins are available in the MLX73290-A (GPIO0 to GPIO3). Several digital signals can be output, e.g. to be further used by the host MCU. Each GPIO pin has an 8-bit GPIOx_CH_SEL[7:0] (registers addresses 0x38 to 0x3B) setting that configures the I/O type of the corresponding pin (analog/digital, input/output) and the signal routing to/from the pin.
  • Page 27 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface GPIOx_CH_SEL Signal Name Description 001000 Fixed logic 0 MLX73290-A is ready after start-up sequence 001001 READY (POR) Battery level measured above the minimum level 001010 BATTOK 2.1V. 001011 Output of uncalibrated internal RC oscillator...
  • Page 28 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface GPIOx_CH_SEL Signal Name Description 110010 3DLF_RX_DATA 3DLF State Machine receiving data 3DLF State Machine checking header or receiving 110011 3DLF_RX_HDR_DATA datas RFRX_PKT_3DLF_PAYLOAD_ RF packet received or 3DLF receiving payload or...
  • Page 29: Register Settings

    With 3DLF Low Power Interface 6 Register settings The MLX73290-A is configured through a set of 126 unbanked registers for current use (addresses from 0x02 to 0x7F). One additional bank of 128 registers (Bank 0) is also available for specific information (addresses from 0x00 to 0x7F).
  • Page 30 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface INVERT CHESTER WHITE PREAMBLE PACKET ADDRESS POSNEG_ FSK_NOOK EN_INTERP POSNEG_IF DIRECT_MOD[2:0] GAUSSIAN RX_RSSI_TH[3:0] RXTERM_EXP[3:0] RXTERM_MANT[3:0] RXTERM_COND[1:0] CALIB_MODE[2:0] PWRUP_ PWRUP_TIME[3:0] MODE RXTERM RXUNLOCK RXERR RXOK TXOK_ACT[1:0] _ACT _ACT _ACT _ACT...
  • Page 31 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 7…0 AFC[7:0] Lower byte of AFC value Table 16: Unbanked register 0x06 Bit(s) Signal Init Description Upper byte of AFC value; to ensure consistency between 7…0 AFC[15:8] the bytes, use one SPI access cycle to read both bytes of AFC.
  • Page 32 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description EN_CORRECT_ISI Enable the ISI (Inter-Symbol-Interference) correction EN_FINE_RECOV Enables fine carrier recovery EN_ROUGH_RECOV Enables rough carrier recovery EN_FAST_PRE_CR Enables fast carrier recovery during the preamble Adjust data rate :...
  • Page 33: Corr

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description EN_D7M1 Enable DASH7 mode 1 DASH7 mode 1 : D7M1_TAG_NINT 0 = interrogator 1 = tag Enable the reception and transmission of packets EN_MULTI_FRAME consisting of multiple frames...
  • Page 34: Dr_Limit[1:0]

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Middle 8 bits of the fractional division ratio of the PLL for 7…0 CENTER_FREQ[10:3] the center frequency Table 32: Unbanked register 0x1D Bit(s) Signal Init...
  • Page 35 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Scaling to be applied to the pulse shaping coefficients by 7…4 MULT_EXP[3:0] shifting them in the modulator, equivalent to 2 MULT_EXP Mantissa of the coefficient that multiplies the signal, equal 3…0...
  • Page 36: Iq_Corr

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description IQ_CORR_EN Enable I/Q imbalance correction I/Q imbalance calibration in progress; set this bit to start I/Q imbalance calibration, automatically cleared by hardware IQ_CORR_CAL when calibration is finished. Clear this bit to abort calibration.
  • Page 37 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Select the modulation type : FSK_NOOK 0 = OOK 1 = FSK EN_GAUSSIAN Enable Gaussian pulse shaping / matched filtering EN_INTERP Enable interpolator on TX modulator output...
  • Page 38 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description After timeout has expired, postpone termination: 0 = always (i.e. never terminate) 1 = never (i.e. terminate unconditionally) 7…6 RXTERM_COND[1:0] 2 = as long as RSSI is above threshold,...
  • Page 39 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Action to take for RX termination timeout RXTERM_ACT 0 = go to error state 1 = flush RF RX FIFO, recalibrate RX, then RX Reserved...
  • Page 40 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Present RF mode: 0 = stopped TX 1 = stopped RX 2 = TX 7…5 RF_MODE[2:0] 3 = RX 4 = calibrate TX, then stop...
  • Page 41 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Packet received, with correct length, address and CRC (if RF_RXFLAG checking enabled); cleared when RF RX FIFO is flushed or a byte is read from the RF RX FIFO...
  • Page 42: Status Byte & Gpios (0X34 To 0X3B)

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Number of bytes in the RF TX FIFO When the FIFO contains 256 bytes, RFTXFIFO_CNT will be 0 but RFTXFIFO_USE will be active. When 7…0...
  • Page 43 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Started in : BATTOK 0 = Battery backup mode 1 = Normal mode PLL_LOCKED PLL is currently in-lock A PLL cycle-slip has been registered since the last read...
  • Page 44: General Purpose Adc (0X3C To 0X3F)

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Reserved 6…0 GPIO2_CH_SEL[6:0] 0x34 See chapter 5.13 Table 63: Unbanked register 0x3A Bit(s) Signal Init Description Reserved 6…0 GPIO3_CH_SEL[6:0] 0x14 See chapter 5.13 Table 64: Unbanked register 0x3B 6.3 General purpose ADC (0x3C to 0x3F)
  • Page 45 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description New data sample available, can be cleared, not set. Set by hardware upon completion of an ADC measurement, ADC_NEWDATA automatically cleared by hardware when lower byte of clear conversion results is read.
  • Page 46: Timers (0X40 To 0X4F)

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 6.4 Timers (0x40 to 0x4F) Addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Timers TMR_MANT[7:0] TMR_SOURCE[1:0] TMR_MODE TMR_EXP[4:0] TMR_FLAG SYS_TIME[7:0]...
  • Page 47 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Output of programmable timer / clock generator TMR_FLAG IRQ flag in timer mode, that will stop the timer and needs to be cleared by the microcontroller 6…0...
  • Page 48 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description 7…0 POLL_PERIOD[7:0] Lower byte of 16-bit period of RF polling timer Table 80: Unbanked register 0x49 (RF polling timer) Bit(s) Signal Init Description · ( 1+��������_������������ ) 7…0...
  • Page 49: 3Dlf Transceiver (0X50 To 0X5F)

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 6.5 3DLF Transceiver (0x50 to 0x5F) Addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3D LF transceiver COIL1_TRIM[5:0] COIL2_TRIM[5:0] COIL3_TRIM[5:0]...
  • Page 50 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description 7…6 Reserved Force 3DLF front-end enabled, set to ‘0’ for normal EN_3DLF operation Recovered carrier clock source, set to ‘0’ for normal operation : 0 = automatically selected 4…3...
  • Page 51 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description 3DLF RX polarity: LFRX_POL 0 = Normal, Manchester pattern 01 will yield 0 as data bit 1 = Reverse, Manchester pattern 01 will yield 0 as data bit...
  • Page 52 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description 7…5 Must be set to ‘111’ LFRX_MASK[2:0] Bit order in reception mode: LFRX_ORDER 0 = LSB first 1 = MSB first 3…0 LFRX_STBY[3:0] See Table 6: LF characteristics...
  • Page 53: Chip Id And Soft Reset (Register 0X7F)

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description Accesses the data in the 3DLF RX FIFO 7…0 LFRXFIFO[7:0] The register address is not auto-incremented Table 99: Unbanked register 0x5F read (3DLF FIFO) Bit(s)
  • Page 54: Bank 0

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 6.7 Bank 0 Addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Test and spare signals 00..06 PN9_ CRC_ PN9_ PGA_...
  • Page 55 MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface Bit(s) Signal Init Description 7…5 Reserved recommended setting = 3 �� Minimum counter value for valid preamble, ������������������,������ �� 4…0 LFRX_MINCNT[4:0] ����������,������ – margin Table 108: Bank0 register 0x50...
  • Page 56: Application Information

    7.1.1 TX/RX Combining Network The RF ports of the MLX73290-A have been designed in order to achieve optimum performance in both TX and RX mode as well as for different RF power levels and at various frequency bands. For this purpose two inductors are used per single-ended RF port.
  • Page 57: Balun

    With 3DLF Low Power Interface 7.1.2 Balun A Balun is used to convert from differential input/output of the MLX73290-A to single-ended signal from/to the RF antenna. Off-the-shelf baluns are available on the market, depending on the wanted frequency range, the actual implementation will vary.
  • Page 58: Performance Plots

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 8 Performance Plots 8.1 Simulated output power Simulated output power , f=915MHz, P =13dBm Simulated output power , f=869MHz, P =13dBm 20.00 20.00 10.00 10.00 0.00 0.00 -10.00 -10.00 -20.00...
  • Page 59: Spectrum Plots

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 8.2 Spectrum Plots Figure 19: FSK (black) and GFSK (blue) spectrum at 250kbps, ±50kHz deviation 390107329001 Page 59 of 63 Data Sheet Rev 003 April/2016...
  • Page 60: Eye Diagram

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 8.3 Eye Diagram Figure 20: 250kbps GMSK transmit signal eye diagram at 868MHz 8.4 Phase Noise 434MHz 868MHz Figure 21: 434MHz and 868MHz phase noise plots 390107329001 Page 60 of 63...
  • Page 61: Manufacturability Of Melexis Products With Different Soldering Processes

    Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board.
  • Page 62: Package Information

    MLX73290-A 300 to 960MHz Multi-channel Transceiver With 3DLF Low Power Interface 11 Package Information The device MLX73290-A is RoHS compliant. exposed pad The “exposed pad” is connected to internal ground, it can be connected to the PCB. Figure 16: 32L QFN 5x5 Quad all Dimension in mm 4.75...
  • Page 63: Disclaimer

    No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services.

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