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CDA-7865R
No.
Symbol
0
Terminal Description
8
AVss3
— _ | GND
connect terminal for analog circuit.
9
AVppD3
— | Power supply terminal for analog circuit.
10
FBAL
© | Focus Balance adjustment output terminal.
11
TBAL
O | Tracking Balance adjustment output terminal.
12
FE
| | Focus Error signal input terminal.
(Analog input)
13
a
NC
— | Noconnect terminal.
15
TE
| | Tracking Error signal input terminal.
(Analog input)
16
|
r
NC
—
|No connect terminal.
18
19
RFENV
| | RF Envelope signal input terminal.
(Analog input)
20
VREF
| | VREF input terminal.
21
ARF
| | RF signal input terminal.
(for DSL)
22
DRF
| | Bias terminal for DSL.
23
DSLF
VO | Roop Filter terminal for DSL.
24
IREF
|__|
Reference current input terminal.
25
PLLF
VO | Roop Filter terminal for PLL.
26
PLLF2
VO | Characteristic Roop Filter switching terminal for PLL.
VCOF
VO | Roop Filter terminal for VCO.
28
VCOF2
VO | Digital Servo Processor (33.8688MHz) / Roop Filter terminal for VCO.
29
TRV
O | Traverse compulsion sending output terminal.
30
TVD
O | Traverse drive output terminal.
31
PC
O | Spindle motor ON output terminal.
32
ECM
O | Spindle motor driving signal terminal.
(compulsion mode output) 3-State
3
ECS
O | Spindle motor driving signal terminal.
(Servo Error signal output)
34
KICK
O | Kick Pulse output terminal.
3-State
35
TRD
O | Tracking Drive output terminal.
36
FOD
O | Focus Drive Output terminal.
37
TOFS
O | Tracking Offset adjustment output terminal.
38
AVppD2
— | Power supply terminal for analog circuit (DSL, PLL, AD and DA block).
39
AVss2
— | GND connect terminal for analog circuit (DSL, PLL, AD and DA block).
40
DVss2
— | GND connect terminal for Digital circuit.
41 | EFMor CK384 (NC) eee No connect terminal.
bi
EVPor Deke
.
Fa
Aes
ce
: DSL Balance output
43
/CLDCK
O | Sub Code Frame Clock signal output terminal.
(fCLDCK=7.35KHz)
44
FCLK
O | Crystal Frame Clock signal outputterminal.
(fecLK=7.35KHz)
45
IPFLAG
O | Interpolation Fiag signal output terminal.
—_H : Interpolation
46
FLAG
O | Flag signal output terminal.
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