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RELEASE INTERRUPT
A device initiates a release interrupt when it is released by
another controller. The controller does not respond to any
release signals from devices unless the Condition Release
Interrupt order first enables the release interrupt logic. If
a TIO, TDV, HIO, or SIO instruction is issued to another
device, the interrupt call is temporarily removed until the
instruction is completed. An AIO or HIO to the interrupt-
ing device clears the interrupt.
ON-SECTOR INTERRUPT
An on-sector interrupt indicates one of two things: a de-
vice has completed a Seek order or a Restore Carriage order
{bit 4 of AIO); or a Seek timeout has occurred (bit 6 of
AIO). The device signals on-sector to the controller when
the heads are not in motion and the head is accessing the
sector prior to the one addressed. Before the control I er wi 11
generate an on-sector interrupt for any device, it must re·-
ceive a Seek or a Restore Carriage order with the modifier
bit set. An interrupt ca 11 {CIL) is set at the start of the
sector prior to the one addressed by the order and is dropped
at the start of the next sector if not cleared by an AIO in-
struction. The CIL is reinitiated the next revolution, how-
ever. An on-sector interrupt is temporarl ly removed by a
TIO, TDV, HIO, or SIO to another device. An AIO, HIO,
or I/O Reset clears it. Please note that an AIO or HIO
clears only the single interrupt, whereas 1/0 Reset also
clears pending interrupts (CIL not set).
DISK SYSTEM ERROR DETECTION ENVIRONMENT
Logic is provided within the controller for automatic detec-
tion of errors in the data flow in and out of the control I er.
Included are !OP parity check, device address parity, read
check character bytes, and fl le address verification.
IOP AND CONTROLLER PARITY CHECKS
Odd parity is generated and checked for data transfers.
Both the !OP and the controller can drive odd parity and
perform parity checking. On the Sigma 9 computer, parity
checking is performed on al I data transfers, single- and
four-byte. However, on the Sigma 5-7 computers, parity
is checked only for these specific data: seek address, sense
bytes, headers, and single-byte transfers.
Generally, this is what occurs {qualified by the Sigma 5-9
restrictions just cited); The controller drives odd parity for
all data-in transfers to the !OP for single- and four-byte
transfers, and drives parity checking on all transfers initi-
ating from it. Odd parity is checked for a
11
data-out on
the single-byte interface.
If the !OP drives the parity
check, the check includes all data transfers on single- or
four-byte transfers.
"Transmission error" indicates data
parity errors and "unusual end" indicates order and address
parity errors.
DEVICE
ADD~ESS
PARITY
The controller generates odd parity for the four device ad-
dress I ines; the device goes "not operationa I" if a parity
error is detected.
READ CHECK CHARACTER BYTES
A two-byte check character is written at the end of each
record (header or data).
The controller initially computes
and inserts these check characters, and recomputes and com-
pares them with those read on any Read or Check-write or-
der. "Transmission error" indicates any check byte error on
data records, and "unusual end" indicates any check byte
error on headers.
FILE ADDRESS VERIFICATION
File addresses are verified by several means.
During each
Seek, the controller automatically reads back from the de-
vice and verifies the file address (cylinder, head, track,
sector) and any differences. It verifies the angular position
of the heads for multiple sector-record Read and Write orders.
The control I er also verifies file address by comparing it with
that read in the header. Any file address verification error
results in order termination with "unusual end".
1/0 FAULT DETECTION AND RECOVERY ACTIONS
The program can determine whether a disk pack 1/0 opera-
tion was completed successfuHy or terminated due to a fault
condition by evaluating the status response and condition
code bits obtained by issuing AIO and TDV instructions
after an 1/0 interrupt.
The program must perform tests to determine whether the 1/0
interrupt is due to a device-g1enerated interrupt or a channel
end or unusual end interrupt - the two are mutually exclu-
sive. If the status bytes received with an AIO do not indi-
cate a device-generated interrupt, assume a channel end or
unusual end interrupt.
TESTS FOLLOWING
D~VICE
1/0 INTERRUPTS
The following tests can be performed after receipt of a de-
vice interrupt to determine
th~
type of interrupt:
1.
Seek timeout error intem,.1pt. If AIO status bit 6 is set,
the device has generated the Seek timeout error inter-
rupt as a result of a hardware malfunction during head
movement.
Use recovery action 3 {see "Recovery
Actions" later in this chapter).
2.
On-sector interrupt.
If AIO status bit 4 is set, the
device has generated the: on-sector interrupt to indicate
the addressed sector's minimum access position time, or
to indicate head motion completion for a Restore Car-
riage order.
34
Disk System Error Detection Environment/1/0 Fault Detection and Recovery Actions
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