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STATUS RESPONSE
The I/O instructions can request a device to return detailed
I/O status information when the instruction is executed.
Detailed descriptions of the Sigma I/O instructions are in
the Sigma Computer Reference Manuals; summary status in-
formation is discussed in the following sections and related
tables and figures.
CONDITION CODES
When an I/O instruction is executed, condition code bits I
and 2 are set to describe the general status of the addressed
1/0 device and controller.
(Condition code 3 is also
meaningful for an I/O instruction - when set it means
either the status returned in the registers is not reliable or
the status has not been returned to the registers; when reset
(zero) it means the status information is reliable.
Note,
however, that the device and control I er do not influence
CC3 - the IOP does.) Table 4 lists the CC I and CC2 set-
tings and their significance for the I/O instructions.
Table 4. Condition Code Settings
1/0
Instruction CCI CC2 Significance
SIO
0
0
1/0 address recognized and SIO
accepted.
0
I
I/O address recognized, SIO
not accepted.
I
0
Not applicable.
I
I
I/O address not recognized.
HIO
0
0
I/O address recognized and de-
vice not "busy" when halt
occurred.
0
I
1/0 address recognized and de-
vice "busy" when halt occurred.
I
0
HIO not accepted; controller
"busy" with device other than
one addressed •
I
I
I/O address not recognized.
TIO
0
0
1/0 address recognized and SIO
can currently be accepted.
0
I
I/O address recognized, but SIO
cannot be currently accepted.
I
0
Not applicable.
I
I
1/0 address not recognized.
18
Key Events
Table 4. Condition Code Settings (cont.)
1/0
Instruction CCI CC2 Significance
TDV
0
0
1/0 address recognized.
0
I
Deviice controller in test mode.
I
0
Controller busy with a device
other than one addressed.
I
I
1/0 address not recognized.
AIO
0
0
Normal interrupt recognition.
0
I
Unusual conditiont, interrupt
condition, or control I er is
switched to a test mode.
I
0
Not applicable.
I
I
No i,nterrupt recognition.
tAn unusual condition is one in which the Seek timeout
error, unusual end, or transmission error storage elements
were set in the previous operation.
DEVICE
ST~TUS
BYTE
A .device status byte is returned to the register when an 1/0
instruction is executed. This byte also describes the status
of the addressed device and its controller, but in more de-
talled fashion than do CCI and CC2. The significance of
each bit is shown in Tables S, 6, and 7.
The device status byte is set (It the beginning of an SIO,
TIO, or HIO instruction.
It:
is set as the result of a TDV
instruction.
For an SIO, it. is set upon receipt of the
instruction if there is an interrupt pending.
OPERATIONAt STATUS BYTE
In addition to the information returned in the device status
byte, the operational status byte generated at the end of
each SIO, HIO, TIO, and TDV instruction execution also
provides indicators to the controlling system (see Table 8).
IOP STATUS BYTE
In place of an Operational Status Byte, an AIO instruction
returns an !OP Status Byte in the same bit positions of the
register. Table 9 summarizes the meanings of the settings
of these bit positions.
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