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from
I
to 0
it
puts
out
a
pLrlse
*hich
irllvances the
couDt on the sccod-l (tens) counter
b!'
one
nuu]bcr.
anil so on
through
all six
Lrnits. When the Counted
Signal Gate
is
closed, thc indicating counter units
displav the number ol the
last cycle received.
Thus.
the
numbe|
oI cvcles displa]'ed
alter
operling
thc Sig-
nill
Gate
lor
exirctly
1
sccond indicates the Irequency
directlv in
cps.
3.3
TIME
BASE
SECTION
'fhc iime
Base
Sectiolr. supplies six
staDdald
Il'e-
quencies: 100.
10 and
1
kilocycles.
100.
10
ancl
1
cycles per se(ond. Thc
'Iime
Base consists of
a
crystirl-controlled.
100-kc
oscillator,
a
series
of
fiv{-, 10
to
1
pirantastron frequency
diviCers,
alid
a
plug-in
decade
divider.
The
plug-in
decade
divider
di!i,l(,s
tire phantastron fr.cquencies
frorll
the
Time
Ilase by
10
duriDg fr'.quer)cy measurentents
anC
lllo
input
signrl
frequencv
l)v
10
Curing
10
PEIUOD
aver-
agc
mcasulem€nt. The sanrc high
accuracl
obtained
Irom thc
crvstrl
oscillittol. is 3lso obtxined $ith all
di!i.lcd
I|equ.rncres rhcn th.r
cilCuits are
ill
corr'ect
iidJ
ustrnent.
The irltcr:r.rl Irequencv stilnCard
IoI
thc
5228
is
lr
cr]stlI-ci)ntrolled. 100-lic.
odilic.i Picrce
or
Colpitts
oscillator.
TIle
crl/still
has a
lo\v
temper-
irtLrrc
coeifici(.ot
anC
is
enclose.i
in
a
temperature
contlolled over to
ol)tain
a f1.equency
stability
oI
bettcl.
tharr
ten parts/
m
iilion/
rveek.
The phantastr.on
Ilequencv
dilid{]rs
and
the
Dec;lde
Divirler
plLrg-in
unit
alrc
.lescribed
below.
3.4
PHANIASIRON
FREQUENCY
DIVIDERS
The
{ive
staldard
gate
trures,
.001. .U1.
0.
1.
1.0
and
10
sec,
anC
t'vo frequoncy
units.
nlilliseconcls
and
secords
are
obtaiDL'C
by
dividing t}le 100-kc cry-stal-
co
ntlolled flcquelcy in
steps
of 10.
Fil'c
10:1
phan-
tastr.on
IrcqucD(!,
diviciers
conuected
in cils.tlldc
so
that
each
di\'ides
rhc output
oI tlte pr.evious
one
to
prcrluce standard lrequencies
of
10
kc,
1
kc,
100
cps
urd
10
cps. The
operatioD
oI
cach
dilider
is the
saDle;
onlv
the
valLre
of one capacitor.
in
erlch sui)scquetlt
divicier
circuii is
changed
to obtain
a
ton-times longer
time constant.
The shapcs
oI the outllut
wiitvelorDl
Ironl
the
dividers are sil1rilar, lalge
uirsyI1rrnetri(ral
posrti\'(,pulses.
Division in
a phantastrou
circuit is
accomplished
bl
adiusting the
time
constant
01
the
circuit
so
that
otle
period
of phantastron opcration Iasts nine c!,cles
oI
the input
Irequenc,\'actually
a
division of
tinre.
Duling
the
pel'iod ot operation the phantastlon
is
not a-lfccted
Sect.
In
Page
3
tr.v
subscquent
input
cycles. After
the
period of
oper-
ation. thc
phirntastr'on
is
l'eturned to
its original
state.
ready
to
Lr.r
tliggered
l)y
the
nexl input
cycIe.
ConsequeDtly, the phaltastron pllts out
one Pulse
Ior
each
ten
c1,cles
(lI input lrequency; but
note
that
ir divides
by
10
only at the
one
lreqLrellcy
-
at other
fr'equencics.
if
not
ri'ltdjusted.
it
divides
by another
Iactor,
always
ploducing pulses haying practically
tile sarre period. regardless of the input Irequc,lcy.
To pIel,ent any oI the lrine
intermediate input clcles
fl.om
preDlaturely operating the
phantastlon, the in-
put signal
is
fed
thlough
a
diode
gate (v109A
in Fig.
J-2) which blocks input cycles during the phantastron
cycle.
The
blocliing
is
accomplished
by
connecting
the diode
plate
to
the
plate of the phantastron
V110,
and
biasing the diode cathode
a
Iew
volts
belo'v the
plate.
WheD
the phantastlon
plate voltage,
and thus
the diode
plate vol'.age.
is high,
the
diode
gate
ls
open
:rnd
the input signai is
pass€d
to the
phantastron.
When
the phantastron
is
triggered
by
an
input signal.
its
plate voltagedrops
and
cuts ofI the diode,
thus
closing the
gate. The pharttastron plate roltage
re-
mairs
down (and
the gate closed)
during nine periods
oi
the input frequency. At the
end
of
its
cl'cle
the
phantastron plate
loltage rises,
the
diode gate is
opened and
the next
(10th)
cycle
triggers
the phantas-
tron-
The switching actjon
in
the phantastron
circuit is
as
Iollows:
Refer
to
Fig.
3-2.
Phantastron
tube
V110
is
a
special
pentode
in \\hich
the suppressor
grid is tightly
wound
iind c:m be use(l as a
sec.Jlrd
control
grid for
the plate
current.
but ]rot
1()r
the screen
current. This
leature
makes
it
possib.le
to switch the
cathode
current Irom
plate to screen
atrd
vise versa. ln this circuit
the
initial
stable state has
cllrrent
going
to the
screen,
0
volts
between
control grid
and
cathode,
and the
cathode
is
25
r'olts positive. The suppressor grid,
lleirg
retulned to
[!r'ouDd.
is thus negative,
and
blocks
current to
the
plrte
such
tllat
cathode
current
goes
to
the scre€.n
grid.
When
a
legativc
irlput pulse
is applied to the phantas-
tron
contl.ol
grid.
the cathode
1'oltage
dIops,
the
neglrtive
bias
oD
the sLlppressor
is
instantaneously
renroved
and
the
cat\ode
current slr'itches to the plate.
CurreDt
coDtinues
to
the
plate
until
the
charge
on
C206
discharges through the
series resistor
R210,
the
control grid
Yoltage
returns in
a
positive direction.
cathode
voltage following until the suppressor-to-
ca.thode
bias
is
again
negative
and
the
plate current
cut
olf.
Actually the voltage
on
the suppressor is
nlaintained constani by voltage
divider
R211,
212,
and
213. while the
contlol-gl'id ard
cathode voltage
. move together as
in
a cathode
follower to ailect
the
shift
in supprcssor-grid bias. This
shilt in
bias is
held
Lr-v
the
time
constant
oI timing capacitor
C206
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