Aiwa CSD-ED88 Service Manual page 29

Pin No. Pin Name I/O Description
41 RFSM O Output RF.
42 RFS- O Establish RF gain and 3T compensation value from EFM signal with RFSM pin.
43 SLC 0 SLICE LEVEL CONTROL; Control data slice level by DSP with RF waveform.
44 SLI I Control data slice level by DSP.
45 DGND
-
Digital GND.
46 FSC 0 Connected to focus search smoothing capacitor.
47 TBC I
TRACKING BALANCE CONTROL: Establish EF balance variable range.
48 NC - Not used.
49 DBF
o
Output disc defect detection.
50 CLK I Input reference clock. Inputs 4.23MHz from DSP.
51 CL I Input microcomputer command clock.
52 DAT I
Input microcomputer command data.
53 CE I Input microcomputer command chip enable.
54 DRF 0 Detect RF: Output RF level detection.
55 FSS I
FOCUS SEARCH SELECT; Switches focus search mode (between ± search
and + search against reference voltage). (Not used)
56 VCC2
-
Servo/digital VCC.
57 REFl
-
Connected to reference voltage bypass condenser.
58 VR 0 Output reference voltage.
59
LF2
-
Establish value in detecting disc defect.
60 PHI
-
Connected to capacitor used to hold peak of RF signal.
61 BHI
-
Connected to capacitor used to hold bottom of RF signal.
62 LDD 0 APC-circuit output pin.
63 LDS I APC-circuit input pin.
64
VCCl - RF VCC.
42