Aiwa CSD-ED88 Service Manual page 27

Pin No. Pin Name I/O
Description
38 LVSS
-
Left channel ground.
39 RVSS
-
Right channel ground.
40 RCHO
0
Right channel output.
41 RVDD
-
Right channel power supply.
42 MUTER
0
Right channel mute output. (Not used)
43 XVDD
-
Crystal oscillator power supply.
44 XOUT
o
Connections for a 16.9344MHz crystal oscillator element.
45 XIN I
46
XVSS
-
Crystal oscillator ground.
47 SBSY
0
Subcode block synchronization signal. (Not used)
48 EFLG
0
Cl, C2 single and double error correction monitor pin. (Not used)
49
PW
o
Subcode P,Q,R,S,T,U and W output. (Not used)
50
SFSY
o
Subcode frame synchronization signal output. (Not used)
51 SBCK I
Subcode readout clock input. (Connected to OV)
52
FSX
o
Output for the 7.35kHz synchronization signal divided from the crystal oscillator.
(Not used)
53
WRQ
o
Subcode Q output standby output.
54 RWC
I Read/Write control input.
55 SQOUT
0
Subcode Q output.
56
COIN I
Command input from the control microprocessor.
57 CQCK I
Input for command input acquisition clock and SQOUT pin subcode readout clock.
58 RES
I
Chip reset input.
59
Til
0
Test output. Leave open. (Not used)
60 16M
0
16.9344MHz output. (Not used)
61 4.2M
o
4.2336MHz output.
62 T5
D
Test input. (Connected to OV)
63
D
Chip select input. (Connected to OV)
64 T1 I Test input. (Connected to OV)
40