Avtech AV-1010-C-NCSU Instructions Manual page 18

The second channel is delayed by between 100 ns and 10
ms. The delay time is controlled by the capacitance
between pins 8 and 13 and the resistance between pin 8
and the +5.8V power supply. Different fixed capacitors,
corresponding to different delay ranges, are switched in
by the DELAY RANGE switch, SWl. The resistance is
varied by the DELAY potentiometer, PT3, and a_ series of
minimum fixed resistances, switched in by SWl. This
delayed pulse is then fed into a monostable
multivibrator to give a fixed 50 ns pulse width. SW5 is
in the DELAY or ADVANCE positions, the pulse is buffered
and applied directly to pin 12. If SW5 is in the DOUBLE
PULSE position, the two channels are added together to
give a double pulse on pin 12, with the spacing between
the leading edges of the pulses controlled by the delay
controls.
When SW5 is in the DELAY or DOUBLE PULSE positions, pin
6 is connected to the SYNC OUT connector and pin 12 is
connected to pin 4 of the pulse width module. In the
DELAY mode, the main output of the AvV-1010 lags after
the SYNC output. In the DOUBLE PULSE mode, the first
pulse is nearly coincident with the first output pulse
in the doublet. In the ADVANCE mode, the connections
for pins 6 and 12 are swapped and the main output pulse
precedes the SYNC pulse. The module also contains a
GATE input, pin 14, which connects to the GATE connector
on the front panel. When a TTL high level (+2 to +5V)
is applied, triggering will be inhibited in all modes.
Normal triggering occurs when the GATE input is held low
or when the GATE input is left open (unconnected).
Pin connections
- Ground
2,3. The capacitance across the pins controls the.
frequency range of the internal oscillator
4. This is connected to the normally open terminal
of Swl0
5. +5.8V in
- Output 1. This is the leading output. The 50
ns pulse is used as the SYNC OUT pulse in the
DELAY and DOUBLE PULSE modes and as the trigger
for the PW module in the ADVANCE mode.
7. jINT/EXT. When this pin is grounded, by SW3, the
clock module is triggered by pin 4 of the
threshold module. When this pin is held at
+5.8V, the module is triggered by its internal
oscillator.
8. The delay timing resistance is placed across
this pin and +5.8V by SW1 and PT3
8,13. The delay timing capacitance is placed across
these pins by SW1
9. No connection