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I
I
•
PDS005A
( IC1004: MAIN UNIT)
•CD - ROM SIGNAL MANAGEMENT,
INTERFACE
vcc
RAIS
RAl4
RAl3
RAl2
RAii
RAIO
RA9
RAS
GND
RA7
RA6
RA5
RA4
RA3
RA2
RAI
RAO
GND
RD7
RDS
RD5
RD4
RD3
RD2
RDI
RDO
~
ROE
vcc
•
Block Diagram (Top View)
SECTOR
PROCESSOR
(ECC/ EDC)
I-
DATA-
BUS
I-
ADDRESS- BUS
~
NM~~m~romo-NM~~w~romo
MMMMMMMMM~~~~~~~~~~~
~
~
~~~~~~~~~
~
~~~~~~~~
r
O-
NM•~m~o
o-
N
M
·rrrrr
WWWWWWWW
WWWWWWwW
RAM
l/F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RESFIFO
CODA 1
/
F
HEADER
CAPTURE
SYSCON 1/F
COM FIFO
"" ""
0
i5
0
0
0
0
0
0
I
~
I
~
•
~
I~
I
~
I
~
0
0
w
({)
0
a._
z
z
z
z
0
a:
f-
a:
({)
N
>- >- >- >-
0
-'
ro
({)
0
({)
({)
({)
({)
<
0
ro
0
w
3:
>-
>-
({)
({)
DR- R504X
vcc
HAO
HAI
HA2
DREO
DACK
toP
HR!)
HWR
INT
r5TACT:
T6B
SREO
SDO
SDI
C2PO
BTCK
LRCK
BSYNC
GND
DSYNC
ESYNC
WSYNC
TESTA
TES
TB
TESTC
TES TD
SYSCLKO
CLKIN
vcc
CLKGEN
HOST
l/
F
~
0
0
I
55
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