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CIRCUIT DESCRIPTION
CIRCUIT DESCRIPTION
10—9. Timing chart
Period
fs
2) 2's complement/COB (Complemented Offset Binary)
'
192fs
256fs
!
;
freee theo peerbahchel
clock pulse frequency
(OW18, OW20)
,
Z|
5 om
rn
a
Reed
1
MsB
Leh data
tsp!
msB
Reh data
use!
|
ae
a ie
on
PORE
sco PEE
EEE EE
As to the number of bits for the output data, any of 16,
Data word length
tw
|
24*tsys | 32"Tsys |
Oi
mbrikawoaetacie
pam
18 and 20-bit can be selected.
t
Word Output Period
—
Tw
I
n bits
'
: 20—n bits =
eee
(
1
|
1 MSB 2 fede ]s|s [2 [------J2[fissl
1 |
\
© Serial output timing (DOL, DOR, BCKO, WCKO, DG)
n
!
1
§
BCKO
i
ere
9 eae
"~~ Th
I
bee--——----——.
Tw/4
|
|
!
|
be $$
pi
be
Ty |
i
1Bbit
!
1Bbit
|
con [etree
'
I
f
1
i
H
ee
DOR
Reh data
Rech data
wero
=
7]
=
|
3/4Tw
|
1
Twi/2
——™|
Tb pe
1
t
|
|
t
!
1
'
~
i
\
|
-
!
1
\
DG
'
CF 6 0a [eae
aR
cea
aR I a
[] ] eS ph ce Es ee
ee oe ah ch |
7
BCKO
t
| | ee
es
De
ae
a
{
D
|
|
i
i
Note
: n means
the number
of output word bits.
DG We
See
ee
1
Fig. 13
Output timing
Fig. 16
Serial output timing
7
+ System reset (RST)
When the reset input is made in the jitter-free mode,
the internal operation timing is reset in synchronization
with the leading edge of input LRCI. Making use of this,
the output timing in the jitter-free mode can be aligned
with input LRCI,
In the compulsory sync mode,
no system reset is
needed. Even in the jitter-free mode, the output timing
does not need to be aligned with input LRCI and no
system reset is necessary.
For system reset at power ON, externally connect a
capacity of around 100pF to pin RST. (Figure 10-7)
SM58134P
Fig. 14
Circuit example of system reset at power ON
36
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