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DP-7020
CIRCUIT DESCRIPTION
10-8. Function
* 8x over-sampling (interpolation) filter function
This function works to output the over-sampling data
of sampling rate 8fs. In this case, sampling noises be-
tween 0.5465fs (24. 1kHz) and 7.4535fs (328.69kHz) are
removed.
The interpolation operation block configuration of this
LSI is of a cascade connection of three 2x interpolation
filters (FIR).
ae
+ System clock (XTI, XTO, CKO, CKSL, CKDV)
The system clock pulse can be selected from 192fs,
256fs, 384fs and 512fs. More, operation is feasible even
by an external clock (input to pin XTI) or a crystal
oscillator (inserted between pins XTI and XTO). In this
unit, a clock pulse of 8.4672 MHz is input to pin XTI.
From pin CKO, the system clock pulse is output. (See
Figure 10-3.)
2x
interpolator
153¢d
(1st FIR}
2x
Interpolator
29th
{2nd FIR)
2x
Interpolator
A7th
DP-7020
CIRCUIT DESCRIPTION
+ Auto data input (DIN, BCKI, LRCI)
The input data is handied as being of 2's comple-
ment, MSB first. Each bit of the serial data input to pin
DIN is read in to register SIPO (serial/parallel conversion
register) a the leading edge of bit clock pulse BCKI, in
which it is in turn converted into a parallel data. The
output of SIPO is transferred to each of the Lch and Rch
input registers at the trailing/leading edge of clock pulse
LRCI.
In addition,
the operation
section and the output
section are independent in signal timing from the input
section and are therefore unsusceptible to the jitter of
the input section. (Jitter-free mote: For details, refer to
the description occurring later.)
on OC)
Input SIPO
16b)
sckt C)
Input Register 2
>
Lech
Input Register 2
>
Ren
FSCK
Fig. 11
Configuration of audio data input section
(3rd FIR)
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OUTPUT
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Fig. 9 Configuration of basic operation section
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Timing of Takes
to Input S1PO
XTI input clock
Fxi
|
urc!
—
G
256f:
384s
512fs
frequency (Fxi)_
= 1/tXI
s
1
-—-——
ee
eet, oe
|
Clock pulse
External clock (input to pin XTI) or internal clock
2
:
.
input method
(a crystal oscillator inserted between pin XT and XTO}. |
pie esse
eet Regaie}
Inout Rep
T
Internal system
*
clock pulse period
Tsys
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ons
|
L
Jock
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tX! stands for the XTI input clock pulse period.
Poise / '
1
.
'
loput Regrster 2
Input Register 2
Input Register 2
Table 10—1
System clock frequency selection and internal system clock
(ke 1) Taken
(n= 1) Takein
ities
16bits right before LRCI edge is taken in as data.
ig.
i
i
imi
r
CKSL Cr ics ah oe a
ee
ci
ee a ee
4
Fig. 12
Audio data input timing example
tkov [}~-
- ------~----------
>
7
TIMING
COUNTER
STARTING EDGE
DETECTOR
RESET
Division Ratio Selection
Each Part Timing
Fig. 10 Clock generation circuit
34
« Selection between jitter-free mode and compul-
sory sync mode (SYN, FSCO)
The signal timing (internal timing) applied to internal
operation or output, that is produced from the system
clock pulse {input to pin XTI), is independent from that
of the data input section (BCKI, LRCI).
For this internal timing, the method of countering the
jitter of clock pulse input LRCI is available in two types,
"jitter-free mode" and "compulsory sync mode". Se-
lection between these both is feasible by setting SYN.
1) Jitter-free mode (SYN="H")
As long as the phase difference between clock pulse
LRCI and the internal timing is within +3/8 to -3/8 of the
input sampling period (1/fs}, the internal timing is not
adjusted. Accordingly, even with a jitter component in
clock pulse LRCI, the internal timing is not affected so
that it is free from faulty operation or jitter transmission
to output.
When
the phase difference
is without the above
range, the internal timing is put in phase synchronously
with the start side of clock pulse
LRCI.
More,
this
treatment
is also performed when
the reset input is
given.
2) Compulsory sync mode (SYN="L")
When
this mode is engaged, the internal timing is
always reset at a pulse edge of the start side of input
LRCI. In this case, when a pulse period shorter than the
specified system clock pulse period exists due to the
jitter of input LRCI, a faulty operation may result.
Conversely, when a pulse period longer exists, the
operation is properly made but no equal output timing is
obtained.
3) Clock pulse FSCO (output)
This is a clock pulse with a period of fs obtained from
the dividing process of clock pulse XTI.
35
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