Panasonic KX-P1180 Service Manual page 26

KX-P1180
(5) Gate Array (IC9) Pin Function
The pin functions are as follows.
Head Duty Trigger
Carriage Trigger
BANK Address Bus <——
Address Bus (15:13) (—~>
Address Bus (7:0) <j
Option SRAM Chip Enable
SRAM Chip Enable ——_
Address Bus (7:0) <>
Address Latch Enable —__.
Write ———_-
Read
Reset ———
Reset ——_-
Carriage Motor <7—>
Line Feed Motor
Head Duty
(6) Chip Select Block
iC9
NHDT
NCAT
NBSY Centronics IF Busy
AB014, ABO15
AB13 — AB15
ABO — AB7
NCE3 DATA1—DATA8| <(—™> Centronics IF Data
NCE2
ADO — AD7
NRD ~__. Centronics IF Prime
NRS
NRT
LFA, LFB
HDTY X1, X2} ——_-_ Cristal
Gate Array have a MMU (Memory Management Unit).
CPU Memory Space expands from 64K bytes to 128K bytes by MMU.
The tables blow shows the levels of address signals used to select the corresponding memory area.
Memory Map
Optional RAM
(0 - 16KB)
*1
(0 — 16KB)
ROM1
(16 — 32KB) (32 ~ 48KB) (48 - 64KB)
Optional RAM Optional RAM Optional RAM
(16 — 32KB) (0 - 16KB) (16 — 32KB)
*1 *2 *2
STANDARD RAM (4K Bytes)
/O (Head, Parallel 1/0, Control Panel, Motor, etc.)
Include CPU RAM (256 Bytes)
Note: *2 reflected in the *1.
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