Panasonic KX-P1180 Service Manual page 25

KX-P1180
(4) Gate Array (IC9)
ICQ is a 64 — Pin Shrink Dip Package and it consists of 7 blocks as shown below.
NRT (a) Reset NRS
NPR Control
NHDT = Head ; HDTY
Contro HD(8:0)
AB(7:0)
(b) Address ™ f
A13 — 15 (c) Decoder
IMT
MMU NCE2, NCE3
all AB014, ABO1S
Ne (d) Read/Write
NRD Control
Bee==
ge== (d) Centronics
NBSY
NST
>
Interface
es (7:0)
(e) a an
game
Oc
p—el(h) Carriage,
Line
an Eee
Feed Motor
CRA, CRB, CRC,
=)
Control
CRD, LFA, LFB
NCAT
Address
Data Bus
(a) Reset Control!
NRS signal, generated by AND of Reset IC and IF Prime signals, performs resetting of the CPU, Gate
Array and Interface option.
(b) Address Latches
Address Latch Enable (ALE) signal latches Address Data Bus and generates AB (7 — 0) signal.
(c) Decoder / MMU (Memory Management Unit)
A decoder signal is generated by decoding the Addresses of 13,14 and 15 for register of the Head,
Centronics IF, Motor and others.
MMU with Bank Register perform the expansion of Address space.
(d) Read / Write Control
Read / Write signal with decoder control the read and write of the registers.
(e) 12 MHz OSC (Oscillator)
12 MHz OSC makes Gate Array internal clock.
(f) Head Control
Head Control signal controls the Head Pin fire time from start to finish.
(g) Centronics Interface
Gate Array automatically generates Busy signal triggered by data input and Strobe signals.
(h) Carriage / Line Feed Motor Control!
Gate Array controls the movement of carriage and line feed motors like a out put port.