Wilder Technologies PCIEG5-M2-TPA3-CLB User Manual page 16

PCIe Gen-5 M.2 Socket-3 Test Adapters User Manual
Table 4. PCIe Gen-5 M.2 Socket-3 Plug (CLB) Pin Assignments
Pin Description
Ground
3.3 V (+3.3 Volts)
No Connect
PERn3 (PCIe RX Lane 3 Negative)
PERp3 (PCIe RX Lane 3 Positive)
PETn3 (PCIe TX Lane 3 Negative)
PETp3 (PCIe TX Lane 3 Positive)
PERn2 (PCIe RX Lane 2 Negative)
PERp2 (PCIe RX Lane 2 Positive)
PETn2 (PCIe TX Lane 2 Negative)
PETp2 (PCIe TX Lane 2 Positive)
PERn1 (PCIe RX Lane 1 Negative)
PERp1 (PCIe RX Lane 1 Positive)
PETn1 (PCIe TX Lane 1 Negative)
PETp1 (PCIe TX Lane 1 Positive)
PERn0 (PCIe RX Lane 0 Negative)
PERp0 (PCIe RX Lane 0 Positive)
PETn0 (PCIe TX Lane 0 Negative)
PETp0 (PCIe TX Lane 0 Positive)
PWRDIS (Power Disable)
PLN# (Power Loss Notification)
LED_1# (Grounded on CLB)
VIO_1.8V
PLA_S3# (Power Loss Acknowledge)
USB_D+ (USB Data Positive)
USB_D- (USB Data Negative)
SMB_CLK (SMBus Clock)
SMB_DATA (SMBus Data)
ALERT# (Alert Notification to initiator)
PERST# (PCIe Reset)
CLKREQ# (Clock Request)
REFCLKN (Reference Clock Negative)
PEWAKE# (PCIe Wake)
REFCLKP (Reference Clock Positive)
MFG_CLOCK (Vendor Specific / Mfg. Pin)
MFG_DATA (Vendor Specific / Mfg. Pin)
Key-M
SUSCLK (Suspend Clock)
PEDET (Interface Detect)
VIO_CFG
Connector Pin Number
1, 3, 9, 15, 21, 27, 32, 33, 38, 39, 45, 51, 57, 71, 75
2, 4, 12, 14, 16, 18, 70, 72, 74
20, 24, 26, 28, 46, 48, 67
5
7
11
13
17
19
23
25
29
31
35
37
41
43
47
49
6
8
10
22
30
34
36
40
42
44
50
52
53
54
55
56
58
Displaced pins: 59, 60, 61, 62, 63, 64, 65, 66
68
69
73
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©2023 Wilder Technologies, LLC
Document No. 910-0077-000 Rev. B
System DUT Destination
GND
NC
NC
PERn3
PERp3
PETn3
PETp3
PERn2
PERp2
PETn2
PETp2
PERn1
PERp1
PETn1
PETp1
PERn0
PERp0
PETn0
PETp0
NC
NC
LED_1#
NC
NC
NC
NC
NC
NC
NC
NC
NC
DEV RCLK-
NC
DEV RCLK+
NC
NC
N/A
NC
NC
VIO_CFG