Bose SoundDock 10 Service Manual page 62

Sync Clock Distribution
DSP supplies PA_SYNCH_CLK, a 3.3V, 50% duty cycle clock for synchronizing
switching amplifiers to 6x 48kHz audio sample rate (288kHz)
PA_SYNCH_CLK routed directly to TPA3100
TDF8599 needs 4V minimum level for sync clock, requires buffering through HCT
NOR gate (U200) to provide a 5V logic swing.
Charging Standby
Supply voltage controlled to +24V
Amplifiers muted (AMP_MUTE held high by DSP)
AMP_STANDBY held high (amps active)
TDF8599 continues to switch, TPA3100 does not
Low Power Standby
Supply voltage controlled to +7V
AMP_STANDBY held low (amps inactive)
Both Amplifier ICs employ internal fault detection
TDF8599
Pulls DIAG signal low on short circuit detect, over-current, over-
temperature, or over/under-voltage
Exact cause of fault reported on I2C bus (not available on SoundDock 10)
TPA3100
Sets FAULT pin high on short circuit detect
FAULT detect may also be caused by overheating
Both ICs clear faults when fault-producing condition is removed
SoundDock 10 Theory of Operation
Low Power Modes
Fault Detection
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