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SECTION IV
THEORY OF OPERATION
4-1
INTRODUCTION
4-2
This section explains the theory of operation for the
Digital Output card. The theory assumes that the reader is
familiar with the instruction set and the basic operation of the
6942A
Multiprogrammer.
First, a brief description is given
covering the basic operation and features of the card. A detail-
ed block diagram discussion then follows.
This section con-
cludes with an example of the processing of an output bit in-
struction.
4-3
OVERALL
OPERATION
4-4
Power Turn-On
4-5
When power is applied to the Digital Output card, the
circuits on the card are first cleared. A power-up delay circuit
holds the 16-output data lines at logic low (or logic high if
jumper W51 is installed) until +5 V is reached {within a few
milliseconds). A self-test is then initiated by the Multiprogram-
mer to test the circuits of the Digital Output card. The self-ID,
data type, size, and LSB parameters of the card are read and
stored in Multiprogrammer memory as part of the wake-up se-
quence.
4-6
First Rank Storage
4-7
` When the Digital Output card is addressed in any out-
put type instruction (OP, OS, OB, Oi, WC, or WF), a 16-bit
data word is'sent to the card and is stored in a register called
first rank storage. The data word in first rank storage can be
read at any time with a Read Value (RV) instruction. If a WF
output instruction were issued at the controller, this instruc-
tion would be completed with the loading of first rank storage.
For any other output instruction, a "cycle" operation (describ-
ed in the next paragraph) begins shortly after the data word is
loaded into first rank storage.
4-8
Cycling The Card
4-9
In a cycle operation, the 16-bit data word in first rank
storage is transferred to a second register called second rank
storage. Immediately after this transfer, several events take
place simultaneously as part of the cycling operation:
a.
A CARD ENABLE signal goes high (if not already
high from a previous cycle) and allows the data word
in second rank storage to select the data lines. A "1"
(or high) in any bit position of the data word in se-
cond rank storage makes the data line associated
with that bit position a logic high. A "0" (or low) in
any bit position makes the data line a logic tow. The
data lines remain at the selected logic levels until: (1)
4-1
they
are
re-programmed,
(2) a power-up
reset
occurs,
{3} a Sytem
Disabile
(SD)
instruction
is
issued, or (4) the External Enable line at the edge
connector is made iow.
b.
BUSY and GATE signals go high and are sent to the
external edge connector. BUSY indicates
that the
data lines are currently being selected. GATE is an
ancillary signal that can be used by the external logic
to trigger a read data-lines operation
410
As mentioned previously, a cycle operation occurs
automatically for all output instructions except a WF instruc-
tion, With a WF instruction, the cycle operation is normally in-
itiated in one of two ways. {See Figure 4-1):
$
By the controller by issuing a Cycle (CY) instruction
to specifically cycle the card, or
2.
Externally at the external interface connector by ap-
pling an EXTERNAL TRIGGER signal. When an Ex-
ternal Trigger is applied, an additional signal called
TRIGGER POLARITY SELECT determines whether
cycling will occur on the low-to-high or high-to-low
transition of the External Trigger pulse.
PROGRAM
SERVICES:
oper
[oman
E
A) INSTRUCTION
CYCLES
CARD
PROGRAM
SERVICES
INTERRUPT
i
8) EXTERNALLY
SUPPLIED TRIGGER PULSE
(EXT) CYCLES CARD
Figure 4-1. Card Cycling and BUSY/EOP Timing
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