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6.3 Power ON/OFF Sequence
To prevent a latch-up or DC operation of the LCD Module, the power on/off
sequence should be as the diagram below.
300㎲≤T1≤10msec
0≤T2≤50msec
0≤T3≤50msec
1sec≤T4
Back-Light
(Recommended)
500msec≤T5
100msec≤T6
The supply voltage of the external system for the Module input should be the same
as the definition of V
Apply the lamp voltage within the LCD operation range. When the back light turns on
before the LCD operation or the LCD turns off before the back light turns off,
the display may momentarily show abnormal screen.
In case of V
DD
please keep the level of input signals low or keep a high impedance.
T4 should be measured after the Module has been fully discharged between power off
and on period.
Interface signal should not be kept at high impedance when the power is on.
MODEL
LTM220MT05
T1 : V
rising time from 10% to 90%
DD
T2 : The time from V
DD
T3 : The time from valid data off to V
T4 : V
off time for Windows restart
DD
T5 : The time from valid data to B/L enable at power ON.
T6 : The time from valid data off to B/L disable at power Off.
.
DD
= off level,
Doc. No
to valid data at power ON.
off at power Off.
DD
05-000-G-080902
Approval Specification
Approval Specification
Page
29/39
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